Wade Fife 23b44d6538 fpga: tools: Add do file for ModelSim ...

Original-commit: 99982799869267550844d34a64fe82dfb1aaa79d

2024-10-08 18:15:52 -05:00

export/x300/radio

Fix instances of sim preamble

2024-09-17 08:43:22 -05:00

lib

Fix instances of sim preamble

2024-09-17 08:43:22 -05:00

sim

fpga: sim: Initialize test_status

2024-06-20 11:35:27 +02:00

tools

fpga: tools: Add do file for ModelSim

2024-10-08 18:15:52 -05:00

top

Fix instances of sim preamble

2024-09-17 08:43:22 -05:00

.gitignore

fpga: Add more spurious files to gitignore

2023-12-13 17:28:09 -06:00

build.py

fpga: Replace references to python -> python3

2023-12-05 15:43:08 -06:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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84 MiB

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Verilog 42.5%

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SystemVerilog 12%

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Other 11.6%