Wade Fife
c322899053
This adds DRAM support to E31x devices. Due to the size of the DDR3 memory controller, it is not enabled by default. You can include the memory controller IP in the build by adding the DRAM environment variable to your build. For example: DRAM=1 make E310_SG3 Original-commit: 788fef11ef890c6dcee3be495fc381bcf2990d3b
129 lines
3.9 KiB
PHP
129 lines
3.9 KiB
PHP
#
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# Copyright 2008-2012 Ettus Research LLC
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#
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##################################################
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# Project Setup
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##################################################
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TOP_MODULE = <Input arg>
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# NAME = <Input arg>
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# PART_ID = <Input arg>
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# ARCH = <Input arg>
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##################################################
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# Include other makefiles
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##################################################
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BASE_DIR = $(abspath ..)
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IP_DIR = $(abspath ./ip)
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include $(BASE_DIR)/../tools/make/viv_design_builder.mak
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include $(IP_DIR)/Makefile.inc
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include ../n3xx/coregen_dsp/Makefile.srcs
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include $(LIB_DIR)/ip/Makefile.inc
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include $(LIB_DIR)/hls/Makefile.inc
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include $(LIB_DIR)/control/Makefile.srcs
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include $(LIB_DIR)/fifo/Makefile.srcs
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include $(LIB_DIR)/axi/Makefile.srcs
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include $(LIB_DIR)/xge_interface/Makefile.srcs
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include $(LIB_DIR)/timing/Makefile.srcs
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include $(LIB_DIR)/packet_proc/Makefile.srcs
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include $(LIB_DIR)/dsp/Makefile.srcs
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include $(LIB_DIR)/io_cap_gen/Makefile.srcs
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include $(LIB_DIR)/rfnoc/Makefile.srcs
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# For the sake of convenience, we include the Makefile.srcs for the DDC, DUC,
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# radio, replay and FIFO blocks. Any other block needs to use the
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# RFNOC_OOT_MAKEFILE_SRCS variable (see below).
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_replay/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs
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# If out-of-tree modules want to be compiled into this image, then they need to
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# pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files.
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# Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual
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# source files.
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-include $(RFNOC_OOT_MAKEFILE_SRCS)
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IMAGE_CORE ?= $(DEFAULT_RFNOC_IMAGE_CORE_FILE)
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EDGE_FILE ?= $(DEFAULT_EDGE_FILE)
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##################################################
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# Sources
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##################################################
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TOP_SRCS = \
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ppsloop.v \
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axi_pmu.v \
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spi_slave.v
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ifneq (IDLE,$(findstring IDLE, $(EXTRA_DEFS)))
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TOP_SRCS += e31x.v
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TOP_SRCS += e31x_core.v
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TOP_SRCS += e31x_dram.v
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TOP_SRCS += e310_io.v
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TOP_SRCS += $(EDGE_FILE) $(IMAGE_CORE)
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MB_XDC = \
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e31x_pins.xdc \
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e31x_timing.xdc
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else
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TOP_SRCS += e31x_idle.v
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MB_XDC = \
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e31x_idle_pins.xdc
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endif
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DRAM_SRCS = $(IP_DRAM_XCI_SRCS)
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# The XDC files must be read in a specific order, motherboard first and then daughterboard.
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# Outside of that, all the other sources can be read in any order desired.
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DESIGN_SRCS = \
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$(abspath $(TOP_SRCS)) \
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$(CONTROL_LIB_SRCS) \
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$(IP_XCI_SRCS) \
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$(XGE_INTERFACE_SRCS) \
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$(PACKET_PROC_SRCS) \
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$(AXI_SRCS) \
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$(FIFO_SRCS) \
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$(AURORA_PHY_SRCS) \
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$(BD_SRCS) \
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$(RADIO_SRCS) \
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$(RFNOC_SRCS) \
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$(TIMING_SRCS) \
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$(VITA_SRCS) \
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$(CAT_CAP_GEN_SRCS) \
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$(DRAM_SRCS) \
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$(COREGEN_DSP_SRCS) \
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$(DSP_SRCS) \
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$(LIB_IP_XCI_SRCS) \
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$(LIB_HLS_IP_SRCS) \
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$(EXTRAM_SRCS) \
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$(CAP_GEN_GENERIC_SRCS) \
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$(RFNOC_OOT_SRCS)\
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$(RFNOC_FRAMEWORK_SRCS) $(RFNOC_BLOCK_NULL_SRC_SINK_SRCS) \
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$(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) $(RFNOC_BLOCK_RADIO_SRCS) \
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$(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \
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$(RFNOC_BLOCK_REPLAY_SRCS) \
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$(RFNOC_BLOCK_EXAMPLE_SRCS) \
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$(abspath $(MB_XDC))
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EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(call RESOLVE_PATH,$(EDGE_FILE))"
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##################################################
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# Dependency Targets
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##################################################
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.SECONDEXPANSION:
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VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF)
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# DESIGN_SRCS and VERILOG_DEFS must be defined
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bin: .prereqs $$(DESIGN_SRCS) ip
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$(call BUILD_VIVADO_DESIGN,$(abspath ./build_e31x.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID))
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synth: .prereqs $$(DESIGN_SRCS) ip
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$(call BUILD_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_synth.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID))
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rtl: .prereqs $$(DESIGN_SRCS) ip
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$(call CHECK_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_check_syntax.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID))
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.PHONY: bin rtl
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