Ryan Volz 1451ae066b fpga/usrp3: Fix DC truncation bias by adding rounding to DDC chain. ...

A digital DC bias caused by various truncations in the DDC chain was
previously noticable with small signal levels, especially with high
decimation rates. This patch eliminates the bias by replacing the
truncation with rounding or simply keeping more bits for longer where it
makes sense.

This is essentially a forward port of a similar prior fix to the usrp2
DDC chain: https://github.com/EttusResearch/fpga/pull/4.

Signed-off-by: Ryan Volz <ryan.volz@gmail.com>


Original-commit: a57c162a0d11ab82a83c911a94272ceb6f7ff70a

2024-06-11 10:20:08 +02:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga/usrp3: Fix DC truncation bias by adding rounding to DDC chain.

2024-06-11 10:20:08 +02:00

sim

fpga: rfnoc: Enable blocks with no inputs/outputs

2024-05-27 17:05:06 +02:00

tools

image builder: Add --build-ip-dir option

2024-06-11 10:20:08 +02:00

top

image builder: Add --build-ip-dir option

2024-06-11 10:20:08 +02:00

.gitignore

fpga: Add more spurious files to gitignore

2023-12-13 17:28:09 -06:00

build.py

fpga: Replace references to python -> python3

2023-12-05 15:43:08 -06:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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