147 lines
3.9 KiB
Verilog
147 lines
3.9 KiB
Verilog
//
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// Copyright 2023 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: qsfp_led_controller
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//
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// Description:
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//
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// Translate the active and link status LED signals on FPGA to control port
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// requests in order to transfer them to the CPLD, which drives the LEDs.
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//
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// Parameters:
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//
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// LED_REGISTER_ADDRESS : Address of LED register within CPLD.
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//
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`default_nettype none
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module qsfp_led_controller #(
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parameter LED_REGISTER_ADDRESS = 0
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) (
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// Common ControlPort signals
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input wire ctrlport_clk,
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input wire ctrlport_rst,
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// ControlPort request
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output reg m_ctrlport_req_wr,
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output wire m_ctrlport_req_rd,
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output wire [19:0] m_ctrlport_req_addr,
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output wire [31:0] m_ctrlport_req_data,
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output wire [ 3:0] m_ctrlport_req_byte_en,
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// ControlPort response
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input wire m_ctrlport_resp_ack,
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input wire [ 1:0] m_ctrlport_resp_status,
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input wire [31:0] m_ctrlport_resp_data,
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// QSFP port LED signals
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input wire [3:0] qsfp0_led_active,
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input wire [3:0] qsfp0_led_link,
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input wire [3:0] qsfp1_led_active,
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input wire [3:0] qsfp1_led_link
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);
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`include "../../lib/rfnoc/core/ctrlport.vh"
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//----------------------------------------------------------
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// Transfer LED signals to local clock domain
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//----------------------------------------------------------
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wire [15:0] led_combined;
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synchronizer #(
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.WIDTH (16),
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.STAGES (2),
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.INITIAL_VAL (0),
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.FALSE_PATH_TO_IN (1)
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) synchronizer_i (
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.clk (ctrlport_clk),
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.rst (ctrlport_rst),
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.in ({qsfp1_led_active, qsfp1_led_link, qsfp0_led_active, qsfp0_led_link}),
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.out (led_combined)
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);
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//----------------------------------------------------------
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// State machine to initialize and update LED status
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//----------------------------------------------------------
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localparam COUNT_W = 8;
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localparam MAX_COUNT = 2**COUNT_W-1;
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// This counter ensures the we have a delay before we attempt to initialize
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// the LED state and limits the rate at which the LEDs update.
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reg [COUNT_W-1:0] startup_count = 0;
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localparam ST_INIT = 0;
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localparam ST_WRITE = 1;
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localparam ST_WAIT_ACK = 2;
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localparam ST_IDLE = 3;
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reg [1:0] state = ST_INIT;
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reg [15:0] led_combined_delayed;
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always @(posedge ctrlport_clk) begin
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m_ctrlport_req_wr <= 0;
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led_combined_delayed <= led_combined;
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case (state)
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ST_INIT : begin
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// Set LED state after a delay
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startup_count <= startup_count + 1;
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if (startup_count == MAX_COUNT) begin
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state <= ST_WRITE;
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end
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end
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ST_WRITE : begin
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// Start an LED update request
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m_ctrlport_req_wr <= 1;
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state <= ST_WAIT_ACK;
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end
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ST_WAIT_ACK : begin
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// Wait for the acknowledgment from the bus
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if (m_ctrlport_resp_ack) begin
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if (m_ctrlport_resp_status != CTRL_STS_OKAY) begin
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// Status was bad, so try again after a delay
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state <= ST_INIT;
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end else begin
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state <= ST_IDLE;
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end
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end
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end
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ST_IDLE : begin
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// Wait here until the LED status changes
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if (led_combined != led_combined_delayed) begin
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state <= ST_INIT;
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end
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end
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endcase
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if (ctrlport_rst) begin
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state <= ST_INIT;
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startup_count <= 0;
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m_ctrlport_req_wr <= 0;
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led_combined_delayed <= 0;
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end
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end
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//----------------------------------------------------------
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// Static ControlPort assignments
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//----------------------------------------------------------
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assign m_ctrlport_req_rd = 0;
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assign m_ctrlport_req_byte_en = 4'b0011;
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assign m_ctrlport_req_addr = LED_REGISTER_ADDRESS;
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assign m_ctrlport_req_data = {16'b0, led_combined_delayed};
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endmodule
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`default_nettype wire
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