Martin Braun
ec4fab0340
- 2to3 was used to convert the Python scripts, except where the tool choked and manual intervention was required - All references to "python" where replaced with "python3" - buffer() was replaced by memoryview() Original-commit: ca68195b5d12c5410cfac8d459a0b0902c4c72c7
337 lines
16 KiB
Python
Executable File
337 lines
16 KiB
Python
Executable File
#! /usr/bin/env python3
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import sys
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import os
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import collections
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import argparse
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import re
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from functools import reduce
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#------------------------------------------------------------
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# Types
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#------------------------------------------------------------
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# Terminal definiion for each reference designator
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terminal_t = collections.namedtuple('terminal_t', 'name pin')
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# FPGA pin definiion
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fpga_pin_t = collections.namedtuple('fpga_pin_t', 'name loc iotype bank')
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# A (ref designator -> terminals) map
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# For each reference designator, this class maintains a list of all terminals
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# including names and pin locations. It also maintains a reverse mapping for all
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# terminal names to reference designator
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class terminal_db_t:
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def __init__(self):
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self.db = dict()
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self.rev_db = dict()
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def add(self, ref_des, net_name, pin_name):
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if ref_des in self.db:
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self.db[ref_des].append(terminal_t(net_name, pin_name))
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else:
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self.db[ref_des] = [terminal_t(net_name, pin_name)]
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if net_name in self.rev_db:
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self.rev_db[net_name].append(ref_des)
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else:
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self.rev_db[net_name] = [ref_des]
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def get_terminals(self, ref_des):
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return self.db[ref_des]
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def lookup_endpoints(self, net_name):
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return self.rev_db[net_name]
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# A (component -> properties) map
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# For each component, this class maintains all properties that are
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# listed in the RINF file
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class component_db_t:
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def __init__(self):
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self.db = dict()
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def add_comp(self, ref_des, name):
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self.db[ref_des] = {'Name':name}
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def add_attr(self, ref_des, prop, value):
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self.db[ref_des][prop] = value
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def exists(self, comp_name):
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return comp_name in self.db
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def lookup(self, comp_name):
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return self.db[comp_name]
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def attr_exists(self, comp_name, attr_name):
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return self.exists(comp_name) and attr_name in self.db[comp_name]
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def get_attr(self, comp_name, attr_name):
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return self.db[comp_name][attr_name]
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# An FPGA (pin location -> properties) map
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# For each FPGA pin location, this class maintains a list of various pin properties
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# Also maintans all the IO Types to aid in filtering
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class fpga_pin_db_t:
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def __init__(self, pkg_file, io_exclusions = []):
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print('INFO: Parsing Xilinx Package File ' + pkg_file + '...')
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header = ['Pin','Pin Name','Memory Byte Group','Bank','VCCAUX Group','Super Logic Region','I/O Type','No-Connect']
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self.pindb = dict()
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self.iodb = set()
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with open(pkg_file, 'r') as pkg_f:
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for line in iter(pkg_f.readlines()):
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tokens = collapse_tokens(line.strip().split(' '))
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if len(tokens) == 8:
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if tokens != header:
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pin_info = dict()
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for col in range(1, len(header)):
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pin_info[header[col].strip()] = tokens[col].strip()
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self.pindb[tokens[0].strip()] = pin_info
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self.iodb.add(pin_info['I/O Type'])
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if len(list(self.pindb.keys())) == 0 or len(self.iodb) == 0:
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print('ERROR: Could not parse Xilinx package file ' + pkg_file)
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sys.exit(1)
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print('INFO: * Found IO types: ' + ', '.join(self.iodb))
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self.iodb.remove('NA')
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for io in io_exclusions:
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if io:
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self.iodb.remove(io.rstrip().lstrip())
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print('INFO: * Using IO types: ' + ', '.join(self.iodb))
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def iface_pins(self):
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iface_pins = set()
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for pin in list(self.pindb.keys()):
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if self.pindb[pin]['I/O Type'] in self.iodb:
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iface_pins.add(pin)
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return iface_pins
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def is_iface_pin(self, pin):
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return (pin in self.pindb) and (self.pindb[pin]['I/O Type'] in self.iodb)
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def get_pin_attr(self, pin, attr):
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return self.pindb[pin][attr]
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#------------------------------------------------------------
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# Helper functions
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#------------------------------------------------------------
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# Parse command line options
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def get_options():
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parser = argparse.ArgumentParser(description='Generate a template IO location XDC and Verilog stub from an RINF netlist and a Xilinx package file.')
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parser.add_argument('--rinf', type=str, default=None, help='Input RINF netlist file (*.frs)')
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parser.add_argument('--xil_pkg_file', type=str, default=None, help='Input Xilinx package pinout file (*.txt)')
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parser.add_argument('--ref_des', type=str, default='U0', help='Reference designator for the FPGA')
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parser.add_argument('--xdc_out', type=str, default='output.xdc', help='Output XDC file with location constraints')
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parser.add_argument('--vstub_out', type=str, default=None, help='Output Verilog stub file with the portmap')
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parser.add_argument('--exclude_io', type=str, default='MIO,DDR,CONFIG', help='Exlcude the specified FPGA IO types from consideration')
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parser.add_argument('--suppress_warn', action='store_true', default=False, help='Suppress sanity check warnings')
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parser.add_argument('--traverse_depth', type=int, default=1, help='How many linear components to traverse before finding a named net')
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parser.add_argument('--fix_names', action='store_true', default=False, help='Fix net names when writing the XDC and Verilog')
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args = parser.parse_args()
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if not args.xil_pkg_file:
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print('ERROR: Please specify a Xilinx package file using the --xil_pkg_file option\n')
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parser.print_help()
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sys.exit(1)
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if not args.rinf:
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print('ERROR: Please specify an input RINF file using the --rinf option\n')
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parser.print_help()
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sys.exit(1)
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return args
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# Remove empty string from a token array
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def collapse_tokens(tokens):
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retval = []
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for tok in tokens:
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tok = tok.rstrip().lstrip()
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if tok:
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retval.append(tok)
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return retval
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# Parse user specified RINF file and return a terminal and component database
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def parse_rinf(rinf_path, suppress_warnings):
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print('INFO: Parsing RINF File ' + rinf_path + '...')
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terminal_db = terminal_db_t()
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component_db = component_db_t()
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with open(rinf_path, 'r') as rinf_f:
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net_name = '<UNDEF>'
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state = '<UNDEF>'
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line_num = 0
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for line in iter(rinf_f.readlines()):
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tokens = collapse_tokens(line.strip().split())
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line_num = line_num + 1
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if tokens:
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if tokens[0].startswith('.'):
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# State transition
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state = tokens[0]
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if state == '.ADD_COM':
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component_db.add_comp(tokens[1], tokens[3])
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elif state == '.ATT_COM':
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component_db.add_attr(tokens[1], tokens[2].strip('"'), tokens[3].strip('"'))
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elif state == '.ADD_TER':
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net_name = tokens[3].strip('"')
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terminal_db.add(tokens[1], net_name, tokens[2])
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elif state == '.TER':
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terminal_db.add(tokens[1], net_name, tokens[2])
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elif state == '.END':
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break
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else:
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# State continuation
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if state == '.TER':
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terminal_db.add(tokens[0], net_name, tokens[1])
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else:
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if not suppress_warnings:
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print('WARNING: Ignoring line continuation for ' + state + ' at line ' + str(line_num))
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return (terminal_db, component_db)
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# From all the FPGA pins filter out the ones
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# relevant for creating an XDC
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def filter_fpga_pins(ref_des, terminal_db, fpga_pin_db, max_level):
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terminals = terminal_db.get_terminals(ref_des)
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pins = dict()
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# Loop through all the terminals of the FPGA
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for fpga_term in terminals:
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term = fpga_term
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level = 0
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# For each net check if there is a valid (non $XXXXXX) name
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# If yes, use it. If not, then traverse one component down and check again
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# If the next net has a valid name, use that. One requirement for this
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# traversal is that the downstream components must form a linear network
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# i.e. no branching. As soon as this algorithm sees a brach, it aborts.
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while term and term.name.startswith('$') and level < max_level:
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level = level + 1
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comps = terminal_db.lookup_endpoints(term.name)
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if len(comps) == 2: #Check for branch
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next_comp = comps[1] if comps[0] == ref_des else comps[0]
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sec_terms = terminal_db.get_terminals(next_comp)
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if len(sec_terms) == 2: #Check for branch
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term = sec_terms[1] if sec_terms[0].name == term.name else sec_terms[0]
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break
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# At this point we either found a valid net of we reached the max_depth
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# Check again before approving this as a valid connection
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if term.name and (not term.name.startswith('$')) and fpga_pin_db.is_iface_pin(fpga_term.pin):
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iotype = fpga_pin_db.get_pin_attr(fpga_term.pin, 'I/O Type')
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bank = fpga_pin_db.get_pin_attr(fpga_term.pin, 'Bank')
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pins[term.name] = fpga_pin_t(term.name, fpga_term.pin, iotype, bank)
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return pins
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# Fix net names.
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# This function lists all the valid substitutions to make to net names
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def fix_net_name(name):
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return re.sub(r'[\W_]', '_', name)
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# Write an XDC file with sanity checks and readability enhancements
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def write_output_files(xdc_path, vstub_path, fpga_pins, fix_names):
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# Figure out the max pin name length for human readable text alignment
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max_pin_len = reduce(lambda x,y:max(x,y), list(map(len, list(fpga_pins.keys()))))
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# Create a bus database. Collapse multi-bit buses into single entries
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bus_db = dict()
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for pin in sorted(fpga_pins.keys()):
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m = re.search('([a-zA-Z0-9_()]+)\(([0-9]+)\)', pin)
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if m:
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bus_name = m.group(1)
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bit_num = int(m.group(2))
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if bus_name in bus_db:
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bus_db[bus_name].append(bit_num)
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else:
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bus_db[bus_name] = [bit_num]
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else:
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bus_db[pin] = []
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# Walk through the bus database and write the XDC file
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with open(xdc_path, 'w') as xdc_f:
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print('INFO: Writing template XDC ' + xdc_path + '...')
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for bus in sorted(bus_db.keys()):
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if not re.match("[a-zA-Z].[a-zA-Z0-9_]*$", bus):
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print('CRITICAL WARNING: Invalid net name (bad Verilog syntax): ' + bus +
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('. Possibly fixed but please review.' if fix_names else '. Please review.'))
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if bus_db[bus] == []:
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xdc_pin = fix_net_name(bus.upper()) if fix_names else bus.upper()
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xdc_loc = fpga_pins[bus].loc.upper().ljust(16)
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xdc_iotype = fpga_pins[bus].iotype
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xdc_iostd = ('<IOSTD_BANK' + fpga_pins[bus].bank + '>').ljust(16)
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xdc_f.write('set_property PACKAGE_PIN ' + xdc_loc + (' [get_ports {' + xdc_pin + '}]').ljust(max_pin_len+16) + '\n')
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xdc_f.write('set_property IOSTANDARD ' + xdc_iostd + ' [get_ports {' + xdc_pin + '}]\n')
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xdc_f.write('\n')
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else:
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bits = sorted(bus_db[bus])
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coherent = (bits == list(range(0, bits[-1]+1)))
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if not coherent:
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print('CRITICAL WARNING: Incoherent bus: ' + bus + '. Some bits may be missing. Please review.')
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for bit in bits:
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bus_full = bus + '(' + str(bit) + ')'
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xdc_pin = bus.upper() + '[' + str(bit) + ']'
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xdc_loc = fpga_pins[bus_full].loc.upper().ljust(16)
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xdc_iotype = fpga_pins[bus_full].iotype
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xdc_iostd = ('<IOSTD_BANK' + fpga_pins[bus_full].bank + '>').ljust(16)
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xdc_f.write('set_property PACKAGE_PIN ' + xdc_loc + (' [get_ports {' + xdc_pin + '}]').ljust(max_pin_len+16) + '\n')
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xdc_f.write('set_property IOSTANDARD ' + xdc_iostd + ' [get_ports {' + bus.upper() + '[*]}]\n')
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xdc_f.write('\n')
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# Walk through the bus database and write a stub Verilog file
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if vstub_path:
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with open(vstub_path, 'w') as vstub_f:
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print('INFO: Writing Verilog stub ' + vstub_path + '...')
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vstub_f.write('module ' + os.path.splitext(os.path.basename(vstub_path))[0] + ' (\n')
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i = 1
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for bus in sorted(bus_db.keys()):
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port_name = fix_net_name(bus.upper()) if fix_names else bus.upper()
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port_loc = fpga_pins[bus].loc.upper() if (bus_db[bus] == []) else '<Multiple>'
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port_dir_short = input('[' + str(i) + '/' + str(len(list(bus_db.keys()))) +'] Direction for ' + port_name + ' (' + port_loc + ')? {[i]nput,[o]utput,[b]oth}: ').lower()
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if port_dir_short.startswith('i'):
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port_dir = ' input '
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elif port_dir_short.startswith('o'):
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port_dir = ' output'
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else:
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port_dir = ' inout '
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if bus_db[bus] == []:
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vstub_f.write(port_dir + ' ' + port_name + ',\n')
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else:
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bus_def = str(sorted(bus_db[bus])[-1]) + ':0'
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vstub_f.write(port_dir + (' [' + bus_def + '] ').ljust(10) + port_name + ',\n')
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i = i + 1
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vstub_f.write(');\n\nendmodule')
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# Report unconnected pins
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def report_unconnected_pins(fpga_pins, fpga_pin_db):
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print('WARNING: The following pins were not connected. Please review.')
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# Collect all the pin locations that have been used for constrain/stub creation
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iface_pins = set()
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for net in list(fpga_pins.keys()):
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iface_pins.add(fpga_pins[net].loc)
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# Loop through all possible pins and check if we have missed any
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for pin in sorted(fpga_pin_db.iface_pins()):
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if pin not in iface_pins:
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print(' * ' + pin.ljust(6) + ': ' +
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'Bank = ' + str(fpga_pin_db.get_pin_attr(pin, 'Bank')).ljust(6) +
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'IO Type = ' + str(fpga_pin_db.get_pin_attr(pin, 'I/O Type')).ljust(10) +
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'Name = ' + str(fpga_pin_db.get_pin_attr(pin, 'Pin Name')).ljust(10))
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#------------------------------------------------------------
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# Main
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#------------------------------------------------------------
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def main():
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args = get_options();
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# Build FPGA pin database using Xilinx package file
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fpga_pin_db = fpga_pin_db_t(args.xil_pkg_file, args.exclude_io.split(','))
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# Parse RINF netlist
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(terminal_db, component_db) = parse_rinf(args.rinf, args.suppress_warn)
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# Look for desired reference designator and print some info about it
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print('INFO: Resolving reference designator ' + args.ref_des + '...')
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if not component_db.exists(args.ref_des):
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print('ERROR: Reference designator not found in the netlist')
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sys.exit(1)
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fpga_info = component_db.lookup(args.ref_des)
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print('INFO: * Name = ' + fpga_info['Name'])
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print('INFO: * Description = ' + fpga_info['Description'])
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# Build a list of all FPGA interface pins in the netlist
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fpga_pins = filter_fpga_pins(args.ref_des, terminal_db, fpga_pin_db, args.traverse_depth)
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if not fpga_pins:
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print('ERROR: Could not cross-reference pins for ' + args.ref_des + ' with FPGA device. Are you sure it is an FPGA?')
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sys.exit(1)
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# Write output XDC and Verilog
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write_output_files(args.xdc_out, args.vstub_out, fpga_pins, args.fix_names)
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print('INFO: Output file(s) generated successfully!')
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# Generate a report of all unconnected pins
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if not args.suppress_warn:
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report_unconnected_pins(fpga_pins, fpga_pin_db)
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if __name__ == '__main__':
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main()
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