Sam Lane bd85dd37ff fpga: tools: Add assert option to synthesis ...

Add -assert option to Vivado synthesis to allow VHDL assert statements
to be checked during synthesis.


Original-commit: 13d004fa9001823e807c4a2b72e92b20efb6f94a

2025-04-03 11:01:14 -05:00

..

make

fpga: tools: Add support for Questa

2025-03-17 13:40:26 -05:00

scripts

fpga: tools: Add assert option to synthesis

2025-04-03 11:01:14 -05:00

utils

fpga: tools: Fix issues in run_testbenches.py

2025-03-14 08:03:34 +01:00