miegl/b210-k7-fpga
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f19fa3cf827cb00a1fff3f4e9e7320a9675ff6eb
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3 Commits
Author SHA1 Message Date
Wade Fife e659f0cfdd Fix instances of sim preamble 
Original-commit: d6ba2dfb5cb524ba2116cb0c3613af9650e57d03
 2024-09-17 08:43:22 -05:00
Wade Fife 38e4708a4a fpga: Remove stale references to UHD_FPGA_DIR 
Original-commit: 8c0c30642d47d17e2fa9d168b462d7ace18cc3d4
 2021-09-08 08:36:05 -05:00
Wade Fife 2eb71626fb fpga: rfnoc: Add Signal Generator RFNoC block 
Original-commit: 1e94f85b8bafc3f9acab7ef35d2675fa7e61f6f4
 2020-07-30 12:51:41 -05:00