miegl/b210-k7-fpga
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eb84b6c949dfb3df2d0f2499eb85d2fed36f2aef
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4 Commits
Author SHA1 Message Date
miegl 90e0b1d038 fifo: replace synthesized simulation FIFO 
Use the real axi_fifo_2clk hierarchy with XPM-based asynchronous FIFO implementations instead of synthesizing axi_fifo_2clk_sim.

Map the deep stream FIFOs into dedicated block RAM while preserving the legacy FWFT FIFO interface.
 2026-08-25 22:21:16 +02:00
miegl a83f31ec3b vivado: migrate Kintex-7 build to Vivado 2026.1 2026-08-24 17:53:26 +02:00
miegl 56604b2187 vivado: add reproducible 2024.1 project build 2026-08-24 17:50:44 +02:00
miegl 3dc3446559 b200: import original Kintex-7 clone port 2026-08-23 11:42:22 +02:00