Synchronize legacy and XPM reset indications into the FIFO read clock domain instead of feeding cross-domain reset logic into asynchronous PRE/CLR paths.
This removes the FIFO-induced CDC-10 findings while preserving legacy reset behavior.
Use the real axi_fifo_2clk hierarchy with XPM-based asynchronous FIFO implementations instead of synthesizing axi_fifo_2clk_sim.
Map the deep stream FIFOs into dedicated block RAM while preserving the legacy FWFT FIFO interface.
miegl