 Wade Fife
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0e65ae3c86
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fpga: x400: Add 1x64, 2x64, and 1x128 DRAM interconnect
Original-commit: daf1ed2ad2fbb72f16a9909fa75a0ba9e2879583
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2023-02-24 08:07:17 -06:00 |
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Wade Fife
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9a4a9645ad
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fpga: x400: Add axi_inter_4x64_512_bd IP
Original-commit: 129440913803de793b82ddbd7b6f5605dacb8aa3
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2022-02-07 13:08:11 -07:00 |
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Wade Fife
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f5b6a04e5c
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fpga: x400: Add axi_inter_2x128_512_bd IP
Original-commit: e88c447a1a890a38ee875c14ab55a713056709b9
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2022-02-07 13:08:11 -07:00 |
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61782b02d7
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fpga: x400: Add support for X410 motherboard FPGA
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com>
Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com>
Co-authored-by: Max Köhler <max.koehler@ni.com>
Co-authored-by: Michael Auchter <michael.auchter@ni.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>
Co-authored-by: Hector Rubio <hrubio@ni.com>
Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
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2021-06-10 11:56:58 -05:00 |
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