This updates the RFNoC image cores to separate the two DRAM banks on
X4xx by splitting them into "dram0" and "dram1". Previously, both DRAM
banks shared the same DRAM port, named "dram", which created some
confusion.
The Replay block has also been duplicated in the bitstreams that use
both banks, so we now have one Replay block per bank.
Original-commit: b5cfab8922e5b3f4ff13a8a64e8b0319876f13db
FPGA:
- Split up MB registers that control daughterboard specific settings so
that daughterboards 0 and 1 could have different setings, in
preparation for future devices that require different settings.
This requires a compat number bump to 8.0.
- Add registers for additional RFDC information, including the
block/tile mapping of the individual channels, and information about
resampling capabilities
- Identify sections of code that would be specific to X410/ZBX and move
them to their own headers, so it's trivial to add device-specific
sections of code instead for other devices in the future.
- This includes constraints for clocks and I/O pins.
- Remove ability to do timed ctrlport transactions to the MB CPLD, this
was unused and possibly broken.
- Move daughterboard-specific code into its own code location
(dboards/zbx)
- Move X410-specific register documentation to its own location
(doc/X410)
- Refactor Makefiles to split out X410/ZBX specific components and allow
switching between device types
- Add 512-bit AXI interconnects
- Make number of timekeepers configurable (X410 keeps the single
timekeeper)
MPM:
- Required compat is bumped to 8.0
- Now supports new registers for detecting DSP capabilities and
multi-rate settings for the daughterboards
- Adds MMCM controls (currently unused)
Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
Wade Fife