miegl/b210-k7-fpga
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8f64fb2ee8e3d8f5ee3932b62dde41a763b671f0
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5 Commits
Author SHA1 Message Date
Wade Fife 9ed8bb22d6 fpga: lib: Fix Vivado warnings 
Original-commit: ad3d614426e068a067692df411412ce3ed936c39
 2023-06-09 09:01:04 -05:00
Wade Fife 1756797ec2 fpga: lib: Fix NODE_INST parameter in eth_internal 
The NODE_INST parameter was set to 0. This adds it as a parameter so
that each transport adapter can have a unique node instance number.


Original-commit: c6bfd2e7f8313d727c2e557958f1b1ac2f674d98
 2022-08-29 17:01:45 -05:00
Wade Fife 032b9677aa fpga: lib: Add NET_CHDR_W parameter to transport adapters 
The NET_CHDR_W parameter tells the transport adapter what CHDR width
is used in transport packets, such as Ethernet packets. By default the
CHDR width used by the transport and RFNoC core will be the same. The
NET_CHDR_W parameter can be used in situations where the RFNoC core
expects a CHDR width from the transport adapter that is different from
that used over the network. In this situation, the transport adapter
will rewrite the CHDR packets so that each side gets the expected CHDR
width.


Original-commit: a9e49b7c587ef778ee0fe327e8bdcb15e0b0fc95
 2022-08-29 17:01:45 -05:00
Andrew Moch d7acf31a38 fpga: lib: add pause support to ethernet xport 
Original-commit: d099fc3b032250bcc70e4c24f78d5eb6508850e1
 2021-06-03 11:26:54 -05:00
Wade Fife feb849051f fpga: lib: Add eth_ipv4_internal 
This adds a generic version of eth_internal that allows you to specify
the CHDR width.


Original-commit: 30b522b268aed6e7b4bc1a556e88d2a4b2fe6f77
 2021-06-03 11:26:54 -05:00