Wade Fife
032b9677aa
The NET_CHDR_W parameter tells the transport adapter what CHDR width is used in transport packets, such as Ethernet packets. By default the CHDR width used by the transport and RFNoC core will be the same. The NET_CHDR_W parameter can be used in situations where the RFNoC core expects a CHDR width from the transport adapter that is different from that used over the network. In this situation, the transport adapter will rewrite the CHDR packets so that each side gets the expected CHDR width. Original-commit: a9e49b7c587ef778ee0fe327e8bdcb15e0b0fc95
446 lines
15 KiB
Systemverilog
446 lines
15 KiB
Systemverilog
//
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// Copyright 2020 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: eth_ipv4_internal
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//
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// Description:
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//
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// This internal Ethernet port is responsible for routing CHDR data between
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// the ARM CPU and RFNoC. Treating the RFNoC interface to the CPU like an
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// internal Ethernet device allows the ARM processor to take advantage of
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// highly optimized DMA engines and software designed for Ethernet. This
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// block also includes an ARP responder for IP address discovery.
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//
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// Prefixes are used to distinguish the various AXI-Stream buses:
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//
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// - e2h : Ethernet to Host (Ethernet transport adapter to ARM)
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// - h2e : Host to Ethernet (ARM to Ethernet transport adapter)
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// - e2v : Ethernet to CHDR (Ethernet transport to RFNoC)
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// - v2e : CHDR to Ethernet (RFNoC to Ethernet transport adapter)
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// - e2c : Ethernet to CPU (Ethernet transport adapter to ARP responder)
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// - c2e : CPU to Ethernet (ARP responder to Ethernet transport adapter)
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//
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// Parameters:
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//
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// CHDR_W : CHDR width used by RFNoC on the FPGA
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// NET_CHDR_W : CHDR width used over the network connection
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// BYTE_MTU : Sets the MTU to 2^BYTE_MTU bytes
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// DWIDTH : Data width for AXI-Lite interface (32 or 64)
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// AWIDTH : Address width for AXI-Lite interface
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// PORTNUM : Ethernet port number
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// RFNOC_PROTOVER : 16-bit RFNoC protocol version (major[7:0], minor[7:0])
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//
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`default_nettype none
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module eth_ipv4_internal #(
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parameter CHDR_W = 64,
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parameter NET_CHDR_W = CHDR_W,
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parameter BYTE_MTU = 10,
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parameter DWIDTH = 32,
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parameter AWIDTH = 14,
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parameter [ 7:0] PORTNUM = 0,
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parameter [15:0] RFNOC_PROTOVER = {8'd1, 8'd0}
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) (
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input wire bus_clk,
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input wire bus_rst,
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// AXI-Lite
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input wire s_axi_aclk,
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input wire s_axi_aresetn,
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input wire [AWIDTH-1:0] s_axi_awaddr,
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input wire s_axi_awvalid,
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output wire s_axi_awready,
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input wire [ DWIDTH-1:0] s_axi_wdata,
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input wire [DWIDTH/8-1:0] s_axi_wstrb,
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input wire s_axi_wvalid,
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output wire s_axi_wready,
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output wire [1:0] s_axi_bresp,
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output wire s_axi_bvalid,
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input wire s_axi_bready,
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input wire [AWIDTH-1:0] s_axi_araddr,
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input wire s_axi_arvalid,
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output wire s_axi_arready,
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output wire [DWIDTH-1:0] s_axi_rdata,
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output wire [ 1:0] s_axi_rresp,
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output wire s_axi_rvalid,
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input wire s_axi_rready,
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// Host DMA Interface
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output wire [ 63:0] e2h_tdata,
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output wire [ 7:0] e2h_tkeep,
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output wire e2h_tlast,
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output wire e2h_tvalid,
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input wire e2h_tready,
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input wire [ 63:0] h2e_tdata,
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input wire [ 7:0] h2e_tkeep,
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input wire h2e_tlast,
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input wire h2e_tvalid,
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output wire h2e_tready,
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// RFNoC Interface
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output reg [CHDR_W-1:0] e2v_tdata,
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output reg e2v_tlast,
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output reg e2v_tvalid,
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input wire e2v_tready,
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input wire [CHDR_W-1:0] v2e_tdata,
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input wire v2e_tlast,
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input wire v2e_tvalid,
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output reg v2e_tready,
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// Misc
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input wire [15:0] device_id
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);
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// The CPU (host DMA) interface is currently fixed at 64 bits, due to the
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// arp_responder and arm_framer/deframer only supporting 64 bits.
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localparam CPU_W = 64;
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//---------------------------------------------------------------------------
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// AXI-Lite to RegPort Register Access Bridge
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//---------------------------------------------------------------------------
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localparam REG_BASE_ETH_IO = 14'h0;
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localparam REG_BASE_ETH_SWITCH = 14'h1000;
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logic reg_wr_req;
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logic [AWIDTH-1:0] reg_wr_addr;
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logic [DWIDTH-1:0] reg_wr_data;
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logic reg_rd_req;
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logic [AWIDTH-1:0] reg_rd_addr;
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logic reg_rd_resp;
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logic [DWIDTH-1:0] reg_rd_data;
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axil_regport_master #(
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.DWIDTH (DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64)
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.AWIDTH (AWIDTH), // Width of the address bus
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.WRBASE (0), // Write address base
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.RDBASE (0), // Read address base
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.TIMEOUT (10) // Read will timeout after (2^TIMEOUT-1) cycles
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) eth_dma_reg_mst_i (
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// Clock and reset
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.s_axi_aclk (s_axi_aclk),
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.s_axi_aresetn (s_axi_aresetn),
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// AXI4-Lite: Write address port (domain: s_axi_aclk)
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.s_axi_awaddr (s_axi_awaddr),
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.s_axi_awvalid (s_axi_awvalid),
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.s_axi_awready (s_axi_awready),
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// AXI4-Lite: Write data port (domain: s_axi_aclk)
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.s_axi_wdata (s_axi_wdata),
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.s_axi_wstrb (s_axi_wstrb),
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.s_axi_wvalid (s_axi_wvalid),
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.s_axi_wready (s_axi_wready),
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// AXI4-Lite: Write response port (domain: s_axi_aclk)
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.s_axi_bresp (s_axi_bresp),
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.s_axi_bvalid (s_axi_bvalid),
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.s_axi_bready (s_axi_bready),
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// AXI4-Lite: Read address port (domain: s_axi_aclk)
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.s_axi_araddr (s_axi_araddr),
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.s_axi_arvalid (s_axi_arvalid),
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.s_axi_arready (s_axi_arready),
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// AXI4-Lite: Read data port (domain: s_axi_aclk)
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.s_axi_rdata (s_axi_rdata),
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.s_axi_rresp (s_axi_rresp),
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.s_axi_rvalid (s_axi_rvalid),
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.s_axi_rready (s_axi_rready),
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// Register port: Write port (domain: reg_clk)
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.reg_clk (bus_clk),
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.reg_wr_req (reg_wr_req),
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.reg_wr_addr (reg_wr_addr),
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.reg_wr_data (reg_wr_data),
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.reg_wr_keep (),
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// Register port: Read port (domain: reg_clk)
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.reg_rd_req (reg_rd_req),
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.reg_rd_addr (reg_rd_addr),
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.reg_rd_resp (reg_rd_resp),
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.reg_rd_data (reg_rd_data)
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);
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logic reg_rd_resp_eth_if;
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logic reg_rd_resp_io = 1'b0;
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logic [DWIDTH-1:0] reg_rd_data_eth_if;
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logic [DWIDTH-1:0] reg_rd_data_io = 'd0;
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// RegPort mux for responses
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regport_resp_mux #(
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.WIDTH (DWIDTH),
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.NUM_SLAVES (2)
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) reg_resp_mux_i (
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.clk (bus_clk),
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.reset (bus_rst),
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.sla_rd_resp ({reg_rd_resp_eth_if, reg_rd_resp_io}),
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.sla_rd_data ({reg_rd_data_eth_if, reg_rd_data_io}),
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.mst_rd_resp (reg_rd_resp),
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.mst_rd_data (reg_rd_data)
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);
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//---------------------------------------------------------------------------
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// ARM Framer/Deframer
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//---------------------------------------------------------------------------
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//
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// The arm_deframer removes bytes from the beginning of every packet sent by
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// the ARM processor to give the packets a specific alignment that will be
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// used later. The framer does the opposite, padding the packet before
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// sending it to the ARM CPU.
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//
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//---------------------------------------------------------------------------
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// Host Ethernet-to-CHDR
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logic [63:0] h2e_chdr_tdata;
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logic [3:0] h2e_chdr_tuser;
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logic h2e_chdr_tlast;
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logic h2e_chdr_tvalid;
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logic h2e_chdr_tready;
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//
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logic [63:0] e2h_chdr_tdata;
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logic [3:0] e2h_chdr_tuser;
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logic e2h_chdr_tlast;
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logic e2h_chdr_tvalid;
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logic e2h_chdr_tready;
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logic [3:0] e2h_tuser;
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logic [3:0] h2e_tuser;
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// Converting tuser to tkeep for ingress packets
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assign e2h_tkeep = ~e2h_tlast ? 8'b1111_1111
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: (e2h_tuser == 4'd0) ? 8'b1111_1111
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: (e2h_tuser == 4'd1) ? 8'b0000_0001
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: (e2h_tuser == 4'd2) ? 8'b0000_0011
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: (e2h_tuser == 4'd3) ? 8'b0000_0111
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: (e2h_tuser == 4'd4) ? 8'b0000_1111
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: (e2h_tuser == 4'd5) ? 8'b0001_1111
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: (e2h_tuser == 4'd6) ? 8'b0011_1111
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: 8'b0111_1111;
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// Convert tkeep to tuser for egress packets
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assign h2e_tuser = ~h2e_tlast ? 4'd0
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: (h2e_tkeep == 8'b1111_1111) ? 4'd0
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: (h2e_tkeep == 8'b0111_1111) ? 4'd7
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: (h2e_tkeep == 8'b0011_1111) ? 4'd6
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: (h2e_tkeep == 8'b0001_1111) ? 4'd5
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: (h2e_tkeep == 8'b0000_1111) ? 4'd4
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: (h2e_tkeep == 8'b0000_0111) ? 4'd3
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: (h2e_tkeep == 8'b0000_0011) ? 4'd2
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: (h2e_tkeep == 8'b0000_0001) ? 4'd1
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: 4'd0;
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arm_deframer arm_deframer_i (
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.clk (bus_clk),
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.reset (bus_rst),
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.clear (1'b0),
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.s_axis_tdata (h2e_tdata),
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.s_axis_tuser (h2e_tuser),
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.s_axis_tlast (h2e_tlast),
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.s_axis_tvalid (h2e_tvalid),
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.s_axis_tready (h2e_tready),
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.m_axis_tdata (h2e_chdr_tdata),
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.m_axis_tuser (h2e_chdr_tuser),
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.m_axis_tlast (h2e_chdr_tlast),
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.m_axis_tvalid (h2e_chdr_tvalid),
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.m_axis_tready (h2e_chdr_tready)
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);
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axi64_to_xge64 arm_framer_i (
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.clk (bus_clk),
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.reset (bus_rst),
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.clear (1'b0),
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.s_axis_tdata (e2h_chdr_tdata),
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.s_axis_tuser (e2h_chdr_tuser),
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.s_axis_tlast (e2h_chdr_tlast),
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.s_axis_tvalid (e2h_chdr_tvalid),
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.s_axis_tready (e2h_chdr_tready),
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.m_axis_tdata (e2h_tdata),
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.m_axis_tuser (e2h_tuser),
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.m_axis_tlast (e2h_tlast),
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.m_axis_tvalid (e2h_tvalid),
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.m_axis_tready (e2h_tready)
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);
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//---------------------------------------------------------------------------
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// Ethernet Interface
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//---------------------------------------------------------------------------
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// FPGA-side addresses for the ARP responder
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logic [47:0] my_mac;
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logic [31:0] my_ip;
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// ARP responder signals
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logic [63:0] e2c_tdata;
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logic [7:0] e2c_tkeep;
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logic e2c_tlast;
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logic e2c_tvalid;
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logic e2c_tready;
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//
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logic [63:0] c2e_tdata;
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logic [7:0] c2e_tkeep;
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logic c2e_tlast;
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logic c2e_tvalid;
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logic c2e_tready;
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localparam CPU_USER_W = $clog2(CPU_W/8)+1; // SOF + trailing bytes
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// Host DMA interfaces
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AxiStreamIf #(.DATA_WIDTH(CPU_W), .USER_WIDTH(CPU_USER_W), .TUSER(1), .TKEEP(0))
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e2h_chdr(bus_clk, bus_rst);
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AxiStreamIf #(.DATA_WIDTH(CPU_W), .USER_WIDTH(CPU_USER_W), .TUSER(1), .TKEEP(0))
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h2e_chdr(bus_clk, bus_rst);
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// RFNoC Interfaces
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AxiStreamIf #(.DATA_WIDTH(CHDR_W), .TUSER(0), .TKEEP(0))
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e2v_chdr(bus_clk, bus_rst);
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AxiStreamIf #(.DATA_WIDTH(CHDR_W), .TUSER(0), .TKEEP(0))
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v2e_chdr(bus_clk, bus_rst);
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// ARP Responder Interfaces
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AxiStreamIf #(.DATA_WIDTH(CPU_W), .TUSER(0), .TKEEP(1))
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e2c_chdr(bus_clk, bus_rst);
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AxiStreamIf #(.DATA_WIDTH(CPU_W), .TUSER(0), .TKEEP(1))
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c2e_chdr(bus_clk, bus_rst);
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// Translate between SystemVerilog interfaces and Verilog signals
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always_comb begin
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e2h_chdr_tdata = e2h_chdr.tdata;
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e2h_chdr_tlast = e2h_chdr.tlast;
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e2h_chdr_tvalid = e2h_chdr.tvalid;
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e2h_chdr_tuser = e2h_chdr.tuser;
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e2h_chdr.tready = e2h_chdr_tready;
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h2e_chdr.tdata = h2e_chdr_tdata;
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h2e_chdr.tlast = h2e_chdr_tlast;
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h2e_chdr.tvalid = h2e_chdr_tvalid;
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h2e_chdr.tuser = h2e_chdr_tuser;
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h2e_chdr_tready = h2e_chdr.tready;
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e2v_tdata = e2v_chdr.tdata;
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e2v_tlast = e2v_chdr.tlast;
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e2v_tvalid = e2v_chdr.tvalid;
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e2v_chdr.tready = e2v_tready;
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v2e_chdr.tdata = v2e_tdata;
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v2e_chdr.tlast = v2e_tlast;
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v2e_chdr.tvalid = v2e_tvalid;
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v2e_tready = v2e_chdr.tready;
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e2c_tdata = e2c_chdr.tdata;
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e2c_tlast = e2c_chdr.tlast;
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e2c_tkeep = e2c_chdr.tkeep;
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e2c_tvalid = e2c_chdr.tvalid;
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e2c_chdr.tready = e2c_tready;
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c2e_chdr.tdata = c2e_tdata;
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c2e_chdr.tlast = c2e_tlast;
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c2e_chdr.tkeep = c2e_tkeep;
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c2e_chdr.tvalid = c2e_tvalid;
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c2e_tready = c2e_chdr.tready;
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end
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eth_ipv4_interface #(
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.PROTOVER (RFNOC_PROTOVER),
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.CPU_FIFO_SIZE (BYTE_MTU),
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.CHDR_FIFO_SIZE (BYTE_MTU),
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.NODE_INST (0),
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.BASE (REG_BASE_ETH_SWITCH),
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.PREAMBLE_BYTES (6),
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.ADD_SOF (1),
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.ENET_W (CPU_W),
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.CPU_W (CPU_W),
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.CHDR_W (CHDR_W),
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.NET_CHDR_W (NET_CHDR_W)
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) eth_ipv4_interface_i (
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.bus_clk (bus_clk),
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.bus_rst (bus_rst),
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.device_id (device_id),
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.reg_wr_req (reg_wr_req),
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.reg_wr_addr (reg_wr_addr),
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.reg_wr_data (reg_wr_data),
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.reg_rd_req (reg_rd_req),
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.reg_rd_addr (reg_rd_addr),
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.reg_rd_resp (reg_rd_resp_eth_if),
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.reg_rd_data (reg_rd_data_eth_if),
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.eth_pause_req (),
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.eth_tx (e2h_chdr),
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.eth_rx (h2e_chdr),
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.e2v (e2v_chdr),
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.v2e (v2e_chdr),
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.e2c (e2c_chdr),
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.c2e (c2e_chdr),
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.my_udp_chdr_port (),
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.my_ip (my_ip),
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.my_mac (my_mac)
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);
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//---------------------------------------------------------------------------
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// ARP Responder
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//---------------------------------------------------------------------------
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//
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// This block sends replies to ARP IPv4 frames.
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//
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//---------------------------------------------------------------------------
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arp_responder arp_responder_i (
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.aclk (bus_clk),
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.aresetn (~bus_rst),
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.mac_addr (my_mac),
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.ip_addr (my_ip),
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.s_axis_tdata (e2c_tdata),
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.s_axis_tvalid (e2c_tvalid),
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.s_axis_tready (e2c_tready),
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.s_axis_tkeep (e2c_tkeep),
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.s_axis_tlast (e2c_tlast),
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.s_axis_tuser (1'b0),
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.m_axis_tdata (c2e_tdata),
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.m_axis_tvalid (c2e_tvalid),
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.m_axis_tready (c2e_tready),
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.m_axis_tkeep (c2e_tkeep),
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.m_axis_tlast (c2e_tlast),
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.m_axis_tuser ()
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);
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//---------------------------------------------------------------------------
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// NIXGE Registers
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//---------------------------------------------------------------------------
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//
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// Implement the minimum subset of registers needed by the NIXGE driver for
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// our internal Ethernet port. Only the NIXGE_REG_LED_CTL register is
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// actually used, but the internal adapter doesn't need LED control. So all
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// registers read as 0 and all writes are ignored.
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//
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//---------------------------------------------------------------------------
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// NIXGE Registers
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localparam REG_PORT_INFO = REG_BASE_ETH_IO + 'h0;
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localparam REG_MAC_CTRL_STATUS = REG_BASE_ETH_IO + 'h4;
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localparam REG_PHY_CTRL_STATUS = REG_BASE_ETH_IO + 'h8;
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localparam REG_MAC_LED_CTL = REG_BASE_ETH_IO + 'hC;
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|
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always @(posedge bus_clk) begin
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if (reg_rd_req) begin
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|
case(reg_rd_addr[AWIDTH-1:2])
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|
REG_PORT_INFO [AWIDTH-1:2] |
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|
REG_MAC_CTRL_STATUS[AWIDTH-1:2] |
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|
REG_PHY_CTRL_STATUS[AWIDTH-1:2] |
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|
REG_MAC_LED_CTL [AWIDTH-1:2]:
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reg_rd_resp_io <= 1'b1;
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default:
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|
reg_rd_resp_io <= 1'b0;
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|
endcase
|
|
end
|
|
end
|
|
|
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endmodule
|
|
|
|
`default_nettype wire
|