Commit Graph
5 Commits
Author SHA1 Message Date
Wade Fife fcfc6bf387 fpga: Update testbenches to work in ModelSim
Original-commit: 0076076467303247c4e62e5824e5bf8ce79cbe66
2021-06-17 08:16:59 -05:00
Wade Fife 4188b6ccbc fpga: lib: Add modports to SV AXI-Stream blocks
Original-commit: da46dddbebab2ddb1f25f2f200431c2299b395f4
2021-06-03 11:26:54 -05:00
Wade Fife ab09eb9b09 fpga: lib: Add clock domain comments to interfaces
Original-commit: c64258e09b221d0bfeb55e01085a20e37c5b62ba
2021-06-03 11:26:54 -05:00
Andrew Moch d7acf31a38 fpga: lib: add pause support to ethernet xport
Original-commit: d099fc3b032250bcc70e4c24f78d5eb6508850e1
2021-06-03 11:26:54 -05:00
Andrew Moch 23be04661f fpga: lib: Add synthesizable AXI4-Stream SV components
Components are connected together with AxiStreamIfc. Some features
include:
  (1) Add bytes to the start of a packet
  (2) Remove bytes from a packet
  (3) Wrappers for some older components
      a.  fifo - buffer but imediately pass a packet
      b.  packet_gate - buffer and hold till end of packet
      c.  width_conv - cross clock domains and change width of axi bus

The AxiStreamIf was moved from PkgAxiStreamBfm to its own file. It can
be used to connect to ports with continuous assignment.
AxiStreamPacketIf must be used procedurally but allows the following
new methods:
  - reached_packet_byte - notify when tdata contains a paritcular byte
  - get_packet_byte/get_packet_field - extract a byte or field from axi
  - put_packet_byte/put_packet_field - overwrite a byte or field onto axi


Original-commit: c3bca6c87700054c96320de119a58f6a688dbd5a
2020-06-25 14:44:04 -05:00