Commit Graph
10 Commits
Author SHA1 Message Date
Max Köhler 40ce83817a fpga: lib: add register stage in ipv4 chdr adapter
Original-commit: 2b9504d84d8f8e5dd7156498b4c8b5db5a2c84da
2025-02-05 09:14:26 -06:00
Wade Fife e4d9a9a448 fpga: lib: Allow buffering in eth_ipv4_chdr_adapter
Enable USE_AS_BUFF on packet gate to allow many packets to be buffered.
This reduces latency when several small packets are sent out close
together.


Original-commit: 32d348efe482d40c7090d8203a3c1374dfcb4a68
2023-10-18 22:23:55 -05:00
Wade Fife 564944ea93 fpga: lib: Fix IPv4 CHDR TUSER width
Fix the TUSER width for some buses in eth_ipv4_chdr_adapter. This
allows wider CHDR widths to be used with 10 GbE.


Original-commit: f0ed58f7518410fc174a6356c072dfb21e3de253
2023-06-11 12:58:25 -05:00
Wade Fife 6c4c231aa5 fpga: lib: Add ZPU support to SV transport adapter
Original-commit: 105d8d1661d76bfe7264798a691b061366c94898
2023-01-10 14:18:59 -08:00
Wade FifeandMartin Braun f2b4426b0f fpga: lib: Add advanced features to IPv4 SV transport adapter
This adds several features to the SystemVerilog Eth/IPv4/UDP transport
adaptor including:

- Compat register
- NODE_INST register
- Capabilities register
- KV map access for custom routing on RX data paths
- CHDR header removal for raw payloads to be sent over UDP

Also adds xport_adapter_ctrl.py, which allows controlling the new
registers.

Co-authored-by: Martin Braun <martin.braun@ettus.com>


Original-commit: 3c3da4c62f33d02bb05bcdc38e8929cbf2cdd9a3
2022-08-29 17:01:45 -05:00
Wade Fife 032b9677aa fpga: lib: Add NET_CHDR_W parameter to transport adapters
The NET_CHDR_W parameter tells the transport adapter what CHDR width
is used in transport packets, such as Ethernet packets. By default the
CHDR width used by the transport and RFNoC core will be the same. The
NET_CHDR_W parameter can be used in situations where the RFNoC core
expects a CHDR width from the transport adapter that is different from
that used over the network. In this situation, the transport adapter
will rewrite the CHDR packets so that each side gets the expected CHDR
width.


Original-commit: a9e49b7c587ef778ee0fe327e8bdcb15e0b0fc95
2022-08-29 17:01:45 -05:00
Wade Fife ab09eb9b09 fpga: lib: Add clock domain comments to interfaces
Original-commit: c64258e09b221d0bfeb55e01085a20e37c5b62ba
2021-06-03 11:26:54 -05:00
Andrew Moch d7acf31a38 fpga: lib: add pause support to ethernet xport
Original-commit: d099fc3b032250bcc70e4c24f78d5eb6508850e1
2021-06-03 11:26:54 -05:00
Andrew Moch f28357679e fpga: lib: Update xport_sv
- Detect dropped words at the dispatch level. This prevents
   an overflow on CHDR from block CPU.
 - Dropped packets are recorded as CPU or CHDR drop count
 - Refactor to put chdr_xport_adapter.sv in different clock
   domain to improve timing
 - Unwrinkle tkeep/trailing transitions


Original-commit: 7f86724ec3387f75d39d683b2ac5f5152e714c74
2020-08-05 17:18:12 -05:00
Andrew Moch 05eb1bc2f1 fpga: lib: Add width agnostic version of Ethernet Interface
The rnfoc/xport section is refactored in System Verilog to allow the
following improvements
(1) CPU_W - Sets the size of the c2e and e2c pipes.  This can be run
    at a different clock rate than the main ethernet pipe
(2) CHDR_W - Sets the size of the v2e and e2v pipes. This can be run
    at a different clock rate than the main ethernet pipe
(3) ENET_W - Sets the size of the eth_tx and eth_rx pipes.

eth_interface_tb runs traffic from e2c,e2v,v2e,c2e simultaneously
against the original xport_sv implementation, and against the new
implementation with widths of 64/128/512. A chdr_management node
info request queries the port info of the node0 in the eth_interface.

eth_ifc_synth_test.sv can be compiled with the make xsim target to test
out the size of various configurations.


Original-commit: eed4988cc266a63370a4332351d02fadedde3a3b
2020-06-30 10:29:35 -05:00