 Friedrich Wenisch
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3ed06cc861
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fpga: x400: refactor RFDC block diagrams and timing constraints
Original-commit: a7bce74be154de9a68d6bdf2f9a6651b480b6dfa
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2025-02-13 07:51:05 -06:00 |
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Max Köhler
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c12766fd4d
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fpga: x400: bump FPGA compat version to 9.0
Original-commit: 85ef95fd85f5fdd0eb8b7792443bf3b9ce4728cf
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2025-02-12 14:38:08 +01:00 |
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Max Köhler
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2a89218e95
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fpga: x400: add rf core ctrlport
Original-commit: a9add0a6a5baefe7dcc8fbb5a39f01dc935c7a3e
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2024-11-12 15:57:36 -06:00 |
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Max Köhler
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ea4f2ff009
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fpga: x440: refactor rf_core_full to use parameters on ports
Original-commit: 40bd20d240b2ee60ec58ad5a00a9ec9eebd1e9af
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2024-08-21 08:06:41 -05:00 |
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