miegl/b210-k7-fpga
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
589 Commits 1 Branch 0 Tags
b210-k7
Commit Graph
1 Commits
Author SHA1 Message Date
Ryan Marlow a90444c784 fpga: lib: Add clock_div module 
Module description:
Clock divider. Generates an output clock that is 1/N times the
frequency of the input clock.


Original-commit: 71bdcd22f07162687771d374178ad0372783bd45
 2023-04-05 15:10:14 -05:00