fpga: Update testbenches to work in ModelSim
Original-commit: 0076076467303247c4e62e5824e5bf8ce79cbe66
This commit is contained in:
Wade Fife
@@ -9,12 +9,9 @@
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir
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BASE_DIR = $(abspath ../../../../top)
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IP_DIR = $(BASE_DIR)/x400/ip
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# Include viv_sim_preamble after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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IP_BUILD_DIR = $(BASE_DIR)/x400/build-ip/xczu28drffvg1517-1e
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#-------------------------------------------------
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# Design Specific
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@@ -24,106 +21,122 @@ ARCH = zynquplusRFSOC
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PART_ID = xczu28dr/ffvg1517/-1/e
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# Include makefiles and sources for the DUT and its dependencies
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include $(BASE_DIR)/../lib/control/Makefile.srcs
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include $(BASE_DIR)/../lib/axi/Makefile.srcs
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include $(BASE_DIR)/../lib/axi4_sv/Makefile.srcs
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include $(BASE_DIR)/../lib/axi4s_sv/Makefile.srcs
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include $(BASE_DIR)/../lib/axi4lite_sv/Makefile.srcs
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include $(BASE_DIR)/../lib/packet_proc/Makefile.srcs
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include $(BASE_DIR)/../lib/xge_interface/Makefile.srcs
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include $(BASE_DIR)/../lib/xge/Makefile.srcs
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include $(BASE_DIR)/../lib/wb_spi/Makefile.srcs
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include $(BASE_DIR)/../lib/fifo/Makefile.srcs
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include $(BASE_DIR)/../lib/xge_interface/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/xport/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/xport_sv/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/crossbar/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
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include $(BASE_DIR)/../lib/xge/Makefile.srcs
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include $(IP_DIR)/Makefile.inc
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IP_AXI_ETH_DMA_BD_HDL_SIM_SRCS = $(wildcard $(addprefix $(IP_BUILD_DIR)/axi_eth_dma_bd/axi_eth_dma_bd/, \
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sim/axi_eth_dma_bd.v\
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ip/*/sim/*.h\
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ip/*/sim/*.v\
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ip/*/sim/*.vhd\
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ip/*/bd_0/hdl/*.v\
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ip/*/bd_0/sim/*.v\
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ip/*/bd_0/ip/ip_*/sim/*.v\
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ip/*/bd_0/ip/ip_*/sim/*.sv\
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ip/*/bd_0/ip/ip_*/sim/*.vhd\
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ipshared/*/hdl/*.sv\
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ipshared/*/hdl/*.v\
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ipshared/*/simulation/*.v\
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ipshared/*/hdl/verilog/*.v\
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ipshared/*/hdl/verilog/*.svh\
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ipshared/*/hdl/verilog/*.vh\
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))
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IP_AXI_INTERCONNECT_DMA_BD_HDL_SIM_SRCS = $(wildcard $(addprefix $(IP_BUILD_DIR)/axi_interconnect_dma_bd/axi_interconnect_dma_bd/, \
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ip/*/sim/*.v\
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))
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TOP_SRC = \
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$(abspath $(BASE_DIR)/x400/x4xx_qsfp_wrapper.sv) \
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$(abspath $(BASE_DIR)/x400/x4xx_qsfp_wrapper_temp.sv) \
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$(abspath $(BASE_DIR)/x400/x4xx_mgt_io_core.sv) \
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$(abspath $(BASE_DIR)/x400/x4xx.v)
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# Xilinx IP wants lots of libraries
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MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm
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# Needed for the HACK_SRC, speeds up the alignment phase (still long!)
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VLOG_ARGS = +define+SIM_SPEED_UP
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SVLOG_ARGS = -lint +define+BUILD_100G=1
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# Xilinx IP wants a second file loaded
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MODELSIM_ARGS = glbl -t 1fs
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DESIGN_SRCS = $(abspath \
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DESIGN_SRCS += $(abspath \
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$(AXI4_SV_SRCS) \
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$(AXI4S_SV_SRCS) \
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$(AXI4LITE_SV_SRCS) \
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$(FIFO_SRCS) \
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$(CONTROL_LIB_SRCS) \
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$(AXI_SRCS) \
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$(XGE_SRCS) \
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$(XGE_INTERFACE_SRCS) \
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$(PACKET_PROC_SRCS) \
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$(RFNOC_UTIL_SRCS) \
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$(RFNOC_XPORT_SRCS) \
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$(RFNOC_XPORT_SV_SRCS) \
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$(RFNOC_XBAR_SRCS) \
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$(RFNOC_CORE_SRCS) \
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$(WISHBONE_SRCS) \
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$(XGE_SRCS) \
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$(XGE_INTERFACE_SRCS) \
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)
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# Add files for the DUT
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DESIGN_SRCS += $(abspath \
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$(BASE_DIR)/x400/x4xx_mgt_io_core.sv \
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$(BASE_DIR)/x400/x4xx_qsfp_wrapper.sv \
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$(BASE_DIR)/x400/x4xx_qsfp_wrapper_temp.sv \
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)
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#-------------------------------------------------
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# IP Specific
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#-------------------------------------------------
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# If simulation contains IP, define the IP_DIR and point
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# it to the base level IP directory
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IP_DIR = ../../ip
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# Include makefiles and sources for all IP components
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# *after* defining the IP_DIR
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include $(IP_DIR)/axi_interconnect_eth_bd/Makefile.inc
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include $(IP_DIR)/axi_interconnect_dma_bd/Makefile.inc
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include $(IP_DIR)/axi_eth_dma_bd/Makefile.inc
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include $(IP_DIR)/xge_pcs_pma/Makefile.inc
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include $(IP_DIR)/eth_100g_bd/Makefile.inc
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DESIGN_SRCS += $(abspath \
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$(IP_AXI_INTERCONNECT_ETH_HDL_SRCS) \
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$(IP_AXI_INTERCONNECT_ETH_BD_SRCS) \
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$(IP_AXI_INTERCONNECT_DMA_HDL_SRCS) \
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$(IP_AXI_INTERCONNECT_DMA_BD_SRCS) \
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$(IP_AXI_ETH_DMA_BD_HDL_SRCS) \
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$(IP_AXI_ETH_DMA_BD_SRCS) \
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$(XGE_PCS_PMA_SRCS) \
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$(IP_100G_HDL_SRCS) \
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$(IP_100G_BD_SRCS) \
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)
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#-------------------------------------------------
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# ModelSim Specific
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#-------------------------------------------------
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IP_AXI_ETH_DMA_BD_HDL_SIM_SRCS = $(wildcard $(addprefix $(IP_BUILD_DIR)/axi_eth_dma_bd/axi_eth_dma_bd/, \
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sim/axi_eth_dma_bd.v \
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ip/*/sim/*.h \
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ip/*/sim/*.v \
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ip/*/sim/*.vhd \
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ip/*/bd_0/hdl/*.v \
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ip/*/bd_0/sim/*.v \
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ip/*/bd_0/ip/ip_*/sim/*.v \
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ip/*/bd_0/ip/ip_*/sim/*.sv \
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ip/*/bd_0/ip/ip_*/sim/*.vhd \
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ipshared/*/hdl/*.sv \
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ipshared/*/hdl/*.v \
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ipshared/*/simulation/*.v \
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ipshared/*/hdl/verilog/*.v \
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ipshared/*/hdl/verilog/*.svh \
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ipshared/*/hdl/verilog/*.vh \
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))
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IP_AXI_INTERCONNECT_DMA_BD_HDL_SIM_SRCS = $(wildcard $(addprefix $(IP_BUILD_DIR)/axi_interconnect_dma_bd/axi_interconnect_dma_bd/, \
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sim/*.v \
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ip/*/sim/*.v \
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))
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MISC_IP_SIM_SRCS += \
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$(VIVADO_PATH)/data/verilog/src/glbl.v \
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$(abspath $(IP_BUILD_DIR)/xge_pcs_pma/model_10gbe.sv) \
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DESIGN_SRCS += $(abspath \
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$(IP_AXI_ETH_DMA_BD_HDL_SIM_SRCS) \
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$(IP_AXI_INTERCONNECT_DMA_BD_HDL_SIM_SRCS) \
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$(IP_AXI_INTERCONNECT_ETH_HDL_SRCS) \
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$(IP_AXI_INTERCONNECT_DMA_HDL_SRCS) \
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$(IP_AXI_ETH_DMA_BD_HDL_SRCS) \
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$(IP_100G_HDL_SRCS) \
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$(AURORA_PHY_SRCS) \
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$(IP_HDL_SIM_SRCS) \
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$(TOP_SRC) \
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$(IP_AXI_INTERCONNECT_ETH_HDL_SIM_SRCS) \
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$(IP_100G_HDL_SIM_SRCS) \
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$(IP_XGE_PCS_PMA_HDL_SIM_SRCS) \
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$(MISC_IP_SIM_SRCS) \
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)
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# Xilinx IP wants lots of libraries
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MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm
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MODELSIM_ARGS += glbl -t 1fs
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# Needed for the HACK_SRC, speeds up the alignment phase (still long!)
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VLOG_ARGS += +define+SIM_SPEED_UP
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# Suppressing the following worthless reminder.
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#* Warning: M:/usrp4-hw/oss-repo/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv(228): (vlog-2583) [SVCHK] -
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# Extra checking for conflicts with always_comb and always_latch variables is done at vopt time
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SVLOG_ARGS += -suppress 2583
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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# Define only one toplevel module
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# Define only one top-level module
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TB_TOP_MODULE ?= x4xx_qsfp_wrapper_all_tb
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SIM_TOP = $(TB_TOP_MODULE)
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SIM_SRCS = \
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$(abspath x4xx_qsfp_wrapper_tb.sv) \
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$(abspath $(TB_TOP_MODULE).sv)
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# Suppressing the following worthless reminder.
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#* Warning: M:/usrp4-hw/oss-repo/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv(228): (vlog-2583) [SVCHK] -
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# Extra checking for conflicts with always_comb and always_latch variables is done at vopt time
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SVLOG_ARGS = -suppress 2583
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$(abspath $(TB_TOP_MODULE).sv) \
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#-------------------------------------------------
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# Bottom-of-Makefile
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@@ -154,8 +154,8 @@ module x4xx_qsfp_wrapper_tb #(
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AxiLiteIf_v #(.DATA_WIDTH(32),.ADDR_WIDTH(40))
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s_axi_v (clk40, clk40_rst);
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`include "../../../../../../lib/axi4lite_sv/axi_lite.vh"
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`include "../../../../../../lib/axi4_sv/axi.vh"
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`include "../../../../lib/axi4lite_sv/axi_lite.vh"
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`include "../../../../lib/axi4_sv/axi.vh"
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always_comb begin
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`AXI4LITE_ASSIGN(s_axi_v,s_axi)
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axi_hp_v.arready = 1'b1;
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