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fpga: Update testbenches to work in ModelSim

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Original-commit: 0076076467303247c4e62e5824e5bf8ce79cbe66
This commit is contained in:
Wade Fife
2021-06-17 08:16:59 -05:00
parent 162632e7c1
commit fcfc6bf387
11 changed files with 304 additions and 137 deletions
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top/n3xx/sim/dram_fifo/Makefile
+32 -3
View File
@@ -50,16 +50,45 @@ $(IP_FIFO_4K_2CLK_SRCS) \
$(IP_FIFO_SHORT_2CLK_SRCS) \
)
#-------------------------------------------------
# ModelSim Specific
#-------------------------------------------------
MODELSIM_IP_SRCS = $(wildcard $(abspath \
$(IP_BUILD_DIR)/fifo_short_2clk/sim/fifo_short_2clk.v \
$(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/sim/axi_intercon_4x64_256_bd.v \
$(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/ip/*/sim/*.v \
$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/ddr3_32bit.v \
$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/ddr3_32bit_mig_sim.v \
$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/*/*.v \
$(VIVADO_PATH)/data/verilog/src/glbl.v \
))
MODELSIM_LIBS += \
secureip \
fifo_generator_v13_2_4 \
axi_register_slice_v2_1_19 \
axi_infrastructure_v1_1_0 \
axi_dwidth_converter_v2_1_19 \
axi_crossbar_v2_1_20 \
blk_mem_gen_v8_4_3 \
axi_data_fifo_v2_1_18 \
generic_baseblocks_v2_1_0 \
modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS)
MODELSIM_ARGS += glbl -t 1fs
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
# Define only one toplevel module
# Define only one top-level module
SIM_TOP = dram_fifo_tb
SIM_SRCS = \
SIM_SRCS += \
$(abspath dram_fifo_tb.sv) \
$(abspath axis_dram_fifo_single.sv) \
$(IP_DDR3_32BIT_SIM_OUTS)
$(IP_DDR3_32BIT_SIM_OUTS) \
#-------------------------------------------------
# Bottom-of-Makefile
top/n3xx/sim/dram_fifo_bist/Makefile
+32 -3
View File
@@ -50,16 +50,45 @@ $(IP_FIFO_4K_2CLK_SRCS) \
$(IP_FIFO_SHORT_2CLK_SRCS) \
)
#-------------------------------------------------
# ModelSim Specific
#-------------------------------------------------
MODELSIM_IP_SRCS = $(wildcard $(abspath \
$(IP_BUILD_DIR)/fifo_short_2clk/sim/fifo_short_2clk.v \
$(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/sim/axi_intercon_4x64_256_bd.v \
$(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/ip/*/sim/*.v \
$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/ddr3_32bit.v \
$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/ddr3_32bit_mig_sim.v \
$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/*/*.v \
$(VIVADO_PATH)/data/verilog/src/glbl.v \
))
MODELSIM_LIBS += \
secureip \
fifo_generator_v13_2_4 \
axi_register_slice_v2_1_19 \
axi_infrastructure_v1_1_0 \
axi_dwidth_converter_v2_1_19 \
axi_crossbar_v2_1_20 \
blk_mem_gen_v8_4_3 \
axi_data_fifo_v2_1_18 \
generic_baseblocks_v2_1_0 \
modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS)
MODELSIM_ARGS += glbl -t 1fs
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
# Define only one toplevel module
# Define only one top-level module
SIM_TOP = dram_fifo_bist_tb
SIM_SRCS = \
SIM_SRCS += \
$(abspath dram_fifo_bist_tb.sv) \
$(abspath ../dram_fifo/axis_dram_fifo_single.sv) \
$(IP_DDR3_32BIT_SIM_OUTS)
$(IP_DDR3_32BIT_SIM_OUTS) \
#-------------------------------------------------
# Bottom-of-Makefile