fpga: n3xx: Rename BIST image cores

Rename the BIST image cores to match the default image core names. This
eliminates the need to provide special arguments to build these images.


Original-commit: aae712c2eafe3f78ba8ed553190f7010a2d17c57

top/n3xx/n300_bist_rfnoc_image_core.v

@@ -13,7 +13,7 @@
 //   This file was automatically generated by the RFNoC image builder tool.
 //   Re-running that tool will overwrite this file!
 //
-// Source: n300_bist_image_core.yml
+// Source: n300_bist_rfnoc_image_core.yml
 //
 
 `default_nettype none

top/n3xx/n300_bist_rfnoc_image_core.vh

@@ -12,7 +12,7 @@
 //   This file was automatically generated by the RFNoC image builder tool.
 //   Re-running that tool will overwrite this file!
 //
-// Source: n300_bist_image_core.yml
+// Source: n300_bist_rfnoc_image_core.yml
 //
 
 `define CHDR_WIDTH     64

top/n3xx/n300_bist_rfnoc_image_core.yml

@@ -8,6 +8,7 @@ license: >-                             # License information used in file heade
 version: '1.0'                          # File version
 chdr_width: 64                          # Bit width of the CHDR bus for this image
 device: 'n300'
+image_core_name: 'n300_bist'            # Name to use for the RFNoC Image Core files
 default_target: 'N300_AA'
 
 # A list of all stream endpoints in design

top/n3xx/n310_bist_rfnoc_image_core.v

@@ -13,7 +13,7 @@
 //   This file was automatically generated by the RFNoC image builder tool.
 //   Re-running that tool will overwrite this file!
 //
-// Source: n310_bist_image_core.yml
+// Source: n310_bist_rfnoc_image_core.yml
 //
 
 `default_nettype none

top/n3xx/n310_bist_rfnoc_image_core.vh

@@ -12,7 +12,7 @@
 //   This file was automatically generated by the RFNoC image builder tool.
 //   Re-running that tool will overwrite this file!
 //
-// Source: n310_bist_image_core.yml
+// Source: n310_bist_rfnoc_image_core.yml
 //
 
 `define CHDR_WIDTH     64

top/n3xx/n310_bist_rfnoc_image_core.yml

@@ -8,6 +8,7 @@ license: >-                             # License information used in file heade
 version: '1.0'                          # File version
 chdr_width: 64                          # Bit width of the CHDR bus for this block
 device: 'n310'
+image_core_name: 'n310_bist'            # Name to use for the RFNoC Image Core files
 default_target: 'N310_AA'
 
 # A list of all stream endpoints in design

top/n3xx/n320_bist_rfnoc_image_core.v

@@ -13,7 +13,7 @@
 //   This file was automatically generated by the RFNoC image builder tool.
 //   Re-running that tool will overwrite this file!
 //
-// Source: n320_bist_image_core.yml
+// Source: n320_bist_rfnoc_image_core.yml
 //
 
 `default_nettype none

top/n3xx/n320_bist_rfnoc_image_core.vh

@@ -12,7 +12,7 @@
 //   This file was automatically generated by the RFNoC image builder tool.
 //   Re-running that tool will overwrite this file!
 //
-// Source: n320_bist_image_core.yml
+// Source: n320_bist_rfnoc_image_core.yml
 //
 
 `define CHDR_WIDTH     64

top/n3xx/n320_bist_rfnoc_image_core.yml

@@ -8,6 +8,7 @@ license: >-                             # License information used in file heade
 version: '1.0'                          # File version
 chdr_width: 64                          # Bit width of the CHDR bus for this block
 device: 'n320'
+image_core_name: 'n320_bist'            # Name to use for the RFNoC Image Core files
 default_target: 'N320_AA'
 
 # A list of all stream endpoints in design