From fc35c2a66a56a43b5666953d19ed8ebb6ef855d5 Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Thu, 14 Mar 2024 17:53:32 -0500 Subject: [PATCH] fpga: n3xx: Rename BIST image cores Rename the BIST image cores to match the default image core names. This eliminates the need to provide special arguments to build these images. Original-commit: aae712c2eafe3f78ba8ed553190f7010a2d17c57 --- .../{n300_bist_image_core.v => n300_bist_rfnoc_image_core.v} | 2 +- .../{n300_bist_image_core.vh => n300_bist_rfnoc_image_core.vh} | 2 +- ...{n300_bist_image_core.yml => n300_bist_rfnoc_image_core.yml} | 1 + .../{n310_bist_image_core.v => n310_bist_rfnoc_image_core.v} | 2 +- .../{n310_bist_image_core.vh => n310_bist_rfnoc_image_core.vh} | 2 +- ...{n310_bist_image_core.yml => n310_bist_rfnoc_image_core.yml} | 1 + .../{n320_bist_image_core.v => n320_bist_rfnoc_image_core.v} | 2 +- .../{n320_bist_image_core.vh => n320_bist_rfnoc_image_core.vh} | 2 +- ...{n320_bist_image_core.yml => n320_bist_rfnoc_image_core.yml} | 1 + 9 files changed, 9 insertions(+), 6 deletions(-) rename top/n3xx/{n300_bist_image_core.v => n300_bist_rfnoc_image_core.v} (99%) rename top/n3xx/{n300_bist_image_core.vh => n300_bist_rfnoc_image_core.vh} (91%) rename top/n3xx/{n300_bist_image_core.yml => n300_bist_rfnoc_image_core.yml} (97%) rename top/n3xx/{n310_bist_image_core.v => n310_bist_rfnoc_image_core.v} (99%) rename top/n3xx/{n310_bist_image_core.vh => n310_bist_rfnoc_image_core.vh} (91%) rename top/n3xx/{n310_bist_image_core.yml => n310_bist_rfnoc_image_core.yml} (98%) rename top/n3xx/{n320_bist_image_core.v => n320_bist_rfnoc_image_core.v} (99%) rename top/n3xx/{n320_bist_image_core.vh => n320_bist_rfnoc_image_core.vh} (91%) rename top/n3xx/{n320_bist_image_core.yml => n320_bist_rfnoc_image_core.yml} (98%) diff --git a/top/n3xx/n300_bist_image_core.v b/top/n3xx/n300_bist_rfnoc_image_core.v similarity index 99% rename from top/n3xx/n300_bist_image_core.v rename to top/n3xx/n300_bist_rfnoc_image_core.v index b7ef8ca..ebdde05 100644 --- a/top/n3xx/n300_bist_image_core.v +++ b/top/n3xx/n300_bist_rfnoc_image_core.v @@ -13,7 +13,7 @@ // This file was automatically generated by the RFNoC image builder tool. // Re-running that tool will overwrite this file! // -// Source: n300_bist_image_core.yml +// Source: n300_bist_rfnoc_image_core.yml // `default_nettype none diff --git a/top/n3xx/n300_bist_image_core.vh b/top/n3xx/n300_bist_rfnoc_image_core.vh similarity index 91% rename from top/n3xx/n300_bist_image_core.vh rename to top/n3xx/n300_bist_rfnoc_image_core.vh index d0061b1..68cb91c 100644 --- a/top/n3xx/n300_bist_image_core.vh +++ b/top/n3xx/n300_bist_rfnoc_image_core.vh @@ -12,7 +12,7 @@ // This file was automatically generated by the RFNoC image builder tool. // Re-running that tool will overwrite this file! // -// Source: n300_bist_image_core.yml +// Source: n300_bist_rfnoc_image_core.yml // `define CHDR_WIDTH 64 diff --git a/top/n3xx/n300_bist_image_core.yml b/top/n3xx/n300_bist_rfnoc_image_core.yml similarity index 97% rename from top/n3xx/n300_bist_image_core.yml rename to top/n3xx/n300_bist_rfnoc_image_core.yml index 7d75c1a..bb579cf 100644 --- a/top/n3xx/n300_bist_image_core.yml +++ b/top/n3xx/n300_bist_rfnoc_image_core.yml @@ -8,6 +8,7 @@ license: >- # License information used in file heade version: '1.0' # File version chdr_width: 64 # Bit width of the CHDR bus for this image device: 'n300' +image_core_name: 'n300_bist' # Name to use for the RFNoC Image Core files default_target: 'N300_AA' # A list of all stream endpoints in design diff --git a/top/n3xx/n310_bist_image_core.v b/top/n3xx/n310_bist_rfnoc_image_core.v similarity index 99% rename from top/n3xx/n310_bist_image_core.v rename to top/n3xx/n310_bist_rfnoc_image_core.v index d85c811..56c350b 100644 --- a/top/n3xx/n310_bist_image_core.v +++ b/top/n3xx/n310_bist_rfnoc_image_core.v @@ -13,7 +13,7 @@ // This file was automatically generated by the RFNoC image builder tool. // Re-running that tool will overwrite this file! // -// Source: n310_bist_image_core.yml +// Source: n310_bist_rfnoc_image_core.yml // `default_nettype none diff --git a/top/n3xx/n310_bist_image_core.vh b/top/n3xx/n310_bist_rfnoc_image_core.vh similarity index 91% rename from top/n3xx/n310_bist_image_core.vh rename to top/n3xx/n310_bist_rfnoc_image_core.vh index 9efec69..09fdf46 100644 --- a/top/n3xx/n310_bist_image_core.vh +++ b/top/n3xx/n310_bist_rfnoc_image_core.vh @@ -12,7 +12,7 @@ // This file was automatically generated by the RFNoC image builder tool. // Re-running that tool will overwrite this file! // -// Source: n310_bist_image_core.yml +// Source: n310_bist_rfnoc_image_core.yml // `define CHDR_WIDTH 64 diff --git a/top/n3xx/n310_bist_image_core.yml b/top/n3xx/n310_bist_rfnoc_image_core.yml similarity index 98% rename from top/n3xx/n310_bist_image_core.yml rename to top/n3xx/n310_bist_rfnoc_image_core.yml index ec7e665..dda784d 100644 --- a/top/n3xx/n310_bist_image_core.yml +++ b/top/n3xx/n310_bist_rfnoc_image_core.yml @@ -8,6 +8,7 @@ license: >- # License information used in file heade version: '1.0' # File version chdr_width: 64 # Bit width of the CHDR bus for this block device: 'n310' +image_core_name: 'n310_bist' # Name to use for the RFNoC Image Core files default_target: 'N310_AA' # A list of all stream endpoints in design diff --git a/top/n3xx/n320_bist_image_core.v b/top/n3xx/n320_bist_rfnoc_image_core.v similarity index 99% rename from top/n3xx/n320_bist_image_core.v rename to top/n3xx/n320_bist_rfnoc_image_core.v index 0d42234..c059e42 100644 --- a/top/n3xx/n320_bist_image_core.v +++ b/top/n3xx/n320_bist_rfnoc_image_core.v @@ -13,7 +13,7 @@ // This file was automatically generated by the RFNoC image builder tool. // Re-running that tool will overwrite this file! // -// Source: n320_bist_image_core.yml +// Source: n320_bist_rfnoc_image_core.yml // `default_nettype none diff --git a/top/n3xx/n320_bist_image_core.vh b/top/n3xx/n320_bist_rfnoc_image_core.vh similarity index 91% rename from top/n3xx/n320_bist_image_core.vh rename to top/n3xx/n320_bist_rfnoc_image_core.vh index 7a85ba4..8f0a101 100644 --- a/top/n3xx/n320_bist_image_core.vh +++ b/top/n3xx/n320_bist_rfnoc_image_core.vh @@ -12,7 +12,7 @@ // This file was automatically generated by the RFNoC image builder tool. // Re-running that tool will overwrite this file! // -// Source: n320_bist_image_core.yml +// Source: n320_bist_rfnoc_image_core.yml // `define CHDR_WIDTH 64 diff --git a/top/n3xx/n320_bist_image_core.yml b/top/n3xx/n320_bist_rfnoc_image_core.yml similarity index 98% rename from top/n3xx/n320_bist_image_core.yml rename to top/n3xx/n320_bist_rfnoc_image_core.yml index 744d812..048e8a6 100644 --- a/top/n3xx/n320_bist_image_core.yml +++ b/top/n3xx/n320_bist_rfnoc_image_core.yml @@ -8,6 +8,7 @@ license: >- # License information used in file heade version: '1.0' # File version chdr_width: 64 # Bit width of the CHDR bus for this block device: 'n320' +image_core_name: 'n320_bist' # Name to use for the RFNoC Image Core files default_target: 'N320_AA' # A list of all stream endpoints in design