Pushing the bulk of UHD-3.7.0 code.

Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
This commit is contained in:
Ben Hilburn
2014-02-14 12:05:07 -08:00
parent 29086f9001
commit fbbc991a7d
2194 changed files with 1489297 additions and 1084 deletions
+32
View File
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`timescale 1ns/1ps
module bus_int_tb();
wire GSR, GTS;
xlnx_glbl glbl( );
reg clk = 0;
reg reset = 1;
always #10 clk = ~clk;
initial $dumpfile("bus_int_tb.vcd");
initial $dumpvars(0,bus_int_tb);
initial
begin
#1000 reset = 0;
#2000000;
$finish;
end
wire sen, sclk, mosi, miso;
wire scl, sda;
bus_int bus_int
(.clk(clk), .reset(reset),
.sen(sen), .sclk(sclk), .mosi(mosi), .miso(miso),
.scl(scl), .sda(sda)
);
endmodule // bus_int_tb