33 lines
531 B
Verilog
33 lines
531 B
Verilog
`timescale 1ns/1ps
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module bus_int_tb();
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wire GSR, GTS;
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xlnx_glbl glbl( );
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reg clk = 0;
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reg reset = 1;
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always #10 clk = ~clk;
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initial $dumpfile("bus_int_tb.vcd");
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initial $dumpvars(0,bus_int_tb);
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initial
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begin
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#1000 reset = 0;
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#2000000;
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$finish;
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end
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wire sen, sclk, mosi, miso;
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wire scl, sda;
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bus_int bus_int
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(.clk(clk), .reset(reset),
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.sen(sen), .sclk(sclk), .mosi(mosi), .miso(miso),
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.scl(scl), .sda(sda)
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);
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endmodule // bus_int_tb
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