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fpga: x400: Place SPI into IOB on X440

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Placing the SPI registers into the IOB makes timing closure more
reliable.


Original-commit: 6c25d54c34f0cc4612d5c9d27e0cbd90ff248795
This commit is contained in:
Max Köhler
2024-04-09 17:12:44 -05:00
committed by Wade Fife
parent 1a4d0543f6
commit fa95da3f7f
1 changed files with 4 additions and 0 deletions
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top/x400/constraints/timing/x440.xdc
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@@ -122,3 +122,7 @@ set spi_max_out_delay 9.500
set spi_out_ports [get_ports {PL_CPLD_SCLK PL_CPLD_MOSI PL_CPLD_CS0_n PL_CPLD_CS1_n}] set spi_out_ports [get_ports {PL_CPLD_SCLK PL_CPLD_MOSI PL_CPLD_CS0_n PL_CPLD_CS1_n}]
set_output_delay -clock [get_clocks pll_ref_clk] -min $spi_min_out_delay $spi_out_ports set_output_delay -clock [get_clocks pll_ref_clk] -min $spi_min_out_delay $spi_out_ports
set_output_delay -clock [get_clocks pll_ref_clk] -max $spi_max_out_delay $spi_out_ports set_output_delay -clock [get_clocks pll_ref_clk] -max $spi_max_out_delay $spi_out_ports
# Force SPI registers into IOB.
set_property IOB TRUE [get_cells "cpld_interface_i/ctrlport_spi_master_i/simple_spi_core_64bit_i/sclk_reg"]
set_property IOB TRUE [get_cells "cpld_interface_i/ctrlport_spi_master_i/simple_spi_core_64bit_i/mosi_reg"]