From fa95da3f7f6f7a6065800678efd5d9ebba07e758 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Max=20K=C3=B6hler?= Date: Fri, 5 Apr 2024 11:04:48 +0000 Subject: [PATCH] fpga: x400: Place SPI into IOB on X440 Placing the SPI registers into the IOB makes timing closure more reliable. Original-commit: 6c25d54c34f0cc4612d5c9d27e0cbd90ff248795 --- top/x400/constraints/timing/x440.xdc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/top/x400/constraints/timing/x440.xdc b/top/x400/constraints/timing/x440.xdc index a5482b2..84ba13e 100644 --- a/top/x400/constraints/timing/x440.xdc +++ b/top/x400/constraints/timing/x440.xdc @@ -122,3 +122,7 @@ set spi_max_out_delay 9.500 set spi_out_ports [get_ports {PL_CPLD_SCLK PL_CPLD_MOSI PL_CPLD_CS0_n PL_CPLD_CS1_n}] set_output_delay -clock [get_clocks pll_ref_clk] -min $spi_min_out_delay $spi_out_ports set_output_delay -clock [get_clocks pll_ref_clk] -max $spi_max_out_delay $spi_out_ports + +# Force SPI registers into IOB. +set_property IOB TRUE [get_cells "cpld_interface_i/ctrlport_spi_master_i/simple_spi_core_64bit_i/sclk_reg"] +set_property IOB TRUE [get_cells "cpld_interface_i/ctrlport_spi_master_i/simple_spi_core_64bit_i/mosi_reg"]