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fpga: sim: Fix typo in clk_wait_f

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Original-commit: cadc906649f438d425926f7fd629857d439c6dca
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Wade Fife committed 2022-12-19 08:57:18 -06:00
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commit df4953a60d
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sim/rfnoc/sim_clock_gen.sv
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@@ -103,7 +103,7 @@ module sim_clock_gen #(
endtask
// Wait for num falling edges of the clock
task clkd_wait_f(int num = 1);
task clk_wait_f(int num = 1);
repeat(num) @(negedge clk);
endtask