fpga: sim: Fix typo in clk_wait_f

Original-commit: cadc906649f438d425926f7fd629857d439c6dca
2022-12-19 08:57:18 -06:00
parent 4d4b06dfac
commit df4953a60d
1 changed files with 1 additions and 1 deletions
@@ -103,7 +103,7 @@ module sim_clock_gen #(
  endtask

  // Wait for num falling edges of the clock
-  task clkd_wait_f(int num = 1);
+  task clk_wait_f(int num = 1);
    repeat(num) @(negedge clk);
  endtask