diff --git a/sim/rfnoc/sim_clock_gen.sv b/sim/rfnoc/sim_clock_gen.sv
index fbe6497..9b36616 100644
--- a/sim/rfnoc/sim_clock_gen.sv
+++ b/sim/rfnoc/sim_clock_gen.sv
@@ -103,7 +103,7 @@ module sim_clock_gen #(
   endtask
 
   // Wait for num falling edges of the clock
-  task clkd_wait_f(int num = 1);
+  task clk_wait_f(int num = 1);
     repeat(num) @(negedge clk);
   endtask