From df4953a60dffd8811234b63c195642d4ba70c898 Mon Sep 17 00:00:00 2001
From: Wade Fife <wade.fife@ettus.com>
Date: Mon, 12 Dec 2022 19:51:14 -0600
Subject: [PATCH] fpga: sim: Fix typo in clk_wait_f

Original-commit: cadc906649f438d425926f7fd629857d439c6dca
---
 sim/rfnoc/sim_clock_gen.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sim/rfnoc/sim_clock_gen.sv b/sim/rfnoc/sim_clock_gen.sv
index fbe6497..9b36616 100644
--- a/sim/rfnoc/sim_clock_gen.sv
+++ b/sim/rfnoc/sim_clock_gen.sv
@@ -103,7 +103,7 @@ module sim_clock_gen #(
   endtask
 
   // Wait for num falling edges of the clock
-  task clkd_wait_f(int num = 1);
+  task clk_wait_f(int num = 1);
     repeat(num) @(negedge clk);
   endtask