fpga: rfnoc: Fix testbenches to run under ModelSim

This updates the makefiles for the testbenches so they can be run using
"make modelsim" without any additional hacks. The "xsim" and "vsim"
simulation targets also still work.


Original-commit: e962cc4a5e51e2326eb656ee2a779ea26774687b

lib/sim/dsp/mult_add_clip/Makefile

@@ -25,13 +25,14 @@ $(DSP_SRCS) \
 #-------------------------------------------------
 # Testbench Specific
 #-------------------------------------------------
-# Define only one toplevel module
-SIM_TOP = mult_add_clip_tb
+# Define toplevel module
+SIM_TOP = mult_add_clip_tb glbl
 
 # Add test bench, user design under test, and
 # additional user created files
 SIM_SRCS = $(abspath \
 mult_add_clip_tb.sv \
+$(VIVADO_PATH)/data/verilog/src/glbl.v \
 )
 
 # MODELSIM_USER_DO = $(abspath wave.do)