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fpga: rfnoc: Fix testbenches to run under ModelSim

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This updates the makefiles for the testbenches so they can be run using
"make modelsim" without any additional hacks. The "xsim" and "vsim"
simulation targets also still work.


Original-commit: e962cc4a5e51e2326eb656ee2a779ea26774687b
This commit is contained in:
Wade Fife
2020-07-20 15:33:22 -05:00
parent 2f517134cd
commit dce6ce8063
9 changed files with 70 additions and 91 deletions
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lib/rfnoc/blocks/rfnoc_block_fft/Makefile.srcs
+1 -1
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@@ -1,5 +1,5 @@
#
# Copyright 2019 Ettus Research, A National Instruments Company
# Copyright 2019 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#