fpga: rfnoc: Fix testbenches to run under ModelSim

This updates the makefiles for the testbenches so they can be run using
"make modelsim" without any additional hacks. The "xsim" and "vsim"
simulation targets also still work.


Original-commit: e962cc4a5e51e2326eb656ee2a779ea26774687b

lib/rfnoc/blocks/rfnoc_block_fft/Makefile

@@ -1,5 +1,5 @@
 #
-# Copyright 2019 Ettus Research, A National Instruments Company
+# Copyright 2019 Ettus Research, a National Instruments Brand
 #
 # SPDX-License-Identifier: LGPL-3.0-or-later
 #
@@ -45,13 +45,10 @@ $(RFNOC_OOT_SRCS) \
 #-------------------------------------------------
 # Testbench Specific
 #-------------------------------------------------
-# Define only one toplevel module
-SIM_TOP = rfnoc_block_fft_tb
-
-# Add test bench, user design under test, and
-# additional user created files
+SIM_TOP = rfnoc_block_fft_tb glbl
 SIM_SRCS = \
-$(abspath rfnoc_block_fft_tb.sv)
+$(abspath rfnoc_block_fft_tb.sv) \
+$(VIVADO_PATH)/data/verilog/src/glbl.v \
 
 #-------------------------------------------------
 # Bottom-of-Makefile

lib/rfnoc/blocks/rfnoc_block_fft/Makefile.srcs

@@ -1,5 +1,5 @@
 #
-# Copyright 2019 Ettus Research, A National Instruments Company
+# Copyright 2019 Ettus Research, a National Instruments Brand
 #
 # SPDX-License-Identifier: LGPL-3.0-or-later
 #