Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt Ettus.
Original-commit: 0df4b801a34697f2058b4a7b95e08d2a0576c9db
This commit is contained in:
Ben Hilburn
@@ -0,0 +1,59 @@
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#
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# Copyright 2008-2013 Ettus Research LLC
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#
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##################################################
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# Constants
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##################################################
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ISE_VER = $(shell xtclsh -h | head -n1 | cut -f2 -d" " | cut -f1 -d.)
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ifeq ($(ISE_VER),10)
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ISE_EXT = ise
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else
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ISE_EXT = xise
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endif
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BASE_DIR = $(abspath ..)
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ISE_HELPER = xtclsh $(BASE_DIR)/tcl/ise_helper.tcl
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SANITY_CHECKER = python $(BASE_DIR)/python/check_inout.py
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TIMING_CHECKER = python $(BASE_DIR)/python/check_timing.py
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ISE_FILE = $(BUILD_DIR)/$(TOP_MODULE).$(ISE_EXT)
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BIN_FILE = $(BUILD_DIR)/$(TOP_MODULE).bin
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BIT_FILE = $(BUILD_DIR)/$(TOP_MODULE).bit
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TWR_FILE = $(BUILD_DIR)/$(TOP_MODULE).twr
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##################################################
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# Global Targets
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##################################################
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all: bin
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proj: $(ISE_FILE)
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check: $(ISE_FILE)
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#$(SANITY_CHECKER) $(TOP_MODULE).v $(TOP_MODULE).ucf
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$(ISE_HELPER) "Check Syntax"
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synth: $(ISE_FILE)
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$(ISE_HELPER) "Synthesize - XST"
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#bin: check $(BIN_FILE)
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bin: $(BIN_FILE) $(BIT_FILE)
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$(TIMING_CHECKER) $(TWR_FILE)
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clean:
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$(RM) -r $(BUILD_DIR)
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.PHONY: all proj check synth bin mcs clean
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##################################################
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# Dependency Targets
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##################################################
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.SECONDEXPANSION:
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$(ISE_FILE): $$(SOURCES) $$(MAKEFILE_LIST)
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@echo $@
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$(ISE_HELPER) ""
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$(BIN_FILE): $(ISE_FILE) $$(SOURCES) $$(MAKEFILE_LIST)
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@echo $@
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$(ISE_HELPER) "Generate Programming File" 2>&1 | tee $(BUILD_DIR)/build.log
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touch $@
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.EXPORT_ALL_VARIABLES:
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@@ -0,0 +1,5 @@
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build*
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catcap_tb
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catgen_tb
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fuse*
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isim*
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@@ -0,0 +1,20 @@
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#
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# Copyright 2012-2013 Ettus Research LLC
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#
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all: B200 B210
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find -name "*.twr" | xargs grep constraint | grep met
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mkdir -p build
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cp build-B200/b200.bin build/usrp_b200_fpga.bin
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cp build-B210/b200.bin build/usrp_b210_fpga.bin
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clean:
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rm -rf build*
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B200:
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make -f Makefile.b200.inc bin NAME=B200 DEVICE=XC6SLX75
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B210:
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make -f Makefile.b200.inc bin NAME=B210 DEVICE=XC6SLX150 EXTRA_DEFS="B200_CAN_HAZ_R1=1"
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.PHONY: all clean
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@@ -0,0 +1,127 @@
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#
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# Copyright 2012-2013 Ettus Research LLC
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#
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##################################################
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# Project Setup
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##################################################
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TOP_MODULE := b200
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BUILD_DIR := build-$(NAME)/
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export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
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# set me in a custom makefile
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CUSTOM_SRCS =
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CUSTOM_DEFS =
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include ../Makefile.common
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include ../../lib/gpif2/Makefile.srcs
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include ../../lib/fifo/Makefile.srcs
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include ../../lib/dsp/Makefile.srcs
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include ../../lib/control/Makefile.srcs
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include ../../lib/packet_proc/Makefile.srcs
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include ../../lib/timing/Makefile.srcs
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include ../../lib/vita/Makefile.srcs
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include ../../lib/wishbone/Makefile.srcs
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B200_COREGEN_SRCS = \
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coregen/b200_clk_gen.v \
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coregen/fifo_4k_2clk.xco \
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coregen/fifo_short_2clk.xco \
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coregen/chipscope_icon.v \
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coregen/chipscope_icon.xco \
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coregen/chipscope_ila_32.v \
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coregen/chipscope_ila_32.xco \
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coregen/chipscope_ila_128.v \
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coregen/chipscope_ila_128.xco \
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coregen/chipscope_ila_256.v \
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coregen/chipscope_ila_256.xco
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##################################################
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# Project Properties
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##################################################
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export PROJECT_PROPERTIES := \
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family "Spartan6" \
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device $(DEVICE) \
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package fgg484 \
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speed -3 \
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top_level_module_type "HDL" \
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synthesis_tool "XST (VHDL/Verilog)" \
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simulator "ISE Simulator (VHDL/Verilog)" \
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"Preferred Language" "Verilog" \
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"Enable Message Filtering" FALSE \
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"Display Incremental Messages" FALSE
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##################################################
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# Sources
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##################################################
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TOP_SRCS = \
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b200.v \
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b200_core.v \
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radio_b200.v \
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catcap_ddr_cmos.v \
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catgen_ddr_cmos.v \
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catcodec_ddr_cmos.v \
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b200.ucf \
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timing.ucf \
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S6CLK2PIN.v \
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$(B200_COREGEN_SRCS)
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SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
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$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) \
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$(TIMING_SRCS) $(OPENCORES_SRCS) \
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$(VRT_SRCS) $(COREGEN_SRCS) \
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$(GPIF2_SRCS) $(PACKET_PROC_SRCS) \
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$(WISHBONE_SRCS) \
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$(TIMING_SRCS) \
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$(DSP_SRCS) \
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$(VITA_SRCS)
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##################################################
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# Process Properties
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##################################################
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SYNTHESIZE_PROPERTIES = \
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"Pack I/O Registers into IOBs" Yes \
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"Optimization Effort" High \
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"Optimize Instantiated Primitives" TRUE \
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"Register Balancing" Yes \
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"Use Clock Enable" Auto \
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"Use Synchronous Reset" Auto \
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"Use Synchronous Set" Auto \
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"Verilog Macros" "SPARTAN6=1 $(EXTRA_DEFS) $(CUSTOM_DEFS)"
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#"Number of Clock Buffers" 8 \
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TRANSLATE_PROPERTIES = \
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"Macro Search Path" "$(shell pwd)/../../coregen/"
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MAP_PROPERTIES = \
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"Generate Detailed MAP Report" TRUE \
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"Allow Logic Optimization Across Hierarchy" TRUE \
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"Map to Input Functions" 4 \
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"Optimization Strategy (Cover Mode)" Speed \
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"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
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"Perform Timing-Driven Packing and Placement" TRUE \
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"Map Effort Level" High \
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"Extra Effort" Normal \
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"Combinatorial Logic Optimization" TRUE \
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"Register Duplication" TRUE
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PLACE_ROUTE_PROPERTIES = \
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"Place & Route Effort Level (Overall)" High
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STATIC_TIMING_PROPERTIES = \
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"Number of Paths in Error/Verbose Report" 10 \
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"Report Type" "Error Report"
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GEN_PROG_FILE_PROPERTIES = \
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"Create Binary Configuration File" TRUE \
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"Done (Output Events)" 5 \
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"Enable Bitstream Compression" TRUE \
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"Unused IOB Pins" "Pull Up"
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#"Configuration Rate" 6 \
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#"Enable Outputs (Output Events)" 6 \
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SIM_MODEL_PROPERTIES = ""
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@@ -0,0 +1,23 @@
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module S6CLK2PIN
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(
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input I,
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output O
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);
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ODDR2 #(
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.DDR_ALIGNMENT("NONE"), // to "NONE", "C0" or "C1"
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.INIT(1'b0), // output to 1'b0 or 1'b1
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.SRTYPE("ASYNC")) // set/reset "SYNC" or "ASYNC"
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ODDR2_S6CLK2PIN
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(
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.Q(O), // 1-bit DDR output data
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.C0(I), // 1-bit clock input
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.C1(~I), // 1-bit clock input
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.CE(1'b1), // 1-bit clock enable input
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.D0(1'b1), // 1-bit data input (associated with C0)
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.D1(1'b0), // 1-bit data input (associated with C1)
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.R(1'b0), // 1-bit reset input
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.S(1'b0) );// 1-bit set input
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endmodule //S6CLK2PIN
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@@ -0,0 +1,244 @@
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## SPI Nets
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NET "cat_ce" LOC = "Y1" | IOSTANDARD = LVCMOS18;
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NET "cat_miso" LOC = "V1" | IOSTANDARD = LVCMOS18;
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NET "cat_mosi" LOC = "T4" | IOSTANDARD = LVCMOS18;
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NET "cat_sclk" LOC = "P7" | IOSTANDARD = LVCMOS18;
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NET "fx3_ce" LOC = "H20" | IOSTANDARD = LVCMOS18 ;
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NET "fx3_miso" LOC = "G20" | IOSTANDARD = LVCMOS18 ;
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NET "fx3_mosi" LOC = "AA20" | IOSTANDARD = LVCMOS18 ;
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#NET "fx3_mosi" LOC = "A9" | IOSTANDARD = LVCMOS33 ;
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NET "fx3_sclk" LOC = "Y21" | IOSTANDARD = LVCMOS18 ;
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NET "pll_ce" LOC = "W11" | IOSTANDARD = LVCMOS18 ;
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NET "pll_mosi" LOC = "AB11" | IOSTANDARD = LVCMOS18 ;
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NET "pll_sclk" LOC = "Y12" | IOSTANDARD = LVCMOS18 ;
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NET "FPGA_RXD0" LOC = "AB8" | IOSTANDARD = LVCMOS18 ;
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NET "FPGA_TXD0" LOC = "AB7" | IOSTANDARD = LVCMOS18 ;
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## Catalina Controls
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NET "codec_enable" LOC = "J6" | IOSTANDARD = LVCMOS18;
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NET "codec_en_agc" LOC = "P6" | IOSTANDARD = LVCMOS18;
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NET "codec_reset" LOC = "Y2" | IOSTANDARD = LVCMOS18;
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NET "codec_sync" LOC = "M3" | IOSTANDARD = LVCMOS18;
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NET "codec_txrx" LOC = "M7" | IOSTANDARD = LVCMOS18;
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NET "codec_ctrl_in<0>" LOC = "E3" | IOSTANDARD = LVCMOS18;
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NET "codec_ctrl_in<1>" LOC = "F2" | IOSTANDARD = LVCMOS18;
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NET "codec_ctrl_in<2>" LOC = "F1" | IOSTANDARD = LVCMOS18;
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NET "codec_ctrl_in<3>" LOC = "E1" | IOSTANDARD = LVCMOS18;
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NET "codec_ctrl_out<0>" LOC = "D1" | IOSTANDARD = LVCMOS18;
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NET "codec_ctrl_out<1>" LOC = "C1" | IOSTANDARD = LVCMOS18;
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NET "codec_ctrl_out<2>" LOC = "H3" | IOSTANDARD = LVCMOS18;
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NET "codec_ctrl_out<3>" LOC = "F3" | IOSTANDARD = LVCMOS18;
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NET "codec_ctrl_out<4>" LOC = "P1" | IOSTANDARD = LVCMOS18;
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NET "codec_ctrl_out<5>" LOC = "J1" | IOSTANDARD = LVCMOS18;
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NET "codec_ctrl_out<6>" LOC = "B1" | IOSTANDARD = LVCMOS18;
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NET "codec_ctrl_out<7>" LOC = "H2" | IOSTANDARD = LVCMOS18;
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## Catalina Data TX
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NET "tx_codec_d<0>" LOC = "T2" | IOSTANDARD = LVCMOS18 ;
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NET "tx_codec_d<1>" LOC = "R1" | IOSTANDARD = LVCMOS18 ;
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NET "tx_codec_d<2>" LOC = "V2" | IOSTANDARD = LVCMOS18 ;
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NET "tx_codec_d<3>" LOC = "N1" | IOSTANDARD = LVCMOS18 ;
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NET "tx_codec_d<4>" LOC = "V3" | IOSTANDARD = LVCMOS18 ;
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NET "tx_codec_d<5>" LOC = "T1" | IOSTANDARD = LVCMOS18 ;
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NET "tx_codec_d<6>" LOC = "W1" | IOSTANDARD = LVCMOS18 ;
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NET "tx_codec_d<7>" LOC = "U1" | IOSTANDARD = LVCMOS18 ;
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NET "tx_codec_d<8>" LOC = "W3" | IOSTANDARD = LVCMOS18 ;
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NET "tx_codec_d<9>" LOC = "U3" | IOSTANDARD = LVCMOS18 ;
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NET "tx_codec_d<10>" LOC = "P2" | IOSTANDARD = LVCMOS18 ;
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NET "tx_codec_d<11>" LOC = "R3" | IOSTANDARD = LVCMOS18 ;
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NET "tx_codec_d*" DRIVE = 2;
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## Catalina Data RX
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NET "rx_codec_d<0>" LOC = "M1" | IOSTANDARD = LVCMOS18 ;
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NET "rx_codec_d<1>" LOC = "K1" | IOSTANDARD = LVCMOS18 ;
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NET "rx_codec_d<2>" LOC = "K2" | IOSTANDARD = LVCMOS18 ;
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NET "rx_codec_d<3>" LOC = "G3" | IOSTANDARD = LVCMOS18 ;
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NET "rx_codec_d<4>" LOC = "M2" | IOSTANDARD = LVCMOS18 ;
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NET "rx_codec_d<5>" LOC = "J4" | IOSTANDARD = LVCMOS18 ;
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NET "rx_codec_d<6>" LOC = "L3" | IOSTANDARD = LVCMOS18 ;
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NET "rx_codec_d<7>" LOC = "H1" | IOSTANDARD = LVCMOS18 ;
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NET "rx_codec_d<8>" LOC = "L4" | IOSTANDARD = LVCMOS18 ;
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NET "rx_codec_d<9>" LOC = "G1" | IOSTANDARD = LVCMOS18 ;
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NET "rx_codec_d<10>" LOC = "N3" | IOSTANDARD = LVCMOS18 ;
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NET "rx_codec_d<11>" LOC = "M4" | IOSTANDARD = LVCMOS18 ;
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NET "rx_codec_d*" DRIVE = 2;
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## Catalina Clocks
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NET "cat_clkout_fpga" LOC = "J3" | IOSTANDARD = LVCMOS18;
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NET "codec_data_clk_p" LOC = "K3" | IOSTANDARD = LVCMOS18;
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NET "codec_fb_clk_p" LOC = "P3" | IOSTANDARD = LVCMOS18 | DRIVE = 2 ;
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NET "codec_main_clk_p" LOC = "K5" | IOSTANDARD = LVDS_25;
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NET "codec_main_clk_n" LOC = "K4" | IOSTANDARD = LVDS_25;
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NET "rx_frame_p" LOC = "U4" | IOSTANDARD = LVCMOS18;
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NET "tx_frame_p" LOC = "T3" | IOSTANDARD = LVCMOS18 | DRIVE = 2 ;
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## Debug Bus
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NET "debug<0>" LOC = "D10" | IOSTANDARD = LVCMOS33 ;
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NET "debug<1>" LOC = "D9" | IOSTANDARD = LVCMOS33 ;
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NET "debug<2>" LOC = "A8" | IOSTANDARD = LVCMOS33 ;
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NET "debug<3>" LOC = "B8" | IOSTANDARD = LVCMOS33 ;
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NET "debug<4>" LOC = "C8" | IOSTANDARD = LVCMOS33 ;
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NET "debug<5>" LOC = "D8" | IOSTANDARD = LVCMOS33 ;
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NET "debug<6>" LOC = "A7" | IOSTANDARD = LVCMOS33 ;
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NET "debug<7>" LOC = "D7" | IOSTANDARD = LVCMOS33 ;
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NET "debug<8>" LOC = "A6" | IOSTANDARD = LVCMOS33 ;
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NET "debug<9>" LOC = "B6" | IOSTANDARD = LVCMOS33 ;
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NET "debug<10>" LOC = "C6" | IOSTANDARD = LVCMOS33 ;
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NET "debug<11>" LOC = "D6" | IOSTANDARD = LVCMOS33 ;
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NET "debug<12>" LOC = "A5" | IOSTANDARD = LVCMOS33 ;
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NET "debug<13>" LOC = "A4" | IOSTANDARD = LVCMOS33 ;
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NET "debug<14>" LOC = "C5" | IOSTANDARD = LVCMOS33 ;
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NET "debug<15>" LOC = "A3" | IOSTANDARD = LVCMOS33 ;
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NET "debug<16>" LOC = "A18" | IOSTANDARD = LVCMOS33 ;
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NET "debug<17>" LOC = "B18" | IOSTANDARD = LVCMOS33 ;
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NET "debug<18>" LOC = "A17" | IOSTANDARD = LVCMOS33 ;
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NET "debug<19>" LOC = "C17" | IOSTANDARD = LVCMOS33 ;
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NET "debug<20>" LOC = "C14" | IOSTANDARD = LVCMOS33 ;
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NET "debug<21>" LOC = "D12" | IOSTANDARD = LVCMOS33 ;
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NET "debug<22>" LOC = "C10" | IOSTANDARD = LVCMOS33 ;
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NET "debug<23>" LOC = "F15" | IOSTANDARD = LVCMOS33 ;
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NET "debug<24>" LOC = "E14" | IOSTANDARD = LVCMOS33 ;
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NET "debug<25>" LOC = "F14" | IOSTANDARD = LVCMOS33 ;
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NET "debug<26>" LOC = "H14" | IOSTANDARD = LVCMOS33 ;
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NET "debug<27>" LOC = "D13" | IOSTANDARD = LVCMOS33 ;
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NET "debug<28>" LOC = "F13" | IOSTANDARD = LVCMOS33 ;
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NET "debug<29>" LOC = "G13" | IOSTANDARD = LVCMOS33 ;
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||||
NET "debug<30>" LOC = "E12" | IOSTANDARD = LVCMOS33 ;
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NET "debug<31>" LOC = "H13" | IOSTANDARD = LVCMOS33 ;
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NET "debug_clk<0>" LOC = "A12" | IOSTANDARD = LVCMOS33 ;
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NET "debug_clk<1>" LOC = "C12" | IOSTANDARD = LVCMOS33 ;
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NET "debug*" DRIVE = 2;
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## GPIF
|
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NET "IFCLK" LOC = "H21" | IOSTANDARD = LVCMOS18 ;
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NET "FX3_EXTINT" LOC = "U20" | IOSTANDARD = LVCMOS18 ;
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NET "IFCLK" DRIVE = 8;
|
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NET "IFCLK" SLEW = SLOW;
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NET "GPIF_CTL0" LOC = "P22" | IOSTANDARD = LVCMOS18 ;
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NET "GPIF_CTL1" LOC = "N22" | IOSTANDARD = LVCMOS18 ;
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NET "GPIF_CTL2" LOC = "AA18" | IOSTANDARD = LVCMOS18 ;
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NET "GPIF_CTL3" LOC = "AB18" | IOSTANDARD = LVCMOS18 ;
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||||
NET "GPIF_CTL4" LOC = "P19" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_CTL5" LOC = "AA2" | IOSTANDARD = LVCMOS18 ;
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||||
NET "GPIF_CTL6" LOC = "M22" | IOSTANDARD = LVCMOS18 ;
|
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NET "GPIF_CTL7" LOC = "AB19" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_CTL8" LOC = "M19" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_CTL9" LOC = "R20" | IOSTANDARD = LVCMOS18 ;
|
||||
##GPIF_CTL10 is "FPGA_CFG_DONE", defined later.
|
||||
NET "GPIF_CTL11" LOC = "M21" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_CTL12" LOC = "M20" | IOSTANDARD = LVCMOS18 ;
|
||||
|
||||
NET "GPIF_D<0>" LOC = "T17" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<1>" LOC = "U14" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<2>" LOC = "U13" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<3>" LOC = "AA6" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<4>" LOC = "AB6" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<5>" LOC = "Y3" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<6>" LOC = "AB3" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<7>" LOC = "AA4" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<8>" LOC = "V20" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<9>" LOC = "AB2" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<10>" LOC = "V21" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<11>" LOC = "T22" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<12>" LOC = "U22" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<13>" LOC = "R22" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<14>" LOC = "AA12" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<15>" LOC = "AB12" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<16>" LOC = "Y13" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<17>" LOC = "N20" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<18>" LOC = "T21" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<19>" LOC = "K18" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<20>" LOC = "H22" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<21>" LOC = "J20" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<22>" LOC = "K19" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<23>" LOC = "L19" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<24>" LOC = "N19" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<25>" LOC = "K22" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<26>" LOC = "L22" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<27>" LOC = "L20" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<28>" LOC = "J22" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<29>" LOC = "K20" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<30>" LOC = "G22" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "GPIF_D<31>" LOC = "F22" | IOSTANDARD = LVCMOS18 ;
|
||||
|
||||
NET "GPIF_*" DRIVE = 2;
|
||||
NET "GPIF_*" SLEW = SLOW;
|
||||
|
||||
## GPS
|
||||
|
||||
NET "gps_lock" LOC = "B14" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "gps_rxd" LOC = "A15" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "gps_txd" LOC = "A14" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "gps_txd_nmea" LOC = "C15" | IOSTANDARD = LVCMOS33 ;
|
||||
|
||||
## LEDS
|
||||
|
||||
NET "LED_RX1" LOC = "C22" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "LED_RX2" LOC = "L15" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "LED_TXRX1_TX" LOC = "C20" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "LED_TXRX2_RX" LOC = "D21" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "LED_TXRX1_RX" LOC = "K16" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "LED_TXRX2_TX" LOC = "D22" | IOSTANDARD = LVCMOS18 ;
|
||||
|
||||
## Misc Hardware Control
|
||||
NET "ref_sel" LOC = "AA14" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "pll_lock" LOC = "AB10" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "AUX_PWR_ON" LOC = "B16" | IOSTANDARD = LVCMOS33 ;
|
||||
#NET "RFUSE" LOC = "P15" | IOSTANDARD = LVCMOS33 ;
|
||||
|
||||
## PPS
|
||||
|
||||
NET "PPS_IN_EXT" LOC = "B10" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "PPS_IN_INT" LOC = "A10" | IOSTANDARD = LVCMOS33 ;
|
||||
|
||||
## RF Hardware Control
|
||||
|
||||
NET "SFDX1_RX" LOC = "A16" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "SFDX1_TX" LOC = "D14" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "SFDX2_RX" LOC = "C11" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "SFDX2_TX" LOC = "A11" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "SRX1_RX" LOC = "D15" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "SRX1_TX" LOC = "C16" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "SRX2_RX" LOC = "B12" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "SRX2_TX" LOC = "D11" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "tx_bandsel_a" LOC = "C13" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "tx_bandsel_b" LOC = "D17" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "tx_enable1" LOC = "Y4" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "tx_enable2" LOC = "R19" | IOSTANDARD = LVCMOS18 ;
|
||||
NET "rx_bandsel_a" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "rx_bandsel_b" LOC = "A13" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "rx_bandsel_c" LOC = "E16" | IOSTANDARD = LVCMOS33 ;
|
||||
|
||||
## FPGA Config Pins
|
||||
|
||||
#NET "FPGA_CFG_INIT_B" LOC = "T6" | IOSTANDARD = LVCMOS18 ;
|
||||
#NET "FPGA_CFG_DONE" LOC = "Y22" | IOSTANDARD = LVCMOS18 ;
|
||||
#NET "FPGA_CFG_M0" LOC = "AA22" | IOSTANDARD = LVCMOS18 ;
|
||||
#NET "FPGA_CFG_M1" LOC = "U15" | IOSTANDARD = LVCMOS18 ;
|
||||
#NET "FPGA_CFG_PROG_B" LOC = "AA1" | IOSTANDARD = LVCMOS18 ;
|
||||
|
||||
## Special Pins
|
||||
|
||||
#NET "VFS" LOC = "P16" | IOSTANDARD = LVCMOS33 ;
|
||||
#NET "TMS" LOC = "C18" | IOSTANDARD = LVCMOS33 ;
|
||||
#NET "TDO" LOC = "A19" | IOSTANDARD = LVCMOS33 ;
|
||||
#NET "TDI" LOC = "E18" | IOSTANDARD = LVCMOS33 ;
|
||||
#NET "TCK" LOC = "G15" | IOSTANDARD = LVCMOS33 ;
|
||||
#NET "GND" LOC = "N15" | IOSTANDARD = LVCMOS33 ;
|
||||
+286
@@ -0,0 +1,286 @@
|
||||
//
|
||||
// Copyright 2013 Ettus Research LLC
|
||||
//
|
||||
|
||||
|
||||
/***********************************************************
|
||||
* B200 Module Declaration
|
||||
**********************************************************/
|
||||
module b200 (
|
||||
// SPI Interfaces
|
||||
output cat_ce,
|
||||
input cat_miso,
|
||||
output cat_mosi,
|
||||
output cat_sclk,
|
||||
|
||||
input fx3_ce,
|
||||
output fx3_miso,
|
||||
input fx3_mosi,
|
||||
input fx3_sclk,
|
||||
|
||||
output pll_ce,
|
||||
output pll_mosi,
|
||||
output pll_sclk,
|
||||
|
||||
// UART
|
||||
input FPGA_RXD0,
|
||||
input FPGA_TXD0,
|
||||
|
||||
// Catalina Controls
|
||||
output codec_enable,
|
||||
output codec_en_agc,
|
||||
output codec_reset,
|
||||
output codec_sync,
|
||||
output codec_txrx,
|
||||
output [3:0] codec_ctrl_in, // These should be outputs
|
||||
input [7:0] codec_ctrl_out, // MUST BE INPUT
|
||||
|
||||
// Catalina Data
|
||||
input codec_data_clk_p, // Clock from CAT (RX)
|
||||
output codec_fb_clk_p, // Clock to CAT (TX)
|
||||
input [11:0] rx_codec_d,
|
||||
output [11:0] tx_codec_d,
|
||||
input rx_frame_p,
|
||||
output tx_frame_p,
|
||||
|
||||
input cat_clkout_fpga,
|
||||
|
||||
//always on 40MHz clock
|
||||
input codec_main_clk_p,
|
||||
input codec_main_clk_n,
|
||||
|
||||
// Debug Bus
|
||||
output [31:0] debug,
|
||||
output [1:0] debug_clk,
|
||||
|
||||
// GPIF, FX3 Slave FIFO
|
||||
output IFCLK, // pclk
|
||||
input FX3_EXTINT,
|
||||
output GPIF_CTL0, // n_slcs
|
||||
output GPIF_CTL1, // n_slwr
|
||||
output GPIF_CTL2, // n_sloe
|
||||
output GPIF_CTL3, // n_slrd
|
||||
output GPIF_CTL7, // n_pktend
|
||||
input GPIF_CTL4, // slfifo_flags[0]
|
||||
input GPIF_CTL5, // slfifo_flags[1]
|
||||
input GPIF_CTL6, // slfifo_flags[2]
|
||||
input GPIF_CTL8, // slfifo_flags[3]
|
||||
output GPIF_CTL11, // slfifo_addr[1]
|
||||
output GPIF_CTL12, // slfifo_addr[0]
|
||||
inout [31:0] GPIF_D,
|
||||
input GPIF_CTL9, // global_reset
|
||||
|
||||
// GPS
|
||||
input gps_lock,
|
||||
output gps_rxd,
|
||||
input gps_txd,
|
||||
input gps_txd_nmea,
|
||||
|
||||
// LEDS
|
||||
output LED_RX1,
|
||||
output LED_RX2,
|
||||
output LED_TXRX1_RX,
|
||||
output LED_TXRX1_TX,
|
||||
output LED_TXRX2_RX,
|
||||
output LED_TXRX2_TX,
|
||||
|
||||
// Misc Hardware Control
|
||||
output ref_sel,
|
||||
input pll_lock,
|
||||
input FPGA_CFG_CS, // Driven by FX3 gpio.
|
||||
input AUX_PWR_ON, // Driven by FX3 gpio.
|
||||
|
||||
// PPS
|
||||
input PPS_IN_EXT,
|
||||
input PPS_IN_INT,
|
||||
|
||||
// RF Hardware Control
|
||||
output SFDX1_RX,
|
||||
output SFDX1_TX,
|
||||
output SFDX2_RX,
|
||||
output SFDX2_TX,
|
||||
output SRX1_RX,
|
||||
output SRX1_TX,
|
||||
output SRX2_RX,
|
||||
output SRX2_TX,
|
||||
output tx_bandsel_a,
|
||||
output tx_bandsel_b,
|
||||
output tx_enable1,
|
||||
output tx_enable2,
|
||||
output rx_bandsel_a,
|
||||
output rx_bandsel_b,
|
||||
output rx_bandsel_c
|
||||
);
|
||||
|
||||
wire reset_global = GPIF_CTL9;
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
// generate clocks from always on codec main clk
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
wire bus_clk, gpif_clk, radio_clk;
|
||||
wire locked;
|
||||
b200_clk_gen gen_clks
|
||||
(
|
||||
.CLK_IN1_40_P(codec_main_clk_p), .CLK_IN1_40_N(codec_main_clk_n),
|
||||
.CLK_OUT1_40_int(), .CLK_OUT2_100_gpif(gpif_clk), .CLK_OUT3_100_bus(bus_clk),
|
||||
.RESET(reset_global), .LOCKED(locked)
|
||||
);
|
||||
|
||||
//hold-off logic for clocks ready
|
||||
reg [15:0] clocks_ready_count;
|
||||
reg clocks_ready;
|
||||
always @(posedge bus_clk or posedge reset_global or negedge locked) begin
|
||||
if (reset_global | !locked) begin
|
||||
clocks_ready_count <= 16'b0;
|
||||
clocks_ready <= 1'b0;
|
||||
end
|
||||
else if (!clocks_ready) begin
|
||||
clocks_ready_count <= clocks_ready_count + 1'b1;
|
||||
clocks_ready <= (clocks_ready_count == 16'hffff);
|
||||
end
|
||||
end
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
// drive output clocks
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
wire [1:0] debug_clk_int;
|
||||
//S6CLK2PIN S6CLK2PIN_dbg0 (.I(debug_clk_int[0]), .O(debug_clk[0]));
|
||||
//S6CLK2PIN S6CLK2PIN_dbg1 (.I(debug_clk_int[1]), .O(debug_clk[1]));
|
||||
assign debug_clk[1:0] = 2'b0;
|
||||
S6CLK2PIN S6CLK2PIN_gpif (.I(gpif_clk), .O(IFCLK));
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
// Create sync reset signals
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
wire gpif_rst, bus_rst, radio_rst;
|
||||
reset_sync gpif_sync(.clk(gpif_clk), .reset_in(!clocks_ready), .reset_out(gpif_rst));
|
||||
reset_sync bus_sync(.clk(bus_clk), .reset_in(!clocks_ready), .reset_out(bus_rst));
|
||||
reset_sync radio_sync(.clk(radio_clk), .reset_in(!clocks_ready), .reset_out(radio_rst));
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
// CODEC capture/gen
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
wire [31:0] rx_data1, rx_data2;
|
||||
wire [31:0] tx_data1, tx_data2;
|
||||
wire mimo, codec_arst;
|
||||
|
||||
catcodec_ddr_cmos catcodec
|
||||
(
|
||||
.radio_clk(radio_clk), .arst(codec_arst), .mimo(mimo),
|
||||
.rx1(rx_data1), .rx2(rx_data2), .tx1(tx_data1), .tx2(tx_data2),
|
||||
.rx_clk(codec_data_clk_p), .rx_frame(rx_frame_p), .rx_d(rx_codec_d),
|
||||
.tx_clk(codec_fb_clk_p), .tx_frame(tx_frame_p), .tx_d(tx_codec_d)
|
||||
);
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
// SPI connections
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
wire mosi, miso, sclk; wire [7:0] sen;
|
||||
assign cat_ce = sen[0] & fx3_ce;
|
||||
assign cat_mosi = (~sen[0] & mosi) | (~fx3_ce & fx3_mosi);
|
||||
assign cat_sclk = (~sen[0] & sclk) | (~fx3_ce & fx3_sclk);
|
||||
assign miso = cat_miso;
|
||||
assign fx3_miso = ~fx3_ce & cat_miso;
|
||||
assign pll_ce = sen[1];
|
||||
assign pll_mosi = ~sen[1] & mosi;
|
||||
assign pll_sclk = ~sen[1] & sclk;
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
// bus signals
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
wire [63:0] ctrl_tdata, resp_tdata, rx_tdata, tx_tdata;
|
||||
wire ctrl_tlast, resp_tlast, rx_tlast, tx_tlast;
|
||||
wire ctrl_tvalid, resp_tvalid, rx_tvalid, tx_tvalid;
|
||||
wire ctrl_tready, resp_tready, rx_tready, tx_tready;
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
// loopback testers
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
/*
|
||||
axi_fifo #(.WIDTH(65), .SIZE(13)) f0
|
||||
(
|
||||
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
|
||||
.i_tdata({ctrl_tlast, ctrl_tdata}), .i_tvalid(ctrl_tvalid), .i_tready(ctrl_tready), .space(),
|
||||
.o_tdata({resp_tlast, resp_tdata}), .o_tvalid(resp_tvalid), .o_tready(resp_tready), .occupied()
|
||||
);
|
||||
//*/
|
||||
|
||||
/*
|
||||
axi_fifo #(.WIDTH(65), .SIZE(13)) f1
|
||||
(
|
||||
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
|
||||
.i_tdata({tx_tlast, tx_tdata}), .i_tvalid(tx_tvalid), .i_tready(tx_tready), .space(),
|
||||
.o_tdata({rx_tlast, rx_tdata}), .o_tvalid(rx_tvalid), .o_tready(rx_tready), .occupied()
|
||||
);
|
||||
//*/
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
// frontend assignments
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
wire [31:0] debug_radio;
|
||||
|
||||
wire [31:0] fe_atr1, fe_atr2;
|
||||
assign {tx_enable1, SFDX1_RX, SFDX1_TX, SRX1_RX, SRX1_TX, LED_RX1, LED_TXRX1_RX, LED_TXRX1_TX} = fe_atr1[7:0];
|
||||
assign {tx_enable2, SFDX2_RX, SFDX2_TX, SRX2_RX, SRX2_TX, LED_RX2, LED_TXRX2_RX, LED_TXRX2_TX} = fe_atr2[7:0];
|
||||
|
||||
wire [31:0] misc_outs; reg [31:0] misc_outs_r;
|
||||
always @(posedge bus_clk) misc_outs_r <= misc_outs; //register misc ios to ease routing to flop
|
||||
assign { tx_bandsel_a, tx_bandsel_b, rx_bandsel_a, rx_bandsel_b, rx_bandsel_c, codec_arst, mimo, ref_sel } = misc_outs_r[7:0];
|
||||
|
||||
assign codec_ctrl_in = 4'b1;
|
||||
assign codec_en_agc = 1'b1;
|
||||
assign codec_txrx = 1'b1;
|
||||
assign codec_enable = 1'b1;
|
||||
assign codec_reset = !reset_global; // Codec Reset // RESETB // Operates active-low
|
||||
assign codec_sync = 1'b0;
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
// b200 core
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
b200_core #(.EXTRA_BUFF_SIZE(12)) b200_xfusion_core
|
||||
(
|
||||
.bus_clk(bus_clk), .bus_rst(bus_rst),
|
||||
.tx_tdata(tx_tdata), .tx_tlast(tx_tlast), .tx_tvalid(tx_tvalid), .tx_tready(tx_tready),
|
||||
.rx_tdata(rx_tdata), .rx_tlast(rx_tlast), .rx_tvalid(rx_tvalid), .rx_tready(rx_tready),
|
||||
.ctrl_tdata(ctrl_tdata), .ctrl_tlast(ctrl_tlast), .ctrl_tvalid(ctrl_tvalid), .ctrl_tready(ctrl_tready),
|
||||
.resp_tdata(resp_tdata), .resp_tlast(resp_tlast), .resp_tvalid(resp_tvalid), .resp_tready(resp_tready),
|
||||
|
||||
.radio_clk(radio_clk), .radio_rst(radio_rst),
|
||||
.rx0(rx_data2), .rx1(rx_data1),
|
||||
.tx0(tx_data2), .tx1(tx_data1),
|
||||
.fe_atr0(fe_atr2), .fe_atr1(fe_atr1),
|
||||
.pps_int(PPS_IN_INT), .pps_ext(PPS_IN_EXT),
|
||||
|
||||
.rxd(gps_txd), .txd(gps_rxd),
|
||||
.sclk(sclk), .sen(sen), .mosi(mosi), .miso(miso),
|
||||
.rb_misc({31'b0, pll_lock}), .misc_outs(misc_outs)
|
||||
);
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
// GPIF2
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
wire [31:0] debug_gpif;
|
||||
|
||||
gpif2_slave_fifo32 #(.DATA_RX_FIFO_SIZE(14), .DATA_TX_FIFO_SIZE(14)) slave_fifo32
|
||||
(
|
||||
.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), .gpif_enb(1'b1),
|
||||
.gpif_ctl({GPIF_CTL8, GPIF_CTL6, GPIF_CTL5, GPIF_CTL4}), .fifoadr({GPIF_CTL11,GPIF_CTL12}),
|
||||
.slwr(GPIF_CTL1), .sloe(GPIF_CTL2), .slcs(GPIF_CTL0), .slrd(GPIF_CTL3), .pktend(GPIF_CTL7),
|
||||
.gpif_d(GPIF_D),
|
||||
|
||||
.fifo_clk(bus_clk), .fifo_rst(bus_rst),
|
||||
.tx_tdata(tx_tdata), .tx_tlast(tx_tlast), .tx_tvalid(tx_tvalid), .tx_tready(tx_tready),
|
||||
.rx_tdata(rx_tdata), .rx_tlast(rx_tlast), .rx_tvalid(rx_tvalid), .rx_tready(rx_tready),
|
||||
.ctrl_tdata(ctrl_tdata), .ctrl_tlast(ctrl_tlast), .ctrl_tvalid(ctrl_tvalid), .ctrl_tready(ctrl_tready),
|
||||
.resp_tdata(resp_tdata), .resp_tlast(resp_tlast), .resp_tvalid(resp_tvalid), .resp_tready(resp_tready),
|
||||
|
||||
.debug(debug_gpif)
|
||||
);
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
// Debug port
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
assign debug_clk_int = { 1'b0, 1'b0 };
|
||||
assign debug = 32'b0;
|
||||
|
||||
endmodule // B200
|
||||
@@ -0,0 +1,305 @@
|
||||
//
|
||||
// Copyright 2013 Ettus Research LLC
|
||||
//
|
||||
|
||||
|
||||
/***********************************************************
|
||||
* B200 Core Guts
|
||||
**********************************************************/
|
||||
module b200_core
|
||||
#(
|
||||
parameter R0_CTRL_SID = 8'h10,
|
||||
parameter R1_CTRL_SID = 8'h20,
|
||||
parameter U0_CTRL_SID = 8'h30,
|
||||
parameter L0_CTRL_SID = 8'h40,
|
||||
parameter R0_DATA_SID = 8'h50,
|
||||
parameter R1_DATA_SID = 8'h60,
|
||||
parameter DEMUX_SID_MASK = 8'hf0,
|
||||
parameter EXTRA_BUFF_SIZE = 0
|
||||
)
|
||||
(
|
||||
////////////////////////////////////////////////////////////////////
|
||||
// bus interfaces
|
||||
////////////////////////////////////////////////////////////////////
|
||||
input bus_clk,
|
||||
input bus_rst,
|
||||
|
||||
input [63:0] tx_tdata, input tx_tlast, input tx_tvalid, output tx_tready,
|
||||
output [63:0] rx_tdata, output rx_tlast, output rx_tvalid, input rx_tready,
|
||||
input [63:0] ctrl_tdata, input ctrl_tlast, input ctrl_tvalid, output ctrl_tready,
|
||||
output [63:0] resp_tdata, output resp_tlast, output resp_tvalid, input resp_tready,
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
// radio interfaces
|
||||
////////////////////////////////////////////////////////////////////
|
||||
input radio_clk,
|
||||
input radio_rst,
|
||||
|
||||
input [31:0] rx0, input [31:0] rx1,
|
||||
output [31:0] tx0, output [31:0] tx1,
|
||||
inout [31:0] fe_atr0,
|
||||
inout [31:0] fe_atr1,
|
||||
input pps_int, input pps_ext,
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
// gpsdo uart
|
||||
////////////////////////////////////////////////////////////////////
|
||||
input rxd,
|
||||
output txd,
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
// core interfaces
|
||||
////////////////////////////////////////////////////////////////////
|
||||
output [7:0] sen, output sclk, output mosi, input miso,
|
||||
input [31:0] rb_misc,
|
||||
output [31:0] misc_outs,
|
||||
|
||||
output [31:0] debug
|
||||
);
|
||||
localparam SR_CORE_SPI = 8'd8;
|
||||
localparam SR_CORE_MISC = 8'd16;
|
||||
localparam SR_CORE_COMPAT = 8'd24;
|
||||
localparam SR_CORE_READBACK = 8'd32;
|
||||
localparam SR_CORE_GPSDO_ST = 8'd40;
|
||||
localparam SR_CORE_PPS_SEL = 8'd48;
|
||||
localparam COMPAT_MAJOR = 16'h0002;
|
||||
localparam COMPAT_MINOR = 16'h0000;
|
||||
|
||||
/*******************************************************************
|
||||
* PPS Timing stuff
|
||||
******************************************************************/
|
||||
reg [1:0] int_pps_del, ext_pps_del;
|
||||
always @(posedge radio_clk) ext_pps_del[1:0] <= {ext_pps_del[0], pps_ext};
|
||||
always @(posedge radio_clk) int_pps_del[1:0] <= {int_pps_del[0], pps_int};
|
||||
wire pps_select;
|
||||
wire pps = pps_select? ext_pps_del[1] : int_pps_del[1];
|
||||
|
||||
/*******************************************************************
|
||||
* Response mux Routing logic
|
||||
******************************************************************/
|
||||
wire [63:0] r0_resp_tdata; wire r0_resp_tlast, r0_resp_tvalid, r0_resp_tready;
|
||||
wire [63:0] r1_resp_tdata; wire r1_resp_tlast, r1_resp_tvalid, r1_resp_tready;
|
||||
wire [63:0] u0_resp_tdata; wire u0_resp_tlast, u0_resp_tvalid, u0_resp_tready;
|
||||
wire [63:0] l0_resp_tdata; wire l0_resp_tlast, l0_resp_tvalid, l0_resp_tready;
|
||||
|
||||
axi_mux4 #(.WIDTH(64), .BUFFER(1)) mux_for_resp
|
||||
(.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
|
||||
.i0_tdata(r0_resp_tdata), .i0_tlast(r0_resp_tlast), .i0_tvalid(r0_resp_tvalid), .i0_tready(r0_resp_tready),
|
||||
.i1_tdata(r1_resp_tdata), .i1_tlast(r1_resp_tlast), .i1_tvalid(r1_resp_tvalid), .i1_tready(r1_resp_tready),
|
||||
.i2_tdata(u0_resp_tdata), .i2_tlast(u0_resp_tlast), .i2_tvalid(u0_resp_tvalid), .i2_tready(u0_resp_tready),
|
||||
.i3_tdata(l0_resp_tdata), .i3_tlast(l0_resp_tlast), .i3_tvalid(l0_resp_tvalid), .i3_tready(l0_resp_tready),
|
||||
.o_tdata(resp_tdata), .o_tlast(resp_tlast), .o_tvalid(resp_tvalid), .o_tready(resp_tready));
|
||||
|
||||
/*******************************************************************
|
||||
* Control demux Routing logic
|
||||
******************************************************************/
|
||||
wire [63:0] r0_ctrl_tdata; wire r0_ctrl_tlast, r0_ctrl_tvalid, r0_ctrl_tready;
|
||||
wire [63:0] r1_ctrl_tdata; wire r1_ctrl_tlast, r1_ctrl_tvalid, r1_ctrl_tready;
|
||||
wire [63:0] u0_ctrl_tdata; wire u0_ctrl_tlast, u0_ctrl_tvalid, u0_ctrl_tready;
|
||||
wire [63:0] l0_ctrl_tdata; wire l0_ctrl_tlast, l0_ctrl_tvalid, l0_ctrl_tready;
|
||||
|
||||
wire [63:0] ctrl_hdr;
|
||||
wire [1:0] ctrl_dst =
|
||||
((ctrl_hdr[7:0] & DEMUX_SID_MASK) == R0_CTRL_SID)? 0 : (
|
||||
((ctrl_hdr[7:0] & DEMUX_SID_MASK) == R1_CTRL_SID)? 1 : (
|
||||
((ctrl_hdr[7:0] & DEMUX_SID_MASK) == U0_CTRL_SID)? 2 : (
|
||||
((ctrl_hdr[7:0] & DEMUX_SID_MASK) == L0_CTRL_SID)? 3 : (
|
||||
3))));
|
||||
axi_demux4 #(.ACTIVE_CHAN(4'b1111), .WIDTH(64), .BUFFER(1)) demux_for_ctrl
|
||||
(.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
|
||||
.header(ctrl_hdr), .dest(ctrl_dst),
|
||||
.i_tdata(ctrl_tdata), .i_tlast(ctrl_tlast), .i_tvalid(ctrl_tvalid), .i_tready(ctrl_tready),
|
||||
.o0_tdata(r0_ctrl_tdata), .o0_tlast(r0_ctrl_tlast), .o0_tvalid(r0_ctrl_tvalid), .o0_tready(r0_ctrl_tready),
|
||||
.o1_tdata(r1_ctrl_tdata), .o1_tlast(r1_ctrl_tlast), .o1_tvalid(r1_ctrl_tvalid), .o1_tready(r1_ctrl_tready),
|
||||
.o2_tdata(u0_ctrl_tdata), .o2_tlast(u0_ctrl_tlast), .o2_tvalid(u0_ctrl_tvalid), .o2_tready(u0_ctrl_tready),
|
||||
.o3_tdata(l0_ctrl_tdata), .o3_tlast(l0_ctrl_tlast), .o3_tvalid(l0_ctrl_tvalid), .o3_tready(l0_ctrl_tready));
|
||||
|
||||
/*******************************************************************
|
||||
* UART
|
||||
******************************************************************/
|
||||
wire [63:0] u0i_ctrl_tdata; wire u0i_ctrl_tlast, u0i_ctrl_tvalid, u0i_ctrl_tready;
|
||||
|
||||
axi_fifo #(.WIDTH(65), .SIZE(0)) ushart_timing_fifo
|
||||
(
|
||||
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
|
||||
.i_tdata({u0_ctrl_tlast, u0_ctrl_tdata}), .i_tvalid(u0_ctrl_tvalid), .i_tready(u0_ctrl_tready), .space(),
|
||||
.o_tdata({u0i_ctrl_tlast, u0i_ctrl_tdata}), .o_tvalid(u0i_ctrl_tvalid), .o_tready(u0i_ctrl_tready), .occupied()
|
||||
);
|
||||
|
||||
cvita_uart #(.SIZE(7)) ushart
|
||||
(
|
||||
.clk(bus_clk), .rst(bus_rst), .rxd(rxd), .txd(txd),
|
||||
.i_tdata(u0i_ctrl_tdata), .i_tlast(u0i_ctrl_tlast), .i_tvalid(u0i_ctrl_tvalid), .i_tready(u0i_ctrl_tready),
|
||||
.o_tdata(u0_resp_tdata), .o_tlast(u0_resp_tlast), .o_tvalid(u0_resp_tvalid), .o_tready(u0_resp_tready)
|
||||
);
|
||||
|
||||
/*******************************************************************
|
||||
* Misc controls
|
||||
******************************************************************/
|
||||
wire set_stb;
|
||||
wire [7:0] set_addr;
|
||||
wire [31:0] set_data;
|
||||
|
||||
wire spi_ready;
|
||||
wire [31:0] spi_readback;
|
||||
|
||||
wire [7:0] gpsdo_st;
|
||||
wire [7:0] radio_st;
|
||||
|
||||
wire [1:0] rb_addr;
|
||||
reg [63:0] rb_data;
|
||||
|
||||
wire [63:0] l0i_ctrl_tdata; wire l0i_ctrl_tlast, l0i_ctrl_tvalid, l0i_ctrl_tready;
|
||||
|
||||
axi_fifo #(.WIDTH(65), .SIZE(0)) radio_ctrl_proc_timing_fifo
|
||||
(
|
||||
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
|
||||
.i_tdata({l0_ctrl_tlast, l0_ctrl_tdata}), .i_tvalid(l0_ctrl_tvalid), .i_tready(l0_ctrl_tready), .space(),
|
||||
.o_tdata({l0i_ctrl_tlast, l0i_ctrl_tdata}), .o_tvalid(l0i_ctrl_tvalid), .o_tready(l0i_ctrl_tready), .occupied()
|
||||
);
|
||||
|
||||
radio_ctrl_proc radio_ctrl_proc
|
||||
(.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
|
||||
.ctrl_tdata(l0i_ctrl_tdata), .ctrl_tlast(l0i_ctrl_tlast), .ctrl_tvalid(l0i_ctrl_tvalid), .ctrl_tready(l0i_ctrl_tready),
|
||||
.resp_tdata(l0_resp_tdata), .resp_tlast(l0_resp_tlast), .resp_tvalid(l0_resp_tvalid), .resp_tready(l0_resp_tready),
|
||||
.vita_time(64'b0),
|
||||
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
|
||||
.ready(spi_ready), .readback(rb_data),
|
||||
.debug());
|
||||
|
||||
setting_reg #(.my_addr(SR_CORE_MISC), .awidth(8), .width(32), .at_reset(8'h0)) sr_misc
|
||||
(.clk(bus_clk), .rst(bus_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
|
||||
.out(misc_outs), .changed());
|
||||
|
||||
setting_reg #(.my_addr(SR_CORE_READBACK), .awidth(8), .width(2)) sr_rdback
|
||||
(.clk(bus_clk), .rst(bus_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
|
||||
.out(rb_addr), .changed());
|
||||
|
||||
setting_reg #(.my_addr(SR_CORE_GPSDO_ST), .awidth(8), .width(8)) sr_gpsdo_st
|
||||
(.clk(bus_clk), .rst(1'b0/*keep*/), .strobe(set_stb), .addr(set_addr), .in(set_data),
|
||||
.out(gpsdo_st), .changed());
|
||||
|
||||
setting_reg #(.my_addr(SR_CORE_PPS_SEL), .awidth(8), .width(1)) sr_pps_sel
|
||||
(.clk(bus_clk), .rst(bus_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
|
||||
.out(pps_select), .changed());
|
||||
|
||||
simple_spi_core #(.BASE(SR_CORE_SPI), .WIDTH(8), .CLK_IDLE(0), .SEN_IDLE(8'hFF)) misc_spi
|
||||
(.clock(bus_clk), .reset(bus_rst),
|
||||
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
|
||||
.readback(spi_readback), .ready(spi_ready),
|
||||
.sen(sen), .sclk(sclk), .mosi(mosi), .miso(miso),
|
||||
.debug());
|
||||
|
||||
always @*
|
||||
case(rb_addr)
|
||||
2'd0 : rb_data <= { 32'hACE0BA5E, COMPAT_MAJOR, COMPAT_MINOR };
|
||||
2'd1 : rb_data <= { 32'b0, spi_readback };
|
||||
2'd2 : rb_data <= { 16'b0, radio_st, gpsdo_st, rb_misc };
|
||||
default : rb_data <= 64'd0;
|
||||
endcase // case (rb_addr)
|
||||
|
||||
/*******************************************************************
|
||||
* RX Data mux Routing logic
|
||||
******************************************************************/
|
||||
wire [63:0] r0_rx_tdata; wire r0_rx_tlast, r0_rx_tvalid, r0_rx_tready;
|
||||
wire [63:0] r1_rx_tdata; wire r1_rx_tlast, r1_rx_tvalid, r1_rx_tready;
|
||||
wire [63:0] rx_tdata_int; wire rx_tlast_int, rx_tvalid_int, rx_tready_int;
|
||||
|
||||
axi_mux4 #(.WIDTH(64), .BUFFER(1)) mux_for_rx
|
||||
(.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
|
||||
.i0_tdata(r0_rx_tdata), .i0_tlast(r0_rx_tlast), .i0_tvalid(r0_rx_tvalid), .i0_tready(r0_rx_tready),
|
||||
.i1_tdata(r1_rx_tdata), .i1_tlast(r1_rx_tlast), .i1_tvalid(r1_rx_tvalid), .i1_tready(r1_rx_tready),
|
||||
.i2_tdata(64'b0), .i2_tlast(1'b0), .i2_tvalid(1'b0), .i2_tready(),
|
||||
.i3_tdata(64'b0), .i3_tlast(1'b0), .i3_tvalid(1'b0), .i3_tready(),
|
||||
.o_tdata(rx_tdata_int), .o_tlast(rx_tlast_int), .o_tvalid(rx_tvalid_int), .o_tready(rx_tready_int));
|
||||
|
||||
axi_fifo #(.WIDTH(65), .SIZE(EXTRA_BUFF_SIZE)) extra_rx_buff
|
||||
(.clk(bus_clk), .reset(bus_rst),
|
||||
.i_tdata({rx_tlast_int, rx_tdata_int}), .i_tvalid(rx_tvalid_int), .i_tready(rx_tready_int),
|
||||
.o_tdata({rx_tlast, rx_tdata}), .o_tvalid(rx_tvalid), .o_tready(rx_tready));
|
||||
|
||||
/*******************************************************************
|
||||
* TX Data mux Routing logic
|
||||
******************************************************************/
|
||||
wire [63:0] r0_tx_tdata; wire r0_tx_tlast, r0_tx_tvalid, r0_tx_tready;
|
||||
wire [63:0] r1_tx_tdata; wire r1_tx_tlast, r1_tx_tvalid, r1_tx_tready;
|
||||
wire [63:0] tx_tdata_int; wire tx_tlast_int, tx_tvalid_int, tx_tready_int;
|
||||
|
||||
axi_fifo #(.WIDTH(65), .SIZE(EXTRA_BUFF_SIZE)) extra_tx_buff
|
||||
(.clk(bus_clk), .reset(bus_rst),
|
||||
.i_tdata({tx_tlast, tx_tdata}), .i_tvalid(tx_tvalid), .i_tready(tx_tready),
|
||||
.o_tdata({tx_tlast_int, tx_tdata_int}), .o_tvalid(tx_tvalid_int), .o_tready(tx_tready_int));
|
||||
|
||||
wire [63:0] tx_hdr;
|
||||
wire [1:0] tx_dst =
|
||||
((tx_hdr[7:0] & DEMUX_SID_MASK) == R0_DATA_SID)? 0 : (
|
||||
((tx_hdr[7:0] & DEMUX_SID_MASK) == R1_DATA_SID)? 1 : (
|
||||
3));
|
||||
axi_demux4 #(.ACTIVE_CHAN(4'b0011), .WIDTH(64), .BUFFER(1)) demux_for_tx
|
||||
(.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
|
||||
.header(tx_hdr), .dest(tx_dst),
|
||||
.i_tdata(tx_tdata_int), .i_tlast(tx_tlast_int), .i_tvalid(tx_tvalid_int), .i_tready(tx_tready_int),
|
||||
.o0_tdata(r0_tx_tdata), .o0_tlast(r0_tx_tlast), .o0_tvalid(r0_tx_tvalid), .o0_tready(r0_tx_tready),
|
||||
.o1_tdata(r1_tx_tdata), .o1_tlast(r1_tx_tlast), .o1_tvalid(r1_tx_tvalid), .o1_tready(r1_tx_tready),
|
||||
.o2_tdata(), .o2_tlast(), .o2_tvalid(), .o2_tready(1'b1),
|
||||
.o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b1));
|
||||
|
||||
/*******************************************************************
|
||||
* Radio 0
|
||||
******************************************************************/
|
||||
radio_b200 #(.FIFO_SIZE(13)) the_radio
|
||||
(
|
||||
.radio_clk(radio_clk), .radio_rst(radio_rst),
|
||||
.rx(rx0), .tx(tx0), .fe_atr(fe_atr0), .pps(pps),
|
||||
|
||||
.bus_clk(bus_clk), .bus_rst(bus_rst),
|
||||
.tx_tdata(r0_tx_tdata), .tx_tlast(r0_tx_tlast), .tx_tvalid(r0_tx_tvalid), .tx_tready(r0_tx_tready),
|
||||
.rx_tdata(r0_rx_tdata), .rx_tlast(r0_rx_tlast), .rx_tvalid(r0_rx_tvalid), .rx_tready(r0_rx_tready),
|
||||
.ctrl_tdata(r0_ctrl_tdata), .ctrl_tlast(r0_ctrl_tlast), .ctrl_tvalid(r0_ctrl_tvalid), .ctrl_tready(r0_ctrl_tready),
|
||||
.resp_tdata(r0_resp_tdata), .resp_tlast(r0_resp_tlast), .resp_tvalid(r0_resp_tvalid), .resp_tready(r0_resp_tready),
|
||||
|
||||
.debug()
|
||||
);
|
||||
|
||||
/*******************************************************************
|
||||
* Radio 1
|
||||
******************************************************************/
|
||||
`ifdef B200_CAN_HAZ_R1
|
||||
assign radio_st = 8'h2;
|
||||
|
||||
radio_b200 #(.FIFO_SIZE(13)) the_radio_1
|
||||
(
|
||||
.radio_clk(radio_clk), .radio_rst(radio_rst),
|
||||
.rx(rx1), .tx(tx1), .fe_atr(fe_atr1), .pps(pps),
|
||||
|
||||
.bus_clk(bus_clk), .bus_rst(bus_rst),
|
||||
.tx_tdata(r1_tx_tdata), .tx_tlast(r1_tx_tlast), .tx_tvalid(r1_tx_tvalid), .tx_tready(r1_tx_tready),
|
||||
.rx_tdata(r1_rx_tdata), .rx_tlast(r1_rx_tlast), .rx_tvalid(r1_rx_tvalid), .rx_tready(r1_rx_tready),
|
||||
.ctrl_tdata(r1_ctrl_tdata), .ctrl_tlast(r1_ctrl_tlast), .ctrl_tvalid(r1_ctrl_tvalid), .ctrl_tready(r1_ctrl_tready),
|
||||
.resp_tdata(r1_resp_tdata), .resp_tlast(r1_resp_tlast), .resp_tvalid(r1_resp_tvalid), .resp_tready(r1_resp_tready),
|
||||
|
||||
.debug()
|
||||
);
|
||||
|
||||
`else
|
||||
assign radio_st = 8'h1;
|
||||
|
||||
//assign undriven outputs
|
||||
assign fe_atr1 = 8'b0;
|
||||
assign tx1 = 32'b0;
|
||||
|
||||
//unused control signals -- leave in loopback
|
||||
assign r1_resp_tdata = r1_ctrl_tdata;
|
||||
assign r1_resp_tlast = r1_ctrl_tlast;
|
||||
assign r1_resp_tvalid = r1_ctrl_tvalid;
|
||||
assign r1_ctrl_tready = r1_resp_tready;
|
||||
|
||||
//unused data signals -- leave in loopback
|
||||
assign r1_rx_tdata = r1_tx_tdata;
|
||||
assign r1_rx_tlast = r1_tx_tlast;
|
||||
assign r1_rx_tvalid = r1_tx_tvalid;
|
||||
assign r1_tx_tready = r1_tx_tready;
|
||||
|
||||
`endif
|
||||
|
||||
endmodule // b200_core
|
||||
@@ -0,0 +1,68 @@
|
||||
|
||||
|
||||
module catcap_ddr_cmos
|
||||
(input data_clk,
|
||||
input reset,
|
||||
input mimo,
|
||||
input rx_frame,
|
||||
input [11:0] rx_d,
|
||||
output rx_clk, output rx_strobe,
|
||||
output reg [11:0] i0, output reg [11:0] q0,
|
||||
output reg [11:0] i1, output reg [11:0] q1);
|
||||
|
||||
//IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE"))
|
||||
//clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n));
|
||||
|
||||
wire [11:0] i,q;
|
||||
wire frame_0, frame_1;
|
||||
|
||||
genvar z;
|
||||
|
||||
generate
|
||||
for(z = 0; z < 12; z = z + 1)
|
||||
begin : gen_pins
|
||||
IDDR2 #(.DDR_ALIGNMENT("C0")) iddr2
|
||||
(.Q0(q[z]), .Q1(i[z]), .C0(data_clk), .C1(~data_clk),
|
||||
.CE(1'b1), .D(rx_d[z]), .R(1'b0), .S(1'b0));
|
||||
end
|
||||
endgenerate
|
||||
IDDR2 #(.DDR_ALIGNMENT("C0")) iddr2_frame
|
||||
(.Q0(frame_0), .Q1(frame_1), .C0(data_clk), .C1(~data_clk),
|
||||
.CE(1'b1), .D(rx_frame), .R(1'b0), .S(1'b0));
|
||||
|
||||
reg frame_d1, frame_d2;
|
||||
always @(posedge data_clk)
|
||||
if(reset)
|
||||
{ frame_d2, frame_d1 } <= 0;
|
||||
else if(~mimo)
|
||||
{ frame_d2, frame_d1 } <= { frame_1, 1'b0 };
|
||||
else
|
||||
{ frame_d2, frame_d1 } <= { frame_d1, frame_1 };
|
||||
|
||||
assign rx_strobe = frame_d2;
|
||||
|
||||
reg [11:0] i_del, q_del;
|
||||
always @(posedge data_clk)
|
||||
if(mimo)
|
||||
if(frame_0)
|
||||
begin
|
||||
i_del <= i;
|
||||
q_del <= q;
|
||||
end
|
||||
else
|
||||
begin
|
||||
i1 <= i;
|
||||
q1 <= q;
|
||||
i0 <= i_del;
|
||||
q0 <= q_del;
|
||||
end
|
||||
else
|
||||
begin
|
||||
i0 <= i;
|
||||
q0 <= q;
|
||||
i1 <= i;
|
||||
q1 <= q;
|
||||
end
|
||||
assign rx_clk = data_clk;
|
||||
|
||||
endmodule // catcap_ddr_cmos
|
||||
Executable
+21
@@ -0,0 +1,21 @@
|
||||
|
||||
#!/bin/sh
|
||||
|
||||
rm -rf isim*
|
||||
rm -rf catcap_tb
|
||||
rm -rf fuse*
|
||||
\
|
||||
# --sourcelibdir ../../models \
|
||||
|
||||
vlogcomp \
|
||||
--sourcelibext .v \
|
||||
--sourcelibdir ../../coregen \
|
||||
--sourcelibdir ../../control_lib \
|
||||
--sourcelibdir . \
|
||||
--sourcelibdir $XILINX/verilog/src \
|
||||
--sourcelibdir $XILINX/verilog/src/unisims \
|
||||
--work work \
|
||||
catcap_tb.v
|
||||
|
||||
|
||||
fuse -o catcap_tb catcap_tb
|
||||
@@ -0,0 +1,109 @@
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module catcap_tb();
|
||||
|
||||
wire GSR, GTS;
|
||||
glbl glbl( );
|
||||
|
||||
reg clk = 0;
|
||||
reg ddrclk = 0;
|
||||
reg reset = 1;
|
||||
|
||||
always #100 clk = ~clk;
|
||||
always @(negedge clk) ddrclk <= ~ddrclk;
|
||||
|
||||
initial $dumpfile("catcap_tb.vcd");
|
||||
initial $dumpvars(0,catcap_tb);
|
||||
|
||||
wire [11:0] i0 = {4'hA,count};
|
||||
wire [11:0] q0 = {4'hB,count};
|
||||
wire [11:0] i1 = {4'hC,count};
|
||||
wire [11:0] q1 = {4'hD,count};
|
||||
|
||||
reg mimo;
|
||||
reg [11:0] pins;
|
||||
reg frame;
|
||||
reg [7:0] count;
|
||||
|
||||
initial
|
||||
begin
|
||||
#1000 reset = 0;
|
||||
MIMO_BURST(4);
|
||||
MIMO_BURST(5);
|
||||
BURST(4);
|
||||
BURST(5);
|
||||
#2000;
|
||||
$finish;
|
||||
end
|
||||
|
||||
task BURST;
|
||||
input [7:0] len;
|
||||
begin
|
||||
frame <= 0;
|
||||
@(posedge clk);
|
||||
@(posedge clk);
|
||||
mimo <= 0;
|
||||
@(posedge clk);
|
||||
@(posedge clk);
|
||||
@(posedge clk);
|
||||
@(posedge ddrclk);
|
||||
count <= 0;
|
||||
repeat(len)
|
||||
begin
|
||||
@(posedge clk);
|
||||
pins <= i0;
|
||||
frame <= 1;
|
||||
@(posedge clk);
|
||||
pins <= q0;
|
||||
frame <= 0;
|
||||
count <= count + 1;
|
||||
end
|
||||
end
|
||||
endtask // BURST
|
||||
|
||||
task MIMO_BURST;
|
||||
input [7:0] len;
|
||||
begin
|
||||
frame <= 0;
|
||||
@(posedge clk);
|
||||
@(posedge clk);
|
||||
mimo <= 1;
|
||||
@(posedge clk);
|
||||
@(posedge clk);
|
||||
@(posedge clk);
|
||||
@(posedge ddrclk);
|
||||
count <= 0;
|
||||
repeat(len)
|
||||
begin
|
||||
@(posedge clk);
|
||||
pins <= i0;
|
||||
frame <= 1;
|
||||
@(posedge clk);
|
||||
pins <= q0;
|
||||
@(posedge clk);
|
||||
pins <= i1;
|
||||
frame <= 0;
|
||||
@(posedge clk);
|
||||
pins <= q1;
|
||||
count <= count + 1;
|
||||
end
|
||||
@(posedge clk);
|
||||
@(posedge clk);
|
||||
end
|
||||
endtask // MIMO_BURST
|
||||
|
||||
wire rx_clk, rx_strobe;
|
||||
wire [11:0] i0o,i1o,q0o,q1o;
|
||||
|
||||
catcap_ddr_cmos catcap
|
||||
(.data_clk(ddrclk),
|
||||
.reset(reset),
|
||||
.mimo(mimo),
|
||||
.rx_frame(frame),
|
||||
.rx_d(pins),
|
||||
.rx_clk(rx_clk),
|
||||
.rx_strobe(rx_strobe),
|
||||
.i0(i0o),.q0(q0o),
|
||||
.i1(i1o),.q1(q1o));
|
||||
|
||||
endmodule // hb_chain_tb
|
||||
@@ -0,0 +1,85 @@
|
||||
|
||||
|
||||
module catcodec_ddr_cmos
|
||||
(
|
||||
//output source sync clock for baseband data
|
||||
output radio_clk,
|
||||
|
||||
//async reset for clocking
|
||||
input arst,
|
||||
|
||||
//control mimo mode
|
||||
input mimo,
|
||||
|
||||
//baseband sample interface
|
||||
output reg [31:0] rx1,
|
||||
output reg [31:0] rx2,
|
||||
input [31:0] tx1,
|
||||
input [31:0] tx2,
|
||||
|
||||
//capture interface
|
||||
input rx_clk,
|
||||
input rx_frame,
|
||||
input [11:0] rx_d,
|
||||
|
||||
//generate interface
|
||||
output tx_clk,
|
||||
output tx_frame,
|
||||
output [11:0] tx_d
|
||||
);
|
||||
|
||||
//rx_clk to DCM - creates codec_clk and codec_clk/2
|
||||
wire clk0, clkdv;
|
||||
wire locked;
|
||||
wire codec_rst = !locked;
|
||||
|
||||
DCM_SP #(
|
||||
.CLKDV_DIVIDE(2),
|
||||
.CLK_FEEDBACK("1X")
|
||||
) DCM_SP_codec_clk
|
||||
(
|
||||
.RST(arst),
|
||||
.CLKIN(rx_clk), .CLKFB(clk0),
|
||||
.CLK0(clk0), .CLKDV(clkdv),
|
||||
.LOCKED(locked)
|
||||
);
|
||||
|
||||
wire codec_clk, half_clk;
|
||||
BUFG BUFG_codec_clk(.I(clk0), .O(codec_clk));
|
||||
BUFG BUFG_half_clk(.I(clkdv), .O(half_clk));
|
||||
BUFGMUX BUFGMUX_radio_clk (.I0(codec_clk), .I1(half_clk), .S(mimo), .O(radio_clk));
|
||||
|
||||
//make codec clock domain mimo mode signal
|
||||
reg mimo_r;
|
||||
always @(posedge codec_clk) mimo_r <= mimo;
|
||||
|
||||
//assign baseband sample interfaces
|
||||
//all samples are registered on strobe
|
||||
wire rx_strobe, tx_strobe;
|
||||
wire [11:0] rx_i0, rx_q0, rx_i1, rx_q1;
|
||||
reg [11:0] tx_i0, tx_q0, tx_i1, tx_q1;
|
||||
//tx mux to feed single channel mode from either input
|
||||
wire [31:0] txm = (mimo_r || (tx1 != 32'b0))? tx1: tx2;
|
||||
always @(posedge codec_clk) begin
|
||||
if (rx_strobe) rx2 <= {rx_i1, 4'b0, rx_q1, 4'b0};
|
||||
if (rx_strobe) rx1 <= {rx_i0, 4'b0, rx_q0, 4'b0};
|
||||
if (tx_strobe) {tx_i0, tx_q0} <= {txm[31:20], txm[15:4]};
|
||||
if (tx_strobe) {tx_i1, tx_q1} <= {tx2[31:20], tx2[15:4]};
|
||||
end
|
||||
|
||||
// CMOS Data interface to catalina, ignore _n pins
|
||||
catcap_ddr_cmos catcap
|
||||
(.data_clk(codec_clk), .reset(codec_rst), .mimo(mimo_r),
|
||||
.rx_frame(rx_frame), .rx_d(rx_d),
|
||||
.rx_clk(/*out*/), .rx_strobe(rx_strobe),
|
||||
.i0(rx_i0), .q0(rx_q0),
|
||||
.i1(rx_i1), .q1(rx_q1));
|
||||
|
||||
catgen_ddr_cmos catgen
|
||||
(.data_clk(tx_clk), .reset(codec_rst), .mimo(mimo_r),
|
||||
.tx_frame(tx_frame), .tx_d(tx_d),
|
||||
.tx_clk(codec_clk), .tx_strobe(tx_strobe),
|
||||
.i0(tx_i0), .q0(tx_q0),
|
||||
.i1(tx_i1), .q1(tx_q1));
|
||||
|
||||
endmodule // catcodec_ddr_cmos
|
||||
@@ -0,0 +1,49 @@
|
||||
|
||||
|
||||
module catgen_ddr_cmos
|
||||
(output data_clk,
|
||||
input reset,
|
||||
input mimo,
|
||||
output tx_frame,
|
||||
output [11:0] tx_d,
|
||||
input tx_clk, output reg tx_strobe,
|
||||
input [11:0] i0, input [11:0] q0,
|
||||
input [11:0] i1, input [11:0] q1);
|
||||
|
||||
//IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE"))
|
||||
//clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n));
|
||||
|
||||
reg [11:0] i,q;
|
||||
genvar z;
|
||||
reg tx_strobe_d;
|
||||
|
||||
generate
|
||||
for(z = 0; z < 12; z = z + 1)
|
||||
begin : gen_pins
|
||||
ODDR2 #(.DDR_ALIGNMENT("C0"),.SRTYPE("ASYNC")) oddr2
|
||||
(.Q(tx_d[z]), .C0(tx_clk), .C1(~tx_clk),
|
||||
.CE(1'b1), .D0(i[z]), .D1(q[z]), .R(1'b0), .S(1'b0));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
ODDR2 #(.DDR_ALIGNMENT("C0"),.SRTYPE("ASYNC")) oddr2_frame
|
||||
(.Q(tx_frame), .C0(tx_clk), .C1(~tx_clk),
|
||||
.CE(1'b1), .D0(tx_strobe_d), .D1(mimo&tx_strobe_d), .R(1'b0), .S(1'b0));
|
||||
|
||||
ODDR2 #(.DDR_ALIGNMENT("C0"),.SRTYPE("ASYNC")) oddr2_clk
|
||||
(.Q(data_clk), .C0(tx_clk), .C1(~tx_clk),
|
||||
.CE(1'b1), .D0(1'b1), .D1(1'b0), .R(1'b0), .S(1'b0));
|
||||
|
||||
always @(posedge tx_clk)
|
||||
tx_strobe <= (mimo)? ~tx_strobe : 1'b1;
|
||||
|
||||
always @(posedge tx_clk)
|
||||
tx_strobe_d <= tx_strobe;
|
||||
|
||||
always @(posedge tx_clk)
|
||||
if(tx_strobe)
|
||||
{i,q} <= {i0,q0};
|
||||
else
|
||||
{i,q} <= {i1,q1};
|
||||
|
||||
endmodule // catgen_ddr_cmos
|
||||
Executable
+21
@@ -0,0 +1,21 @@
|
||||
|
||||
#!/bin/sh
|
||||
|
||||
rm -rf isim*
|
||||
rm -rf catgen_tb
|
||||
rm -rf fuse*
|
||||
\
|
||||
# --sourcelibdir ../../models \
|
||||
|
||||
vlogcomp \
|
||||
--sourcelibext .v \
|
||||
--sourcelibdir ../../coregen \
|
||||
--sourcelibdir ../../control_lib \
|
||||
--sourcelibdir . \
|
||||
--sourcelibdir $XILINX/verilog/src \
|
||||
--sourcelibdir $XILINX/verilog/src/unisims \
|
||||
--work work \
|
||||
catgen_tb.v
|
||||
|
||||
|
||||
fuse -o catgen_tb catgen_tb
|
||||
@@ -0,0 +1,97 @@
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module catgen_tb();
|
||||
|
||||
wire GSR, GTS;
|
||||
glbl glbl( );
|
||||
|
||||
reg clk = 0;
|
||||
reg reset = 1;
|
||||
wire ddrclk;
|
||||
|
||||
always #100 clk = ~clk;
|
||||
|
||||
initial $dumpfile("catgen_tb.vcd");
|
||||
initial $dumpvars(0,catgen_tb);
|
||||
|
||||
wire [11:0] pins;
|
||||
wire frame;
|
||||
|
||||
reg mimo;
|
||||
reg [7:0] count;
|
||||
reg tx_strobe;
|
||||
|
||||
wire [11:0] i0 = {4'hA,count};
|
||||
wire [11:0] q0 = {4'hB,count};
|
||||
wire [11:0] i1 = {4'hC,count};
|
||||
wire [11:0] q1 = {4'hD,count};
|
||||
|
||||
initial
|
||||
begin
|
||||
#1000 reset = 0;
|
||||
BURST(4);
|
||||
BURST(5);
|
||||
MIMO_BURST(4);
|
||||
MIMO_BURST(5);
|
||||
#2000;
|
||||
$finish;
|
||||
end
|
||||
|
||||
task BURST;
|
||||
input [7:0] len;
|
||||
|
||||
begin
|
||||
tx_strobe <= 0;
|
||||
mimo <= 0;
|
||||
count <= 0;
|
||||
@(posedge clk);
|
||||
@(posedge clk);
|
||||
repeat(len)
|
||||
begin
|
||||
tx_strobe <= 1;
|
||||
@(posedge clk);
|
||||
count <= count + 1;
|
||||
end
|
||||
tx_strobe <= 0;
|
||||
@(posedge clk);
|
||||
@(posedge clk);
|
||||
@(posedge clk);
|
||||
end
|
||||
endtask // BURST
|
||||
|
||||
task MIMO_BURST;
|
||||
input [7:0] len;
|
||||
|
||||
begin
|
||||
tx_strobe <= 0;
|
||||
mimo <= 1;
|
||||
count <= 0;
|
||||
@(posedge clk);
|
||||
@(posedge clk);
|
||||
repeat(len)
|
||||
begin
|
||||
tx_strobe <= 1;
|
||||
@(posedge clk);
|
||||
tx_strobe <= 0;
|
||||
@(posedge clk);
|
||||
count <= count + 1;
|
||||
end
|
||||
tx_strobe <= 0;
|
||||
@(posedge clk);
|
||||
@(posedge clk);
|
||||
@(posedge clk);
|
||||
end
|
||||
endtask // BURST
|
||||
|
||||
catgen_ddr_cmos catgen
|
||||
(.data_clk(ddrclk),
|
||||
.reset(reset),
|
||||
.mimo(mimo),
|
||||
.tx_frame(frame),
|
||||
.tx_d(pins),
|
||||
.tx_clk(clk),
|
||||
.tx_strobe(tx_strobe),
|
||||
.i0(i0),.q0(q0),
|
||||
.i1(i1),.q1(q1));
|
||||
|
||||
endmodule // hb_chain_tb
|
||||
@@ -0,0 +1 @@
|
||||
iverilog ../top/b200/b200.v -y control/ -y timing/ -y fifo/ -y vita/ -y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ -y ../top/b200/ -y ../top/b200/coregen/ -y gpif2/ -y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/XilinxCoreLib/ -Wall | grep -v timescale
|
||||
Executable
+1
@@ -0,0 +1 @@
|
||||
iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpif2/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac B200.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models
|
||||
@@ -0,0 +1,3 @@
|
||||
/tmp
|
||||
/_xmsgs
|
||||
/*.log
|
||||
@@ -0,0 +1,9 @@
|
||||
Version 4
|
||||
SymbolType BLOCK
|
||||
TEXT 32 32 LEFT 4 b200_chipscope_icon
|
||||
RECTANGLE Normal 32 32 544 864
|
||||
LINE Wide 576 112 544 112
|
||||
PIN 576 112 RIGHT 36
|
||||
PINATTR PinName control0[35:0]
|
||||
PINATTR Polarity BOTH
|
||||
|
||||
@@ -0,0 +1,9 @@
|
||||
NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;
|
||||
TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;
|
||||
#Update Constraints
|
||||
NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;
|
||||
NET "U0/iSHIFT_OUT" TIG ;
|
||||
TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;
|
||||
TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;
|
||||
TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;
|
||||
TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;
|
||||
@@ -0,0 +1,7 @@
|
||||
# icon XDC
|
||||
create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}]
|
||||
create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}]
|
||||
set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}]
|
||||
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2
|
||||
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1
|
||||
set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK}
|
||||
@@ -0,0 +1,31 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="b200_chipscope_icon.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="b200_chipscope_icon.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VEO" xil_pn:name="b200_chipscope_icon.veo" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
|
||||
|
||||
</generated_project>
|
||||
File diff suppressed because one or more lines are too long
@@ -0,0 +1,9 @@
|
||||
NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;
|
||||
TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;
|
||||
#Update Constraints
|
||||
NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;
|
||||
NET "U0/iSHIFT_OUT" TIG ;
|
||||
TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;
|
||||
TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;
|
||||
TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;
|
||||
TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;
|
||||
@@ -0,0 +1,27 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 2013 Xilinx, Inc.
|
||||
// All Rights Reserved
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor : Xilinx
|
||||
// \ \ \/ Version : 14.4
|
||||
// \ \ Application: Xilinx CORE Generator
|
||||
// / / Filename : b200_chipscope_icon.v
|
||||
// /___/ /\ Timestamp : Tue Feb 19 14:28:40 PST 2013
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
// Design Name: Verilog Synthesis Wrapper
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// This wrapper is used to integrate with Project Navigator and PlanAhead
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module b200_chipscope_icon(
|
||||
CONTROL0) /* synthesis syn_black_box syn_noprune=1 */;
|
||||
|
||||
|
||||
inout [35 : 0] CONTROL0;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,28 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 2013 Xilinx, Inc.
|
||||
// All Rights Reserved
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor : Xilinx
|
||||
// \ \ \/ Version : 14.4
|
||||
// \ \ Application: Xilinx CORE Generator
|
||||
// / / Filename : b200_chipscope_icon.veo
|
||||
// /___/ /\ Timestamp : Tue Feb 19 14:28:40 PST 2013
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
// Design Name: ISE Instantiation template
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
b200_chipscope_icon YourInstanceName (
|
||||
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
|
||||
);
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
@@ -0,0 +1,56 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.4
|
||||
# Date: Tue Feb 19 22:27:58 2013
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = Verilog
|
||||
SET device = xc6slx75
|
||||
SET devicefamily = spartan6
|
||||
SET flowvendor = Foundation_ISE
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = fgg484
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -3
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = false
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET component_name=b200_chipscope_icon
|
||||
CSET constraint_type=external
|
||||
CSET enable_jtag_bufg=true
|
||||
CSET example_design=false
|
||||
CSET number_control_ports=1
|
||||
CSET use_ext_bscan=false
|
||||
CSET use_softbscan=false
|
||||
CSET use_unused_bscan=false
|
||||
CSET user_scan_chain=USER1
|
||||
# END Parameters
|
||||
# BEGIN Extra information
|
||||
MISC pkg_timestamp=2012-12-18T02:47:25Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: 729764e8
|
||||
@@ -0,0 +1,7 @@
|
||||
# icon XDC
|
||||
create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}]
|
||||
create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}]
|
||||
set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}]
|
||||
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2
|
||||
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1
|
||||
set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK}
|
||||
@@ -0,0 +1,73 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="b200_chipscope_icon.ngc" xil_pn:type="FILE_NGC">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="b200_chipscope_icon.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Module|b200_chipscope_icon" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="b200_chipscope_icon.ngc" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/b200_chipscope_icon" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="b200_chipscope_icon" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-02-19T14:28:45" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="A24BB47ADAFD196B0AED5F1EDE7080BB" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
@@ -0,0 +1,15 @@
|
||||
# Output products list for <b200_chipscope_icon>
|
||||
b200_chipscope_icon.asy
|
||||
b200_chipscope_icon.constraints/b200_chipscope_icon.ucf
|
||||
b200_chipscope_icon.constraints/b200_chipscope_icon.xdc
|
||||
b200_chipscope_icon.gise
|
||||
b200_chipscope_icon.ngc
|
||||
b200_chipscope_icon.ucf
|
||||
b200_chipscope_icon.v
|
||||
b200_chipscope_icon.veo
|
||||
b200_chipscope_icon.xco
|
||||
b200_chipscope_icon.xdc
|
||||
b200_chipscope_icon.xise
|
||||
b200_chipscope_icon_flist.txt
|
||||
b200_chipscope_icon_readme.txt
|
||||
b200_chipscope_icon_xmdf.tcl
|
||||
@@ -0,0 +1,45 @@
|
||||
The following files were generated for 'b200_chipscope_icon' in directory
|
||||
/home/bhilburn/xilinx/
|
||||
|
||||
XCO file generator:
|
||||
Generate an XCO file for compatibility with legacy flows.
|
||||
|
||||
* b200_chipscope_icon.xco
|
||||
|
||||
Creates an implementation netlist:
|
||||
Creates an implementation netlist for the IP.
|
||||
|
||||
* b200_chipscope_icon.constraints/b200_chipscope_icon.ucf
|
||||
* b200_chipscope_icon.constraints/b200_chipscope_icon.xdc
|
||||
* b200_chipscope_icon.ngc
|
||||
* b200_chipscope_icon.ucf
|
||||
* b200_chipscope_icon.v
|
||||
* b200_chipscope_icon.veo
|
||||
* b200_chipscope_icon.xdc
|
||||
* b200_chipscope_icon_xmdf.tcl
|
||||
|
||||
IP Symbol Generator:
|
||||
Generate an IP symbol based on the current project options'.
|
||||
|
||||
* b200_chipscope_icon.asy
|
||||
|
||||
Generate ISE subproject:
|
||||
Create an ISE subproject for use when including this core in ISE designs
|
||||
|
||||
* b200_chipscope_icon.gise
|
||||
* b200_chipscope_icon.xise
|
||||
|
||||
Deliver Readme:
|
||||
Readme file for the IP.
|
||||
|
||||
* b200_chipscope_icon_readme.txt
|
||||
|
||||
Generate FLIST file:
|
||||
Text file listing all of the output files produced when a customized core was
|
||||
generated in the CORE Generator.
|
||||
|
||||
* b200_chipscope_icon_flist.txt
|
||||
|
||||
Please see the Xilinx CORE Generator online help for further details on
|
||||
generated files and how to use them.
|
||||
|
||||
+88
@@ -0,0 +1,88 @@
|
||||
# The package naming convention is <core_name>_xmdf
|
||||
package provide b200_chipscope_icon_xmdf 1.0
|
||||
|
||||
# This includes some utilities that support common XMDF operations
|
||||
package require utilities_xmdf
|
||||
|
||||
# Define a namespace for this package. The name of the name space
|
||||
# is <core_name>_xmdf
|
||||
namespace eval ::b200_chipscope_icon_xmdf {
|
||||
# Use this to define any statics
|
||||
}
|
||||
|
||||
# Function called by client to rebuild the params and port arrays
|
||||
# Optional when the use context does not require the param or ports
|
||||
# arrays to be available.
|
||||
proc ::b200_chipscope_icon_xmdf::xmdfInit { instance } {
|
||||
# Variable containing name of library into which module is compiled
|
||||
# Recommendation: <module_name>
|
||||
# Required
|
||||
utilities_xmdf::xmdfSetData $instance Module Attributes Name b200_chipscope_icon
|
||||
}
|
||||
# ::b200_chipscope_icon_xmdf::xmdfInit
|
||||
|
||||
# Function called by client to fill in all the xmdf* data variables
|
||||
# based on the current settings of the parameters
|
||||
proc ::b200_chipscope_icon_xmdf::xmdfApplyParams { instance } {
|
||||
|
||||
set fcount 0
|
||||
# Array containing libraries that are assumed to exist
|
||||
# Examples include unisim and xilinxcorelib
|
||||
# Optional
|
||||
# In this example, we assume that the unisim library will
|
||||
# be available to the simulation and synthesis tool
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
|
||||
incr fcount
|
||||
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.asy
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.constraints/b200_chipscope_icon.ucf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.ncf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.constraints/b200_chipscope_icon.xdc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.xcf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.ngc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.veo
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.xco
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon_xmdf.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module b200_chipscope_icon
|
||||
incr fcount
|
||||
|
||||
}
|
||||
|
||||
# ::gen_comp_name_xmdf::xmdfApplyParams
|
||||
|
||||
|
||||
@@ -0,0 +1,21 @@
|
||||
Version 4
|
||||
SymbolType BLOCK
|
||||
TEXT 32 32 LEFT 4 b200_chipscope_ila
|
||||
RECTANGLE Normal 32 32 288 704
|
||||
LINE Wide 0 80 32 80
|
||||
PIN 0 80 LEFT 36
|
||||
PINATTR PinName control[35:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 112 32 112
|
||||
PIN 0 112 LEFT 36
|
||||
PINATTR PinName clk
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 144 32 144
|
||||
PIN 0 144 LEFT 36
|
||||
PINATTR PinName data[63:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 176 32 176
|
||||
PIN 0 176 LEFT 36
|
||||
PINATTR PinName trig0[7:0]
|
||||
PINATTR Polarity IN
|
||||
|
||||
@@ -0,0 +1,83 @@
|
||||
#ChipScope Core Generator Project File Version 3.0
|
||||
#Tue Feb 19 16:52:47 PST 2013
|
||||
SignalExport.clockChannel=CLK
|
||||
SignalExport.dataChannel<0000>=DATA[0]
|
||||
SignalExport.dataChannel<0001>=DATA[1]
|
||||
SignalExport.dataChannel<0002>=DATA[2]
|
||||
SignalExport.dataChannel<0003>=DATA[3]
|
||||
SignalExport.dataChannel<0004>=DATA[4]
|
||||
SignalExport.dataChannel<0005>=DATA[5]
|
||||
SignalExport.dataChannel<0006>=DATA[6]
|
||||
SignalExport.dataChannel<0007>=DATA[7]
|
||||
SignalExport.dataChannel<0008>=DATA[8]
|
||||
SignalExport.dataChannel<0009>=DATA[9]
|
||||
SignalExport.dataChannel<0010>=DATA[10]
|
||||
SignalExport.dataChannel<0011>=DATA[11]
|
||||
SignalExport.dataChannel<0012>=DATA[12]
|
||||
SignalExport.dataChannel<0013>=DATA[13]
|
||||
SignalExport.dataChannel<0014>=DATA[14]
|
||||
SignalExport.dataChannel<0015>=DATA[15]
|
||||
SignalExport.dataChannel<0016>=DATA[16]
|
||||
SignalExport.dataChannel<0017>=DATA[17]
|
||||
SignalExport.dataChannel<0018>=DATA[18]
|
||||
SignalExport.dataChannel<0019>=DATA[19]
|
||||
SignalExport.dataChannel<0020>=DATA[20]
|
||||
SignalExport.dataChannel<0021>=DATA[21]
|
||||
SignalExport.dataChannel<0022>=DATA[22]
|
||||
SignalExport.dataChannel<0023>=DATA[23]
|
||||
SignalExport.dataChannel<0024>=DATA[24]
|
||||
SignalExport.dataChannel<0025>=DATA[25]
|
||||
SignalExport.dataChannel<0026>=DATA[26]
|
||||
SignalExport.dataChannel<0027>=DATA[27]
|
||||
SignalExport.dataChannel<0028>=DATA[28]
|
||||
SignalExport.dataChannel<0029>=DATA[29]
|
||||
SignalExport.dataChannel<0030>=DATA[30]
|
||||
SignalExport.dataChannel<0031>=DATA[31]
|
||||
SignalExport.dataChannel<0032>=DATA[32]
|
||||
SignalExport.dataChannel<0033>=DATA[33]
|
||||
SignalExport.dataChannel<0034>=DATA[34]
|
||||
SignalExport.dataChannel<0035>=DATA[35]
|
||||
SignalExport.dataChannel<0036>=DATA[36]
|
||||
SignalExport.dataChannel<0037>=DATA[37]
|
||||
SignalExport.dataChannel<0038>=DATA[38]
|
||||
SignalExport.dataChannel<0039>=DATA[39]
|
||||
SignalExport.dataChannel<0040>=DATA[40]
|
||||
SignalExport.dataChannel<0041>=DATA[41]
|
||||
SignalExport.dataChannel<0042>=DATA[42]
|
||||
SignalExport.dataChannel<0043>=DATA[43]
|
||||
SignalExport.dataChannel<0044>=DATA[44]
|
||||
SignalExport.dataChannel<0045>=DATA[45]
|
||||
SignalExport.dataChannel<0046>=DATA[46]
|
||||
SignalExport.dataChannel<0047>=DATA[47]
|
||||
SignalExport.dataChannel<0048>=DATA[48]
|
||||
SignalExport.dataChannel<0049>=DATA[49]
|
||||
SignalExport.dataChannel<0050>=DATA[50]
|
||||
SignalExport.dataChannel<0051>=DATA[51]
|
||||
SignalExport.dataChannel<0052>=DATA[52]
|
||||
SignalExport.dataChannel<0053>=DATA[53]
|
||||
SignalExport.dataChannel<0054>=DATA[54]
|
||||
SignalExport.dataChannel<0055>=DATA[55]
|
||||
SignalExport.dataChannel<0056>=DATA[56]
|
||||
SignalExport.dataChannel<0057>=DATA[57]
|
||||
SignalExport.dataChannel<0058>=DATA[58]
|
||||
SignalExport.dataChannel<0059>=DATA[59]
|
||||
SignalExport.dataChannel<0060>=DATA[60]
|
||||
SignalExport.dataChannel<0061>=DATA[61]
|
||||
SignalExport.dataChannel<0062>=DATA[62]
|
||||
SignalExport.dataChannel<0063>=DATA[63]
|
||||
SignalExport.dataEqualsTrigger=false
|
||||
SignalExport.dataPortWidth=64
|
||||
SignalExport.triggerChannel<0000><0000>=TRIG0[0]
|
||||
SignalExport.triggerChannel<0000><0001>=TRIG0[1]
|
||||
SignalExport.triggerChannel<0000><0002>=TRIG0[2]
|
||||
SignalExport.triggerChannel<0000><0003>=TRIG0[3]
|
||||
SignalExport.triggerChannel<0000><0004>=TRIG0[4]
|
||||
SignalExport.triggerChannel<0000><0005>=TRIG0[5]
|
||||
SignalExport.triggerChannel<0000><0006>=TRIG0[6]
|
||||
SignalExport.triggerChannel<0000><0007>=TRIG0[7]
|
||||
SignalExport.triggerPort<0000>.name=TRIG0
|
||||
SignalExport.triggerPortCount=1
|
||||
SignalExport.triggerPortIsData<0000>=false
|
||||
SignalExport.triggerPortWidth<0000>=8
|
||||
SignalExport.type=ila
|
||||
|
||||
@@ -0,0 +1,17 @@
|
||||
#
|
||||
# Clock constraints
|
||||
#
|
||||
NET "CLK" TNM_NET = D_CLK ;
|
||||
INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK;
|
||||
TIMESPEC TS_D2_TO_T2_b200_chipscope_ila = FROM D2_CLK TO "FFS" TIG;
|
||||
TIMESPEC TS_J2_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
|
||||
TIMESPEC TS_J3_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
|
||||
TIMESPEC TS_J4_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
|
||||
|
||||
#
|
||||
# Input keep/save net constraints
|
||||
#
|
||||
NET "TRIG0<*" S;
|
||||
NET "TRIG0<*" KEEP;
|
||||
NET "DATA<*" S;
|
||||
NET "DATA<*" KEEP;
|
||||
@@ -0,0 +1,6 @@
|
||||
#
|
||||
# Clock constraints
|
||||
#
|
||||
set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]]
|
||||
set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
|
||||
set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
|
||||
@@ -0,0 +1,31 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="b200_chipscope_ila.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="b200_chipscope_ila.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VEO" xil_pn:name="b200_chipscope_ila.veo" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
|
||||
|
||||
</generated_project>
|
||||
File diff suppressed because one or more lines are too long
@@ -0,0 +1,17 @@
|
||||
#
|
||||
# Clock constraints
|
||||
#
|
||||
NET "CLK" TNM_NET = D_CLK ;
|
||||
INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK;
|
||||
TIMESPEC TS_D2_TO_T2_b200_chipscope_ila = FROM D2_CLK TO "FFS" TIG;
|
||||
TIMESPEC TS_J2_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
|
||||
TIMESPEC TS_J3_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
|
||||
TIMESPEC TS_J4_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG;
|
||||
|
||||
#
|
||||
# Input keep/save net constraints
|
||||
#
|
||||
NET "TRIG0<*" S;
|
||||
NET "TRIG0<*" KEEP;
|
||||
NET "DATA<*" S;
|
||||
NET "DATA<*" KEEP;
|
||||
@@ -0,0 +1,33 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 2013 Xilinx, Inc.
|
||||
// All Rights Reserved
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor : Xilinx
|
||||
// \ \ \/ Version : 14.4
|
||||
// \ \ Application: Xilinx CORE Generator
|
||||
// / / Filename : b200_chipscope_ila.v
|
||||
// /___/ /\ Timestamp : Tue Feb 19 16:52:47 PST 2013
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
// Design Name: Verilog Synthesis Wrapper
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// This wrapper is used to integrate with Project Navigator and PlanAhead
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module b200_chipscope_ila(
|
||||
CONTROL,
|
||||
CLK,
|
||||
DATA,
|
||||
TRIG0) /* synthesis syn_black_box syn_noprune=1 */;
|
||||
|
||||
|
||||
inout [35 : 0] CONTROL;
|
||||
input CLK;
|
||||
input [63 : 0] DATA;
|
||||
input [7 : 0] TRIG0;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,31 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 2013 Xilinx, Inc.
|
||||
// All Rights Reserved
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor : Xilinx
|
||||
// \ \ \/ Version : 14.4
|
||||
// \ \ Application: Xilinx CORE Generator
|
||||
// / / Filename : b200_chipscope_ila.veo
|
||||
// /___/ /\ Timestamp : Tue Feb 19 16:52:47 PST 2013
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
// Design Name: ISE Instantiation template
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
b200_chipscope_ila YourInstanceName (
|
||||
.CONTROL(CONTROL), // INOUT BUS [35:0]
|
||||
.CLK(CLK), // IN
|
||||
.DATA(DATA), // IN BUS [63:0]
|
||||
.TRIG0(TRIG0) // IN BUS [7:0]
|
||||
);
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
@@ -0,0 +1,141 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.4
|
||||
# Date: Wed Feb 20 00:50:54 2013
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = Verilog
|
||||
SET device = xc6slx75
|
||||
SET devicefamily = spartan6
|
||||
SET flowvendor = Foundation_ISE
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = fgg484
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -3
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = false
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET check_bramcount=false
|
||||
CSET component_name=b200_chipscope_ila
|
||||
CSET constraint_type=external
|
||||
CSET counter_width_1=Disabled
|
||||
CSET counter_width_10=Disabled
|
||||
CSET counter_width_11=Disabled
|
||||
CSET counter_width_12=Disabled
|
||||
CSET counter_width_13=Disabled
|
||||
CSET counter_width_14=Disabled
|
||||
CSET counter_width_15=Disabled
|
||||
CSET counter_width_16=Disabled
|
||||
CSET counter_width_2=Disabled
|
||||
CSET counter_width_3=Disabled
|
||||
CSET counter_width_4=Disabled
|
||||
CSET counter_width_5=Disabled
|
||||
CSET counter_width_6=Disabled
|
||||
CSET counter_width_7=Disabled
|
||||
CSET counter_width_8=Disabled
|
||||
CSET counter_width_9=Disabled
|
||||
CSET data_port_width=64
|
||||
CSET data_same_as_trigger=false
|
||||
CSET disable_save_keep=false
|
||||
CSET enable_storage_qualification=true
|
||||
CSET enable_trigger_output_port=false
|
||||
CSET example_design=false
|
||||
CSET exclude_from_data_storage_1=true
|
||||
CSET exclude_from_data_storage_10=true
|
||||
CSET exclude_from_data_storage_11=true
|
||||
CSET exclude_from_data_storage_12=true
|
||||
CSET exclude_from_data_storage_13=true
|
||||
CSET exclude_from_data_storage_14=true
|
||||
CSET exclude_from_data_storage_15=true
|
||||
CSET exclude_from_data_storage_16=true
|
||||
CSET exclude_from_data_storage_2=true
|
||||
CSET exclude_from_data_storage_3=true
|
||||
CSET exclude_from_data_storage_4=true
|
||||
CSET exclude_from_data_storage_5=true
|
||||
CSET exclude_from_data_storage_6=true
|
||||
CSET exclude_from_data_storage_7=true
|
||||
CSET exclude_from_data_storage_8=true
|
||||
CSET exclude_from_data_storage_9=true
|
||||
CSET match_type_1=basic_with_edges
|
||||
CSET match_type_10=basic_with_edges
|
||||
CSET match_type_11=basic_with_edges
|
||||
CSET match_type_12=basic_with_edges
|
||||
CSET match_type_13=basic_with_edges
|
||||
CSET match_type_14=basic_with_edges
|
||||
CSET match_type_15=basic_with_edges
|
||||
CSET match_type_16=basic_with_edges
|
||||
CSET match_type_2=basic_with_edges
|
||||
CSET match_type_3=basic_with_edges
|
||||
CSET match_type_4=basic_with_edges
|
||||
CSET match_type_5=basic_with_edges
|
||||
CSET match_type_6=basic_with_edges
|
||||
CSET match_type_7=basic_with_edges
|
||||
CSET match_type_8=basic_with_edges
|
||||
CSET match_type_9=basic_with_edges
|
||||
CSET match_units_1=1
|
||||
CSET match_units_10=1
|
||||
CSET match_units_11=1
|
||||
CSET match_units_12=1
|
||||
CSET match_units_13=1
|
||||
CSET match_units_14=1
|
||||
CSET match_units_15=1
|
||||
CSET match_units_16=1
|
||||
CSET match_units_2=1
|
||||
CSET match_units_3=1
|
||||
CSET match_units_4=1
|
||||
CSET match_units_5=1
|
||||
CSET match_units_6=1
|
||||
CSET match_units_7=1
|
||||
CSET match_units_8=1
|
||||
CSET match_units_9=1
|
||||
CSET max_sequence_levels=1
|
||||
CSET number_of_trigger_ports=1
|
||||
CSET sample_data_depth=8192
|
||||
CSET sample_on=Rising
|
||||
CSET trigger_port_width_1=8
|
||||
CSET trigger_port_width_10=8
|
||||
CSET trigger_port_width_11=8
|
||||
CSET trigger_port_width_12=8
|
||||
CSET trigger_port_width_13=8
|
||||
CSET trigger_port_width_14=8
|
||||
CSET trigger_port_width_15=8
|
||||
CSET trigger_port_width_16=8
|
||||
CSET trigger_port_width_2=8
|
||||
CSET trigger_port_width_3=8
|
||||
CSET trigger_port_width_4=8
|
||||
CSET trigger_port_width_5=8
|
||||
CSET trigger_port_width_6=8
|
||||
CSET trigger_port_width_7=8
|
||||
CSET trigger_port_width_8=8
|
||||
CSET trigger_port_width_9=8
|
||||
CSET use_rpms=false
|
||||
# END Parameters
|
||||
# BEGIN Extra information
|
||||
MISC pkg_timestamp=2012-12-18T02:47:40Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: 92d75d38
|
||||
@@ -0,0 +1,6 @@
|
||||
#
|
||||
# Clock constraints
|
||||
#
|
||||
set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]]
|
||||
set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
|
||||
set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC]
|
||||
@@ -0,0 +1,73 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="b200_chipscope_ila.ngc" xil_pn:type="FILE_NGC">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="b200_chipscope_ila.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Module|b200_chipscope_ila" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="b200_chipscope_ila.ngc" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/b200_chipscope_ila" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="b200_chipscope_ila" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-02-19T16:52:50" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="1246592F65CAF06BF6A1D464FDE11DBE" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
@@ -0,0 +1,18 @@
|
||||
# Output products list for <b200_chipscope_ila>
|
||||
_xmsgs/pn_parser.xmsgs
|
||||
b200_chipscope_ila.asy
|
||||
b200_chipscope_ila.cdc
|
||||
b200_chipscope_ila.constraints/b200_chipscope_ila.ucf
|
||||
b200_chipscope_ila.constraints/b200_chipscope_ila.xdc
|
||||
b200_chipscope_ila.gise
|
||||
b200_chipscope_ila.ncf
|
||||
b200_chipscope_ila.ngc
|
||||
b200_chipscope_ila.ucf
|
||||
b200_chipscope_ila.v
|
||||
b200_chipscope_ila.veo
|
||||
b200_chipscope_ila.xco
|
||||
b200_chipscope_ila.xdc
|
||||
b200_chipscope_ila.xise
|
||||
b200_chipscope_ila_flist.txt
|
||||
b200_chipscope_ila_readme.txt
|
||||
b200_chipscope_ila_xmdf.tcl
|
||||
@@ -0,0 +1,48 @@
|
||||
The following files were generated for 'b200_chipscope_ila' in directory
|
||||
/home/bhilburn/code/ettus/b200_dev/fpgapriv.git/usrp3/top/b200/coregen/
|
||||
|
||||
XCO file generator:
|
||||
Generate an XCO file for compatibility with legacy flows.
|
||||
|
||||
* b200_chipscope_ila.xco
|
||||
|
||||
Creates an implementation netlist:
|
||||
Creates an implementation netlist for the IP.
|
||||
|
||||
* b200_chipscope_ila.cdc
|
||||
* b200_chipscope_ila.constraints/b200_chipscope_ila.ucf
|
||||
* b200_chipscope_ila.constraints/b200_chipscope_ila.xdc
|
||||
* b200_chipscope_ila.ncf
|
||||
* b200_chipscope_ila.ngc
|
||||
* b200_chipscope_ila.ucf
|
||||
* b200_chipscope_ila.v
|
||||
* b200_chipscope_ila.veo
|
||||
* b200_chipscope_ila.xdc
|
||||
* b200_chipscope_ila_xmdf.tcl
|
||||
|
||||
IP Symbol Generator:
|
||||
Generate an IP symbol based on the current project options'.
|
||||
|
||||
* b200_chipscope_ila.asy
|
||||
|
||||
Generate ISE subproject:
|
||||
Create an ISE subproject for use when including this core in ISE designs
|
||||
|
||||
* _xmsgs/pn_parser.xmsgs
|
||||
* b200_chipscope_ila.gise
|
||||
* b200_chipscope_ila.xise
|
||||
|
||||
Deliver Readme:
|
||||
Readme file for the IP.
|
||||
|
||||
* b200_chipscope_ila_readme.txt
|
||||
|
||||
Generate FLIST file:
|
||||
Text file listing all of the output files produced when a customized core was
|
||||
generated in the CORE Generator.
|
||||
|
||||
* b200_chipscope_ila_flist.txt
|
||||
|
||||
Please see the Xilinx CORE Generator online help for further details on
|
||||
generated files and how to use them.
|
||||
|
||||
Executable
+87
@@ -0,0 +1,87 @@
|
||||
# The package naming convention is <core_name>_xmdf
|
||||
package provide b200_chipscope_ila_xmdf 1.0
|
||||
|
||||
# This includes some utilities that support common XMDF operations
|
||||
package require utilities_xmdf
|
||||
|
||||
# Define a namespace for this package. The name of the name space
|
||||
# is <core_name>_xmdf
|
||||
namespace eval ::b200_chipscope_ila_xmdf {
|
||||
# Use this to define any statics
|
||||
}
|
||||
|
||||
# Function called by client to rebuild the params and port arrays
|
||||
# Optional when the use context does not require the param or ports
|
||||
# arrays to be available.
|
||||
proc ::b200_chipscope_ila_xmdf::xmdfInit { instance } {
|
||||
# Variable containing name of library into which module is compiled
|
||||
# Recommendation: <module_name>
|
||||
# Required
|
||||
utilities_xmdf::xmdfSetData $instance Module Attributes Name b200_chipscope_ila
|
||||
}
|
||||
# ::b200_chipscope_ila_xmdf::xmdfInit
|
||||
|
||||
# Function called by client to fill in all the xmdf* data variables
|
||||
# based on the current settings of the parameters
|
||||
proc ::b200_chipscope_ila_xmdf::xmdfApplyParams { instance } {
|
||||
|
||||
set fcount 0
|
||||
# Array containing libraries that are assumed to exist
|
||||
# Examples include unisim and xilinxcorelib
|
||||
# Optional
|
||||
# In this example, we assume that the unisim library will
|
||||
# be available to the simulation and synthesis tool
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
|
||||
incr fcount
|
||||
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.asy
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.cdc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.constraints/b200_chipscope_ila.ucf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf
|
||||
incr fcount
|
||||
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.ncf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.constraints/b200_chipscope_ila.xdc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.ngc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.veo
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.xco
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila_xmdf.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module b200_chipscope_ila
|
||||
incr fcount
|
||||
|
||||
}
|
||||
|
||||
# ::gen_comp_name_xmdf::xmdfApplyParams
|
||||
|
||||
@@ -0,0 +1,33 @@
|
||||
Version 4
|
||||
SymbolType BLOCK
|
||||
TEXT 32 32 LEFT 4 b200_clk_gen
|
||||
RECTANGLE Normal 32 32 576 1088
|
||||
LINE Normal 0 112 32 112
|
||||
PIN 0 112 LEFT 36
|
||||
PINATTR PinName clk_in1_p
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 144 32 144
|
||||
PIN 0 144 LEFT 36
|
||||
PINATTR PinName clk_in1_n
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 432 32 432
|
||||
PIN 0 432 LEFT 36
|
||||
PINATTR PinName reset
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 608 80 576 80
|
||||
PIN 608 80 RIGHT 36
|
||||
PINATTR PinName clk_out1
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 608 176 576 176
|
||||
PIN 608 176 RIGHT 36
|
||||
PINATTR PinName clk_out2
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 608 272 576 272
|
||||
PIN 608 272 RIGHT 36
|
||||
PINATTR PinName clk_out3
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 608 976 576 976
|
||||
PIN 608 976 RIGHT 36
|
||||
PINATTR PinName locked
|
||||
PINATTR Polarity OUT
|
||||
|
||||
@@ -0,0 +1,31 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="b200_clk_gen.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="b200_clk_gen.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VEO" xil_pn:name="b200_clk_gen.veo" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
|
||||
|
||||
</generated_project>
|
||||
Executable
+72
@@ -0,0 +1,72 @@
|
||||
# file: b200_clk_gen.ucf
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# Input clock periods. These duplicate the values entered for the
|
||||
# input clocks. You can use these to time your system
|
||||
#----------------------------------------------------------------
|
||||
# Differential clock only needs one constraint
|
||||
NET "CLK_IN1_P" TNM_NET = "CLK_IN1_P";
|
||||
TIMESPEC "TS_CLK_IN1_P" = PERIOD "CLK_IN1_P" 25.0 ns HIGH 50% INPUT_JITTER 250.0ps;
|
||||
|
||||
# Derived clock periods. These are commented out because they are
|
||||
# automatically propogated by the tools
|
||||
# However, if you'd like to use them for module level testing, you
|
||||
# can copy them into your module level timing checks
|
||||
#-----------------------------------------------------------------
|
||||
# NET "clk_int[1]" TNM_NET = "CLK_OUT1";
|
||||
# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 40.000 MHz;
|
||||
|
||||
# NET "clk_int[2]" TNM_NET = "CLK_OUT2";
|
||||
# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 100.000 MHz;
|
||||
# NET "clk_int[3]" TNM_NET = "CLK_OUT3";
|
||||
# TIMESPEC "TS_CLK_OUT3" = PERIOD "CLK_OUT3" 100.000 MHz;
|
||||
|
||||
# FALSE PATH constraints
|
||||
PIN "RESET" TIG;
|
||||
|
||||
Executable
+163
@@ -0,0 +1,163 @@
|
||||
// file: b200_clk_gen.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// "Output Output Phase Duty Pk-to-Pk Phase"
|
||||
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
|
||||
//----------------------------------------------------------------------------
|
||||
// CLK_OUT1____40.000______0.000______50.0______200.000____150.000
|
||||
// CLK_OUT2___100.000______0.000______50.0______400.000____150.000
|
||||
// CLK_OUT3___100.000______0.000______50.0______400.000____150.000
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// "Input Clock Freq (MHz) Input Jitter (UI)"
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary__________40.000____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "b200_clk_gen,clk_wiz_v3_6,{component_name=b200_clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=3,clkin1_period=25.0,clkin2_period=25.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
|
||||
module b200_clk_gen
|
||||
(// Clock in ports
|
||||
input CLK_IN1_40_P,
|
||||
input CLK_IN1_40_N,
|
||||
// Clock out ports
|
||||
output CLK_OUT1_40_int,
|
||||
output CLK_OUT2_100_gpif,
|
||||
output CLK_OUT3_100_bus,
|
||||
// Status and control signals
|
||||
input RESET,
|
||||
output LOCKED
|
||||
);
|
||||
|
||||
// Input buffering
|
||||
//------------------------------------
|
||||
IBUFGDS clkin1_buf
|
||||
(.O (clkin1),
|
||||
.I (CLK_IN1_40_P),
|
||||
.IB (CLK_IN1_40_N));
|
||||
|
||||
|
||||
// Clocking primitive
|
||||
//------------------------------------
|
||||
|
||||
// Instantiation of the DCM primitive
|
||||
// * Unused inputs are tied off
|
||||
// * Unused outputs are labeled unused
|
||||
wire psdone_unused;
|
||||
wire locked_int;
|
||||
wire [7:0] status_int;
|
||||
wire clkfb;
|
||||
wire clk0;
|
||||
wire clkfx;
|
||||
|
||||
DCM_SP
|
||||
#(.CLKDV_DIVIDE (2.000),
|
||||
.CLKFX_DIVIDE (2),
|
||||
.CLKFX_MULTIPLY (5),
|
||||
.CLKIN_DIVIDE_BY_2 ("FALSE"),
|
||||
.CLKIN_PERIOD (25.0),
|
||||
.CLKOUT_PHASE_SHIFT ("NONE"),
|
||||
.CLK_FEEDBACK ("1X"),
|
||||
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
|
||||
.PHASE_SHIFT (0),
|
||||
.STARTUP_WAIT ("FALSE"))
|
||||
dcm_sp_inst
|
||||
// Input clock
|
||||
(.CLKIN (clkin1),
|
||||
.CLKFB (clkfb),
|
||||
// Output clocks
|
||||
.CLK0 (clk0),
|
||||
.CLK90 (),
|
||||
.CLK180 (),
|
||||
.CLK270 (),
|
||||
.CLK2X (),
|
||||
.CLK2X180 (),
|
||||
.CLKFX (clkfx),
|
||||
.CLKFX180 (),
|
||||
.CLKDV (),
|
||||
// Ports for dynamic phase shift
|
||||
.PSCLK (1'b0),
|
||||
.PSEN (1'b0),
|
||||
.PSINCDEC (1'b0),
|
||||
.PSDONE (),
|
||||
// Other control and status signals
|
||||
.LOCKED (locked_int),
|
||||
.STATUS (status_int),
|
||||
|
||||
.RST (RESET),
|
||||
// Unused pin- tie low
|
||||
.DSSEN (1'b0));
|
||||
|
||||
assign LOCKED = locked_int;
|
||||
|
||||
// Output buffering
|
||||
//-----------------------------------
|
||||
assign clkfb = CLK_OUT1_40_int;
|
||||
|
||||
BUFG clkout1_buf
|
||||
(.O (CLK_OUT1_40_int),
|
||||
.I (clk0));
|
||||
|
||||
|
||||
BUFG clkout2_buf
|
||||
(.O (CLK_OUT2_100_gpif),
|
||||
.I (clkfx));
|
||||
|
||||
BUFG clkout3_buf
|
||||
(.O (CLK_OUT3_100_bus),
|
||||
.I (clkfx));
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
Executable
+83
@@ -0,0 +1,83 @@
|
||||
//
|
||||
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// "Output Output Phase Duty Pk-to-Pk Phase"
|
||||
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
|
||||
//----------------------------------------------------------------------------
|
||||
// CLK_OUT1____40.000______0.000______50.0______200.000____150.000
|
||||
// CLK_OUT2___100.000______0.000______50.0______400.000____150.000
|
||||
// CLK_OUT3___100.000______0.000______50.0______400.000____150.000
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// "Input Clock Freq (MHz) Input Jitter (UI)"
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary__________40.000____________0.010
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
b200_clk_gen instance_name
|
||||
(// Clock in ports
|
||||
.CLK_IN1_40_P(CLK_IN1_40_P), // IN
|
||||
.CLK_IN1_40_N(CLK_IN1_40_N), // IN
|
||||
// Clock out ports
|
||||
.CLK_OUT1_40_int(CLK_OUT1_40_int), // OUT
|
||||
.CLK_OUT2_100_gpif(CLK_OUT2_100_gpif), // OUT
|
||||
.CLK_OUT3_100_bus(CLK_OUT3_100_bus), // OUT
|
||||
// Status and control signals
|
||||
.RESET(RESET),// IN
|
||||
.LOCKED(LOCKED)); // OUT
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
@@ -0,0 +1,269 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.4
|
||||
# Date: Fri Jan 25 20:00:48 2013
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# Generated from component: xilinx.com:ip:clk_wiz:3.6
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = Verilog
|
||||
SET device = xc6slx75
|
||||
SET devicefamily = spartan6
|
||||
SET flowvendor = Other
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = csg484
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -2
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = false
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET calc_done=DONE
|
||||
CSET clk_in_sel_port=CLK_IN_SEL
|
||||
CSET clk_out1_port=CLK_OUT1_40_int
|
||||
CSET clk_out1_use_fine_ps_gui=false
|
||||
CSET clk_out2_port=CLK_OUT2_100_gpif
|
||||
CSET clk_out2_use_fine_ps_gui=false
|
||||
CSET clk_out3_port=CLK_OUT3_100_bus
|
||||
CSET clk_out3_use_fine_ps_gui=false
|
||||
CSET clk_out4_port=CLK_OUT4
|
||||
CSET clk_out4_use_fine_ps_gui=false
|
||||
CSET clk_out5_port=CLK_OUT5
|
||||
CSET clk_out5_use_fine_ps_gui=false
|
||||
CSET clk_out6_port=CLK_OUT6
|
||||
CSET clk_out6_use_fine_ps_gui=false
|
||||
CSET clk_out7_port=CLK_OUT7
|
||||
CSET clk_out7_use_fine_ps_gui=false
|
||||
CSET clk_valid_port=CLK_VALID
|
||||
CSET clkfb_in_n_port=CLKFB_IN_N
|
||||
CSET clkfb_in_p_port=CLKFB_IN_P
|
||||
CSET clkfb_in_port=CLKFB_IN
|
||||
CSET clkfb_in_signaling=SINGLE
|
||||
CSET clkfb_out_n_port=CLKFB_OUT_N
|
||||
CSET clkfb_out_p_port=CLKFB_OUT_P
|
||||
CSET clkfb_out_port=CLKFB_OUT
|
||||
CSET clkfb_stopped_port=CLKFB_STOPPED
|
||||
CSET clkin1_jitter_ps=250.0
|
||||
CSET clkin1_ui_jitter=0.010
|
||||
CSET clkin2_jitter_ps=100.0
|
||||
CSET clkin2_ui_jitter=0.010
|
||||
CSET clkout1_drives=BUFG
|
||||
CSET clkout1_requested_duty_cycle=50.000
|
||||
CSET clkout1_requested_out_freq=40.000
|
||||
CSET clkout1_requested_phase=0.000
|
||||
CSET clkout2_drives=BUFG
|
||||
CSET clkout2_requested_duty_cycle=50.000
|
||||
CSET clkout2_requested_out_freq=100.000
|
||||
CSET clkout2_requested_phase=0.000
|
||||
CSET clkout2_used=true
|
||||
CSET clkout3_drives=BUFG
|
||||
CSET clkout3_requested_duty_cycle=50.000
|
||||
CSET clkout3_requested_out_freq=100.000
|
||||
CSET clkout3_requested_phase=0.000
|
||||
CSET clkout3_used=true
|
||||
CSET clkout4_drives=BUFG
|
||||
CSET clkout4_requested_duty_cycle=50.000
|
||||
CSET clkout4_requested_out_freq=100.000
|
||||
CSET clkout4_requested_phase=0.000
|
||||
CSET clkout4_used=false
|
||||
CSET clkout5_drives=BUFG
|
||||
CSET clkout5_requested_duty_cycle=50.000
|
||||
CSET clkout5_requested_out_freq=100.000
|
||||
CSET clkout5_requested_phase=0.000
|
||||
CSET clkout5_used=false
|
||||
CSET clkout6_drives=BUFG
|
||||
CSET clkout6_requested_duty_cycle=50.000
|
||||
CSET clkout6_requested_out_freq=100.000
|
||||
CSET clkout6_requested_phase=0.000
|
||||
CSET clkout6_used=false
|
||||
CSET clkout7_drives=BUFG
|
||||
CSET clkout7_requested_duty_cycle=50.000
|
||||
CSET clkout7_requested_out_freq=100.000
|
||||
CSET clkout7_requested_phase=0.000
|
||||
CSET clkout7_used=false
|
||||
CSET clock_mgr_type=AUTO
|
||||
CSET component_name=b200_clk_gen
|
||||
CSET daddr_port=DADDR
|
||||
CSET dclk_port=DCLK
|
||||
CSET dcm_clk_feedback=1X
|
||||
CSET dcm_clk_out1_port=CLK0
|
||||
CSET dcm_clk_out2_port=CLKFX
|
||||
CSET dcm_clk_out3_port=CLKFX
|
||||
CSET dcm_clk_out4_port=CLK0
|
||||
CSET dcm_clk_out5_port=CLK0
|
||||
CSET dcm_clk_out6_port=CLK0
|
||||
CSET dcm_clkdv_divide=2.0
|
||||
CSET dcm_clkfx_divide=2
|
||||
CSET dcm_clkfx_multiply=5
|
||||
CSET dcm_clkgen_clk_out1_port=CLKFX
|
||||
CSET dcm_clkgen_clk_out2_port=CLKFX
|
||||
CSET dcm_clkgen_clk_out3_port=CLKFX
|
||||
CSET dcm_clkgen_clkfx_divide=1
|
||||
CSET dcm_clkgen_clkfx_md_max=0.000
|
||||
CSET dcm_clkgen_clkfx_multiply=4
|
||||
CSET dcm_clkgen_clkfxdv_divide=2
|
||||
CSET dcm_clkgen_clkin_period=10.000
|
||||
CSET dcm_clkgen_notes=None
|
||||
CSET dcm_clkgen_spread_spectrum=NONE
|
||||
CSET dcm_clkgen_startup_wait=false
|
||||
CSET dcm_clkin_divide_by_2=false
|
||||
CSET dcm_clkin_period=25.000
|
||||
CSET dcm_clkout_phase_shift=NONE
|
||||
CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS
|
||||
CSET dcm_notes=None
|
||||
CSET dcm_phase_shift=0
|
||||
CSET dcm_pll_cascade=NONE
|
||||
CSET dcm_startup_wait=false
|
||||
CSET den_port=DEN
|
||||
CSET din_port=DIN
|
||||
CSET dout_port=DOUT
|
||||
CSET drdy_port=DRDY
|
||||
CSET dwe_port=DWE
|
||||
CSET feedback_source=FDBK_AUTO
|
||||
CSET in_freq_units=Units_MHz
|
||||
CSET in_jitter_units=Units_UI
|
||||
CSET input_clk_stopped_port=INPUT_CLK_STOPPED
|
||||
CSET jitter_options=UI
|
||||
CSET jitter_sel=No_Jitter
|
||||
CSET locked_port=LOCKED
|
||||
CSET mmcm_bandwidth=OPTIMIZED
|
||||
CSET mmcm_clkfbout_mult_f=4.000
|
||||
CSET mmcm_clkfbout_phase=0.000
|
||||
CSET mmcm_clkfbout_use_fine_ps=false
|
||||
CSET mmcm_clkin1_period=10.000
|
||||
CSET mmcm_clkin2_period=10.000
|
||||
CSET mmcm_clkout0_divide_f=4.000
|
||||
CSET mmcm_clkout0_duty_cycle=0.500
|
||||
CSET mmcm_clkout0_phase=0.000
|
||||
CSET mmcm_clkout0_use_fine_ps=false
|
||||
CSET mmcm_clkout1_divide=1
|
||||
CSET mmcm_clkout1_duty_cycle=0.500
|
||||
CSET mmcm_clkout1_phase=0.000
|
||||
CSET mmcm_clkout1_use_fine_ps=false
|
||||
CSET mmcm_clkout2_divide=1
|
||||
CSET mmcm_clkout2_duty_cycle=0.500
|
||||
CSET mmcm_clkout2_phase=0.000
|
||||
CSET mmcm_clkout2_use_fine_ps=false
|
||||
CSET mmcm_clkout3_divide=1
|
||||
CSET mmcm_clkout3_duty_cycle=0.500
|
||||
CSET mmcm_clkout3_phase=0.000
|
||||
CSET mmcm_clkout3_use_fine_ps=false
|
||||
CSET mmcm_clkout4_cascade=false
|
||||
CSET mmcm_clkout4_divide=1
|
||||
CSET mmcm_clkout4_duty_cycle=0.500
|
||||
CSET mmcm_clkout4_phase=0.000
|
||||
CSET mmcm_clkout4_use_fine_ps=false
|
||||
CSET mmcm_clkout5_divide=1
|
||||
CSET mmcm_clkout5_duty_cycle=0.500
|
||||
CSET mmcm_clkout5_phase=0.000
|
||||
CSET mmcm_clkout5_use_fine_ps=false
|
||||
CSET mmcm_clkout6_divide=1
|
||||
CSET mmcm_clkout6_duty_cycle=0.500
|
||||
CSET mmcm_clkout6_phase=0.000
|
||||
CSET mmcm_clkout6_use_fine_ps=false
|
||||
CSET mmcm_clock_hold=false
|
||||
CSET mmcm_compensation=ZHOLD
|
||||
CSET mmcm_divclk_divide=1
|
||||
CSET mmcm_notes=None
|
||||
CSET mmcm_ref_jitter1=0.010
|
||||
CSET mmcm_ref_jitter2=0.010
|
||||
CSET mmcm_startup_wait=false
|
||||
CSET num_out_clks=3
|
||||
CSET override_dcm=false
|
||||
CSET override_dcm_clkgen=false
|
||||
CSET override_mmcm=false
|
||||
CSET override_pll=false
|
||||
CSET platform=lin64
|
||||
CSET pll_bandwidth=OPTIMIZED
|
||||
CSET pll_clk_feedback=CLKFBOUT
|
||||
CSET pll_clkfbout_mult=4
|
||||
CSET pll_clkfbout_phase=0.000
|
||||
CSET pll_clkin_period=10.000
|
||||
CSET pll_clkout0_divide=1
|
||||
CSET pll_clkout0_duty_cycle=0.500
|
||||
CSET pll_clkout0_phase=0.000
|
||||
CSET pll_clkout1_divide=1
|
||||
CSET pll_clkout1_duty_cycle=0.500
|
||||
CSET pll_clkout1_phase=0.000
|
||||
CSET pll_clkout2_divide=1
|
||||
CSET pll_clkout2_duty_cycle=0.500
|
||||
CSET pll_clkout2_phase=0.000
|
||||
CSET pll_clkout3_divide=1
|
||||
CSET pll_clkout3_duty_cycle=0.500
|
||||
CSET pll_clkout3_phase=0.000
|
||||
CSET pll_clkout4_divide=1
|
||||
CSET pll_clkout4_duty_cycle=0.500
|
||||
CSET pll_clkout4_phase=0.000
|
||||
CSET pll_clkout5_divide=1
|
||||
CSET pll_clkout5_duty_cycle=0.500
|
||||
CSET pll_clkout5_phase=0.000
|
||||
CSET pll_compensation=SYSTEM_SYNCHRONOUS
|
||||
CSET pll_divclk_divide=1
|
||||
CSET pll_notes=None
|
||||
CSET pll_ref_jitter=0.010
|
||||
CSET power_down_port=POWER_DOWN
|
||||
CSET prim_in_freq=40.000
|
||||
CSET prim_in_jitter=0.010
|
||||
CSET prim_source=Differential_clock_capable_pin
|
||||
CSET primary_port=CLK_IN1_40
|
||||
CSET primitive=MMCM
|
||||
CSET primtype_sel=PLL_BASE
|
||||
CSET psclk_port=PSCLK
|
||||
CSET psdone_port=PSDONE
|
||||
CSET psen_port=PSEN
|
||||
CSET psincdec_port=PSINCDEC
|
||||
CSET relative_inclk=REL_PRIMARY
|
||||
CSET reset_port=RESET
|
||||
CSET secondary_in_freq=100.000
|
||||
CSET secondary_in_jitter=0.010
|
||||
CSET secondary_port=CLK_IN2
|
||||
CSET secondary_source=Single_ended_clock_capable_pin
|
||||
CSET ss_mod_freq=250
|
||||
CSET ss_mode=CENTER_HIGH
|
||||
CSET status_port=STATUS
|
||||
CSET summary_strings=empty
|
||||
CSET use_clk_valid=false
|
||||
CSET use_clkfb_stopped=false
|
||||
CSET use_dyn_phase_shift=false
|
||||
CSET use_dyn_reconfig=false
|
||||
CSET use_freeze=false
|
||||
CSET use_freq_synth=true
|
||||
CSET use_inclk_stopped=false
|
||||
CSET use_inclk_switchover=false
|
||||
CSET use_locked=true
|
||||
CSET use_max_i_jitter=false
|
||||
CSET use_min_o_jitter=false
|
||||
CSET use_min_power=false
|
||||
CSET use_phase_alignment=true
|
||||
CSET use_power_down=false
|
||||
CSET use_reset=true
|
||||
CSET use_spread_spectrum=false
|
||||
CSET use_spread_spectrum_1=false
|
||||
CSET use_status=false
|
||||
# END Parameters
|
||||
# BEGIN Extra information
|
||||
MISC pkg_timestamp=2012-05-10T12:44:55Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: af7323ea
|
||||
Executable
+68
@@ -0,0 +1,68 @@
|
||||
# file: b200_clk_gen.xdc
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# Input clock periods. These duplicate the values entered for the
|
||||
# input clocks. You can use these to time your system
|
||||
#----------------------------------------------------------------
|
||||
# Differential clock only needs one constraint
|
||||
create_clock -name CLK_IN1_P -period 25.0 [get_ports CLK_IN1_P]
|
||||
set_propagated_clock CLK_IN1_P
|
||||
set_input_jitter CLK_IN1_P 0.25
|
||||
|
||||
set_false_path -from [get_ports "RESET"]
|
||||
|
||||
# Derived clock periods. These are commented out because they are
|
||||
# automatically propogated by the tools
|
||||
# However, if you'd like to use them for module level testing, you
|
||||
# can copy them into your module level timing checks
|
||||
#-----------------------------------------------------------------
|
||||
|
||||
#-----------------------------------------------------------------
|
||||
|
||||
#-----------------------------------------------------------------
|
||||
@@ -0,0 +1,408 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="b200_clk_gen/example_design/b200_clk_gen_exdes.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="b200_clk_gen/example_design/b200_clk_gen_exdes.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="b200_clk_gen.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc6slx75" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Module|b200_clk_gen_exdes" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="b200_clk_gen/example_design/b200_clk_gen_exdes.v" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/b200_clk_gen_exdes" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="b200_clk_gen_exdes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="csg484" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="b200_clk_gen_exdes_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="b200_clk_gen_exdes_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="b200_clk_gen_exdes_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="b200_clk_gen_exdes_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="b200_clk_gen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-01-25T12:01:05" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="BF4ABAECC95F189A3B1A35E026FF9799" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
@@ -0,0 +1,181 @@
|
||||
CHANGE LOG for LogiCORE Clocking Wizard V3.6
|
||||
|
||||
Release Date: July 25, 2012
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
|
||||
1. INTRODUCTION
|
||||
2. DEVICE SUPPORT
|
||||
3. NEW FEATURE HISTORY
|
||||
4. RESOLVED ISSUES
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
7. CORE RELEASE HISTORY
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
1. INTRODUCTION
|
||||
|
||||
For installation instructions for this release, please go to:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
|
||||
|
||||
For system requirements:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
|
||||
|
||||
This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
|
||||
solution. For the latest core updates, see the product page at:
|
||||
|
||||
http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
|
||||
|
||||
................................................................................
|
||||
|
||||
2. DEVICE SUPPORT
|
||||
|
||||
|
||||
2.1 ISE
|
||||
|
||||
|
||||
The following device families are supported by the core for this release.
|
||||
|
||||
All 7 Series devices
|
||||
|
||||
|
||||
Zynq-7000 devices
|
||||
Zynq-7000
|
||||
Defense Grade Zynq-7000Q (XQ)
|
||||
|
||||
|
||||
All Virtex-6 devices
|
||||
|
||||
|
||||
All Spartan-6 devices
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
3. NEW FEATURE HISTORY
|
||||
|
||||
|
||||
3.1 ISE
|
||||
|
||||
- Spread Spectrum support for 7 series MMCME2
|
||||
|
||||
- ISE 14.2 software support
|
||||
|
||||
................................................................................
|
||||
|
||||
4. RESOLVED ISSUES
|
||||
|
||||
|
||||
4.1 ISE
|
||||
|
||||
Resolved issue with Virtex6 MMCM instantiation for VHDL project
|
||||
Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
|
||||
|
||||
................................................................................
|
||||
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
|
||||
|
||||
5.1 ISE
|
||||
|
||||
|
||||
The most recent information, including known issues, workarounds, and
|
||||
resolutions for this version is provided in the IP Release Notes Guide
|
||||
located at
|
||||
|
||||
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
|
||||
|
||||
To obtain technical support, create a WebCase at www.xilinx.com/support.
|
||||
Questions are routed to a team with expertise using this product.
|
||||
|
||||
Xilinx provides technical support for use of this product when used
|
||||
according to the guidelines described in the core documentation, and
|
||||
cannot guarantee timing, functionality, or support of this product for
|
||||
designs that do not follow specified guidelines.
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
7. CORE RELEASE HISTORY
|
||||
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support
|
||||
07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support
|
||||
04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
|
||||
01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support
|
||||
06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support
|
||||
03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support
|
||||
12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support
|
||||
09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support
|
||||
07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support
|
||||
04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support
|
||||
12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support
|
||||
09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support
|
||||
06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support
|
||||
04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support
|
||||
================================================================================
|
||||
|
||||
................................................................................
|
||||
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
international copyright and other intellectual property
|
||||
laws.
|
||||
|
||||
DISCLAIMER
|
||||
This disclaimer is not a license and does not grant any
|
||||
rights to the materials distributed herewith. Except as
|
||||
otherwise provided in a valid license issued to you by
|
||||
Xilinx, and to the maximum extent permitted by applicable
|
||||
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
(2) Xilinx shall not be liable (whether in contract or tort,
|
||||
including negligence, or under any other theory of
|
||||
liability) for any loss or damage of any kind or nature
|
||||
related to, arising under or in connection with these
|
||||
materials, including for any direct, or any indirect,
|
||||
special, incidental, or consequential loss or damage
|
||||
(including loss of data, profits, goodwill, or any type of
|
||||
loss or damage suffered as a result of any action brought
|
||||
by a third party) even if such damage or loss was
|
||||
reasonably foreseeable or Xilinx had been advised of the
|
||||
possibility of the same.
|
||||
|
||||
CRITICAL APPLICATIONS
|
||||
Xilinx products are not designed or intended to be fail-
|
||||
safe, or for use in any application requiring fail-safe
|
||||
performance, such as life-support or safety devices or
|
||||
systems, Class III medical devices, nuclear facilities,
|
||||
applications related to the deployment of airbags, or any
|
||||
other applications that could lead to death, personal
|
||||
injury, or severe property or environmental damage
|
||||
(individually and collectively, "Critical
|
||||
Applications"). Customer assumes the sole risk and
|
||||
liability of any use of Xilinx products in Critical
|
||||
Applications, subject only to applicable laws and
|
||||
regulations governing limitations on product liability.
|
||||
|
||||
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
@@ -0,0 +1,181 @@
|
||||
CHANGE LOG for LogiCORE Clocking Wizard V3.6
|
||||
|
||||
Release Date: July 25, 2012
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
|
||||
1. INTRODUCTION
|
||||
2. DEVICE SUPPORT
|
||||
3. NEW FEATURE HISTORY
|
||||
4. RESOLVED ISSUES
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
7. CORE RELEASE HISTORY
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
1. INTRODUCTION
|
||||
|
||||
For installation instructions for this release, please go to:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
|
||||
|
||||
For system requirements:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
|
||||
|
||||
This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
|
||||
solution. For the latest core updates, see the product page at:
|
||||
|
||||
http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
|
||||
|
||||
................................................................................
|
||||
|
||||
2. DEVICE SUPPORT
|
||||
|
||||
|
||||
2.1 ISE
|
||||
|
||||
|
||||
The following device families are supported by the core for this release.
|
||||
|
||||
All 7 Series devices
|
||||
|
||||
|
||||
Zynq-7000 devices
|
||||
Zynq-7000
|
||||
Defense Grade Zynq-7000Q (XQ)
|
||||
|
||||
|
||||
All Virtex-6 devices
|
||||
|
||||
|
||||
All Spartan-6 devices
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
3. NEW FEATURE HISTORY
|
||||
|
||||
|
||||
3.1 ISE
|
||||
|
||||
- Spread Spectrum support for 7 series MMCME2
|
||||
|
||||
- ISE 14.2 software support
|
||||
|
||||
................................................................................
|
||||
|
||||
4. RESOLVED ISSUES
|
||||
|
||||
|
||||
4.1 ISE
|
||||
|
||||
Resolved issue with Virtex6 MMCM instantiation for VHDL project
|
||||
Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
|
||||
|
||||
................................................................................
|
||||
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
|
||||
|
||||
5.1 ISE
|
||||
|
||||
|
||||
The most recent information, including known issues, workarounds, and
|
||||
resolutions for this version is provided in the IP Release Notes Guide
|
||||
located at
|
||||
|
||||
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
|
||||
|
||||
To obtain technical support, create a WebCase at www.xilinx.com/support.
|
||||
Questions are routed to a team with expertise using this product.
|
||||
|
||||
Xilinx provides technical support for use of this product when used
|
||||
according to the guidelines described in the core documentation, and
|
||||
cannot guarantee timing, functionality, or support of this product for
|
||||
designs that do not follow specified guidelines.
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
7. CORE RELEASE HISTORY
|
||||
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support
|
||||
07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support
|
||||
04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
|
||||
01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support
|
||||
06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support
|
||||
03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support
|
||||
12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support
|
||||
09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support
|
||||
07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support
|
||||
04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support
|
||||
12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support
|
||||
09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support
|
||||
06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support
|
||||
04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support
|
||||
================================================================================
|
||||
|
||||
................................................................................
|
||||
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
international copyright and other intellectual property
|
||||
laws.
|
||||
|
||||
DISCLAIMER
|
||||
This disclaimer is not a license and does not grant any
|
||||
rights to the materials distributed herewith. Except as
|
||||
otherwise provided in a valid license issued to you by
|
||||
Xilinx, and to the maximum extent permitted by applicable
|
||||
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
(2) Xilinx shall not be liable (whether in contract or tort,
|
||||
including negligence, or under any other theory of
|
||||
liability) for any loss or damage of any kind or nature
|
||||
related to, arising under or in connection with these
|
||||
materials, including for any direct, or any indirect,
|
||||
special, incidental, or consequential loss or damage
|
||||
(including loss of data, profits, goodwill, or any type of
|
||||
loss or damage suffered as a result of any action brought
|
||||
by a third party) even if such damage or loss was
|
||||
reasonably foreseeable or Xilinx had been advised of the
|
||||
possibility of the same.
|
||||
|
||||
CRITICAL APPLICATIONS
|
||||
Xilinx products are not designed or intended to be fail-
|
||||
safe, or for use in any application requiring fail-safe
|
||||
performance, such as life-support or safety devices or
|
||||
systems, Class III medical devices, nuclear facilities,
|
||||
applications related to the deployment of airbags, or any
|
||||
other applications that could lead to death, personal
|
||||
injury, or severe property or environmental damage
|
||||
(individually and collectively, "Critical
|
||||
Applications"). Customer assumes the sole risk and
|
||||
liability of any use of Xilinx products in Critical
|
||||
Applications, subject only to applicable laws and
|
||||
regulations governing limitations on product liability.
|
||||
|
||||
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
@@ -0,0 +1,192 @@
|
||||
<HTML>
|
||||
<HEAD>
|
||||
<TITLE>clk_wiz_v3_6_vinfo</TITLE>
|
||||
<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
|
||||
</HEAD>
|
||||
<BODY>
|
||||
<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
|
||||
CHANGE LOG for LogiCORE Clocking Wizard V3.6
|
||||
|
||||
Release Date: July 25, 2012
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
|
||||
1. INTRODUCTION
|
||||
2. DEVICE SUPPORT
|
||||
3. NEW FEATURE HISTORY
|
||||
4. RESOLVED ISSUES
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
7. CORE RELEASE HISTORY
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
1. INTRODUCTION
|
||||
|
||||
For installation instructions for this release, please go to:
|
||||
|
||||
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
|
||||
|
||||
For system requirements:
|
||||
|
||||
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
|
||||
|
||||
This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
|
||||
solution. For the latest core updates, see the product page at:
|
||||
|
||||
<A HREF="http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/">www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/</A>
|
||||
|
||||
................................................................................
|
||||
|
||||
2. DEVICE SUPPORT
|
||||
|
||||
|
||||
2.1 ISE
|
||||
|
||||
|
||||
The following device families are supported by the core for this release.
|
||||
|
||||
All 7 Series devices
|
||||
|
||||
|
||||
Zynq-7000 devices
|
||||
Zynq-7000
|
||||
Defense Grade Zynq-7000Q (XQ)
|
||||
|
||||
|
||||
All Virtex-6 devices
|
||||
|
||||
|
||||
All Spartan-6 devices
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
3. NEW FEATURE HISTORY
|
||||
|
||||
|
||||
3.1 ISE
|
||||
|
||||
- Spread Spectrum support for 7 series MMCME2
|
||||
|
||||
- ISE 14.2 software support
|
||||
|
||||
................................................................................
|
||||
|
||||
4. RESOLVED ISSUES
|
||||
|
||||
|
||||
4.1 ISE
|
||||
|
||||
Resolved issue with Virtex6 MMCM instantiation for VHDL project
|
||||
Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
|
||||
|
||||
................................................................................
|
||||
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
|
||||
|
||||
5.1 ISE
|
||||
|
||||
|
||||
The most recent information, including known issues, workarounds, and
|
||||
resolutions for this version is provided in the IP Release Notes Guide
|
||||
located at
|
||||
|
||||
<A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
|
||||
|
||||
To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
|
||||
Questions are routed to a team with expertise using this product.
|
||||
|
||||
Xilinx provides technical support for use of this product when used
|
||||
according to the guidelines described in the core documentation, and
|
||||
cannot guarantee timing, functionality, or support of this product for
|
||||
designs that do not follow specified guidelines.
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
7. CORE RELEASE HISTORY
|
||||
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support
|
||||
07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support
|
||||
04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
|
||||
01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support
|
||||
06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support
|
||||
03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support
|
||||
12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support
|
||||
09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support
|
||||
07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support
|
||||
04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support
|
||||
12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support
|
||||
09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support
|
||||
06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support
|
||||
04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support
|
||||
================================================================================
|
||||
|
||||
................................................................................
|
||||
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
international copyright and other intellectual property
|
||||
laws.
|
||||
|
||||
DISCLAIMER
|
||||
This disclaimer is not a license and does not grant any
|
||||
rights to the materials distributed herewith. Except as
|
||||
otherwise provided in a valid license issued to you by
|
||||
Xilinx, and to the maximum extent permitted by applicable
|
||||
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
(2) Xilinx shall not be liable (whether in contract or tort,
|
||||
including negligence, or under any other theory of
|
||||
liability) for any loss or damage of any kind or nature
|
||||
related to, arising under or in connection with these
|
||||
materials, including for any direct, or any indirect,
|
||||
special, incidental, or consequential loss or damage
|
||||
(including loss of data, profits, goodwill, or any type of
|
||||
loss or damage suffered as a result of any action brought
|
||||
by a third party) even if such damage or loss was
|
||||
reasonably foreseeable or Xilinx had been advised of the
|
||||
possibility of the same.
|
||||
|
||||
CRITICAL APPLICATIONS
|
||||
Xilinx products are not designed or intended to be fail-
|
||||
safe, or for use in any application requiring fail-safe
|
||||
performance, such as life-support or safety devices or
|
||||
systems, Class III medical devices, nuclear facilities,
|
||||
applications related to the deployment of airbags, or any
|
||||
other applications that could lead to death, personal
|
||||
injury, or severe property or environmental damage
|
||||
(individually and collectively, "Critical
|
||||
Applications"). Customer assumes the sole risk and
|
||||
liability of any use of Xilinx products in Critical
|
||||
Applications, subject only to applicable laws and
|
||||
regulations governing limitations on product liability.
|
||||
|
||||
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
</FONT>
|
||||
</PRE>
|
||||
</BODY>
|
||||
</HTML>
|
||||
Binary file not shown.
@@ -0,0 +1,73 @@
|
||||
# file: b200_clk_gen_exdes.ucf
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# Input clock periods. These duplicate the values entered for the
|
||||
# input clocks. You can use these to time your system
|
||||
#----------------------------------------------------------------
|
||||
# Differential clock only needs one constraint
|
||||
NET "CLK_IN1_P" TNM_NET = "CLK_IN1_P";
|
||||
TIMESPEC "TS_CLK_IN1_P" = PERIOD "CLK_IN1_P" 25.0 ns HIGH 50% INPUT_JITTER 250.0ps;
|
||||
|
||||
# Derived clock periods. These are commented out because they are
|
||||
# automatically propogated by the tools
|
||||
# However, if you'd like to use them for module level testing, you
|
||||
# can copy them into your module level timing checks
|
||||
#-----------------------------------------------------------------
|
||||
# NET "clk_int[1]" TNM_NET = "CLK_OUT1";
|
||||
# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 40.000 MHz;
|
||||
|
||||
# NET "clk_int[2]" TNM_NET = "CLK_OUT2";
|
||||
# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 100.000 MHz;
|
||||
# NET "clk_int[3]" TNM_NET = "CLK_OUT3";
|
||||
# TIMESPEC "TS_CLK_OUT3" = PERIOD "CLK_OUT3" 100.000 MHz;
|
||||
|
||||
# FALSE PATH constraints
|
||||
PIN "COUNTER_RESET" TIG;
|
||||
PIN "RESET" TIG;
|
||||
|
||||
@@ -0,0 +1,180 @@
|
||||
// file: b200_clk_gen_exdes.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// Clocking wizard example design
|
||||
//----------------------------------------------------------------------------
|
||||
// This example design instantiates the created clocking network, where each
|
||||
// output clock drives a counter. The high bit of each counter is ported.
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module b200_clk_gen_exdes
|
||||
#(
|
||||
parameter TCQ = 100
|
||||
)
|
||||
(// Clock in ports
|
||||
input CLK_IN1_P,
|
||||
input CLK_IN1_N,
|
||||
// Reset that only drives logic in example design
|
||||
input COUNTER_RESET,
|
||||
output [3:1] CLK_OUT,
|
||||
// High bits of counters driven by clocks
|
||||
output [3:1] COUNT,
|
||||
// Status and control signals
|
||||
input RESET,
|
||||
output LOCKED
|
||||
);
|
||||
|
||||
// Parameters for the counters
|
||||
//-------------------------------
|
||||
// Counter width
|
||||
localparam C_W = 16;
|
||||
// Number of counters
|
||||
localparam NUM_C = 3;
|
||||
genvar count_gen;
|
||||
// When the clock goes out of lock, reset the counters
|
||||
wire reset_int = !LOCKED || RESET || COUNTER_RESET;
|
||||
|
||||
reg [NUM_C:1] rst_sync;
|
||||
reg [NUM_C:1] rst_sync_int;
|
||||
reg [NUM_C:1] rst_sync_int1;
|
||||
reg [NUM_C:1] rst_sync_int2;
|
||||
|
||||
|
||||
// Declare the clocks and counters
|
||||
wire [NUM_C:1] clk_int;
|
||||
wire [NUM_C:1] clk_n;
|
||||
wire [NUM_C:1] clk;
|
||||
reg [C_W-1:0] counter [NUM_C:1];
|
||||
|
||||
// Instantiation of the clocking network
|
||||
//--------------------------------------
|
||||
b200_clk_gen clknetwork
|
||||
(// Clock in ports
|
||||
.CLK_IN1_40_P (CLK_IN1_P),
|
||||
.CLK_IN1_40_N (CLK_IN1_N),
|
||||
// Clock out ports
|
||||
.CLK_OUT1_40_int (clk_int[1]),
|
||||
.CLK_OUT2_100_gpif (clk_int[2]),
|
||||
.CLK_OUT3_100_bus (clk_int[3]),
|
||||
// Status and control signals
|
||||
.RESET (RESET),
|
||||
.LOCKED (LOCKED));
|
||||
|
||||
genvar clk_out_pins;
|
||||
|
||||
generate
|
||||
for (clk_out_pins = 1; clk_out_pins <= NUM_C; clk_out_pins = clk_out_pins + 1)
|
||||
begin: gen_outclk_oddr
|
||||
assign clk_n[clk_out_pins] = ~clk[clk_out_pins];
|
||||
|
||||
ODDR2 clkout_oddr
|
||||
(.Q (CLK_OUT[clk_out_pins1]),
|
||||
.C0 (clk[clk_out_pins]),
|
||||
.C1 (clk_n[clk_out_pins]),
|
||||
.CE (1'b1),
|
||||
.D0 (1'b1),
|
||||
.D1 (1'b0),
|
||||
.R (1'b0),
|
||||
.S (1'b0));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// Connect the output clocks to the design
|
||||
//-----------------------------------------
|
||||
assign clk[1] = clk_int[1];
|
||||
assign clk[2] = clk_int[2];
|
||||
assign clk[3] = clk_int[3];
|
||||
|
||||
|
||||
// Reset synchronizer
|
||||
//-----------------------------------
|
||||
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters_1
|
||||
always @(posedge reset_int or posedge clk[count_gen]) begin
|
||||
if (reset_int) begin
|
||||
rst_sync[count_gen] <= 1'b1;
|
||||
rst_sync_int[count_gen]<= 1'b1;
|
||||
rst_sync_int1[count_gen]<= 1'b1;
|
||||
rst_sync_int2[count_gen]<= 1'b1;
|
||||
end
|
||||
else begin
|
||||
rst_sync[count_gen] <= 1'b0;
|
||||
rst_sync_int[count_gen] <= rst_sync[count_gen];
|
||||
rst_sync_int1[count_gen] <= rst_sync_int[count_gen];
|
||||
rst_sync_int2[count_gen] <= rst_sync_int1[count_gen];
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
// Output clock sampling
|
||||
//-----------------------------------
|
||||
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters
|
||||
|
||||
always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin
|
||||
if (rst_sync_int2[count_gen]) begin
|
||||
counter[count_gen] <= #TCQ { C_W { 1'b 0 } };
|
||||
end else begin
|
||||
counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1;
|
||||
end
|
||||
end
|
||||
// alias the high bit of each counter to the corresponding
|
||||
// bit in the output bus
|
||||
assign COUNT[count_gen] = counter[count_gen][C_W-1];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,70 @@
|
||||
# file: b200_clk_gen_exdes.xdc
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# Input clock periods. These duplicate the values entered for the
|
||||
# input clocks. You can use these to time your system
|
||||
#----------------------------------------------------------------
|
||||
# Differential clock only needs one constraint
|
||||
create_clock -name CLK_IN1_P -period 25.0 [get_ports CLK_IN1_P]
|
||||
set_propagated_clock CLK_IN1_P
|
||||
set_input_jitter CLK_IN1_P 0.25
|
||||
|
||||
# FALSE PATH constraint added on COUNTER_RESET
|
||||
set_false_path -from [get_ports "COUNTER_RESET"]
|
||||
set_false_path -from [get_ports "RESET"]
|
||||
|
||||
# Derived clock periods. These are commented out because they are
|
||||
# automatically propogated by the tools
|
||||
# However, if you'd like to use them for module level testing, you
|
||||
# can copy them into your module level timing checks
|
||||
#-----------------------------------------------------------------
|
||||
|
||||
#-----------------------------------------------------------------
|
||||
|
||||
#-----------------------------------------------------------------
|
||||
+90
@@ -0,0 +1,90 @@
|
||||
REM file: implement.bat
|
||||
REM
|
||||
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
REM
|
||||
REM This file contains confidential and proprietary information
|
||||
REM of Xilinx, Inc. and is protected under U.S. and
|
||||
REM international copyright and other intellectual property
|
||||
REM laws.
|
||||
REM
|
||||
REM DISCLAIMER
|
||||
REM This disclaimer is not a license and does not grant any
|
||||
REM rights to the materials distributed herewith. Except as
|
||||
REM otherwise provided in a valid license issued to you by
|
||||
REM Xilinx, and to the maximum extent permitted by applicable
|
||||
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
REM (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
REM including negligence, or under any other theory of
|
||||
REM liability) for any loss or damage of any kind or nature
|
||||
REM related to, arising under or in connection with these
|
||||
REM materials, including for any direct, or any indirect,
|
||||
REM special, incidental, or consequential loss or damage
|
||||
REM (including loss of data, profits, goodwill, or any type of
|
||||
REM loss or damage suffered as a result of any action brought
|
||||
REM by a third party) even if such damage or loss was
|
||||
REM reasonably foreseeable or Xilinx had been advised of the
|
||||
REM possibility of the same.
|
||||
REM
|
||||
REM CRITICAL APPLICATIONS
|
||||
REM Xilinx products are not designed or intended to be fail-
|
||||
REM safe, or for use in any application requiring fail-safe
|
||||
REM performance, such as life-support or safety devices or
|
||||
REM systems, Class III medical devices, nuclear facilities,
|
||||
REM applications related to the deployment of airbags, or any
|
||||
REM other applications that could lead to death, personal
|
||||
REM injury, or severe property or environmental damage
|
||||
REM (individually and collectively, "Critical
|
||||
REM Applications"). Customer assumes the sole risk and
|
||||
REM liability of any use of Xilinx products in Critical
|
||||
REM Applications, subject only to applicable laws and
|
||||
REM regulations governing limitations on product liability.
|
||||
REM
|
||||
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
REM PART OF THIS FILE AT ALL TIMES.
|
||||
REM
|
||||
|
||||
REM -----------------------------------------------------------------------------
|
||||
REM Script to synthesize and implement the RTL provided for the clocking wizard
|
||||
REM -----------------------------------------------------------------------------
|
||||
|
||||
REM Clean up the results directory
|
||||
rmdir /S /Q results
|
||||
mkdir results
|
||||
|
||||
REM Copy unisim_comp.v file to results directory
|
||||
copy %XILINX%\verilog\src\iSE\unisim_comp.v .\results\
|
||||
|
||||
REM Synthesize the Verilog Wrapper Files
|
||||
echo 'Synthesizing Clocking Wizard design with XST'
|
||||
xst -ifn xst.scr
|
||||
move b200_clk_gen_exdes.ngc results\
|
||||
|
||||
REM Copy the constraints files generated by Coregen
|
||||
echo 'Copying files from constraints directory to results directory'
|
||||
copy ..\example_design\b200_clk_gen_exdes.ucf results\
|
||||
|
||||
cd results
|
||||
|
||||
echo 'Running ngdbuild'
|
||||
ngdbuild -uc b200_clk_gen_exdes.ucf b200_clk_gen_exdes
|
||||
|
||||
echo 'Running map'
|
||||
map -timing -pr b b200_clk_gen_exdes -o mapped.ncd
|
||||
|
||||
echo 'Running par'
|
||||
par -w mapped.ncd routed mapped.pcf
|
||||
|
||||
echo 'Running trce'
|
||||
trce -e 10 routed -o routed mapped.pcf
|
||||
|
||||
echo 'Running design through bitgen'
|
||||
bitgen -w routed
|
||||
|
||||
echo 'Running netgen to create gate level model for the clocking wizard example design'
|
||||
netgen -ofmt verilog -sim -sdf_anno false -tm b200_clk_gen_exdes -w routed.ncd routed.v
|
||||
cd ..
|
||||
|
||||
+91
@@ -0,0 +1,91 @@
|
||||
#!/bin/sh
|
||||
# file: implement.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
#-----------------------------------------------------------------------------
|
||||
# Script to synthesize and implement the RTL provided for the clocking wizard
|
||||
#-----------------------------------------------------------------------------
|
||||
|
||||
# Clean up the results directory
|
||||
rm -rf results
|
||||
mkdir results
|
||||
|
||||
# Copy unisim_comp.v file to results directory
|
||||
cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/
|
||||
|
||||
# Synthesize the Verilog Wrapper Files
|
||||
echo 'Synthesizing Clocking Wizard design with XST'
|
||||
xst -ifn xst.scr
|
||||
mv b200_clk_gen_exdes.ngc results/
|
||||
|
||||
# Copy the constraints files generated by Coregen
|
||||
echo 'Copying files from constraints directory to results directory'
|
||||
cp ../example_design/b200_clk_gen_exdes.ucf results/
|
||||
|
||||
cd results
|
||||
|
||||
echo 'Running ngdbuild'
|
||||
ngdbuild -uc b200_clk_gen_exdes.ucf b200_clk_gen_exdes
|
||||
|
||||
echo 'Running map'
|
||||
map -timing b200_clk_gen_exdes -o mapped.ncd
|
||||
|
||||
echo 'Running par'
|
||||
par -w mapped.ncd routed mapped.pcf
|
||||
|
||||
echo 'Running trce'
|
||||
trce -e 10 routed -o routed mapped.pcf
|
||||
|
||||
echo 'Running design through bitgen'
|
||||
bitgen -w routed
|
||||
|
||||
echo 'Running netgen to create gate level model for the clocking wizard example design'
|
||||
netgen -ofmt verilog -sim -sdf_anno false -tm b200_clk_gen_exdes -w routed.ncd routed.v
|
||||
|
||||
cd ..
|
||||
@@ -0,0 +1,58 @@
|
||||
REM file: planAhead_ise.bat
|
||||
REM
|
||||
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
REM
|
||||
REM This file contains confidential and proprietary information
|
||||
REM of Xilinx, Inc. and is protected under U.S. and
|
||||
REM international copyright and other intellectual property
|
||||
REM laws.
|
||||
REM
|
||||
REM DISCLAIMER
|
||||
REM This disclaimer is not a license and does not grant any
|
||||
REM rights to the materials distributed herewith. Except as
|
||||
REM otherwise provided in a valid license issued to you by
|
||||
REM Xilinx, and to the maximum extent permitted by applicable
|
||||
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
REM (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
REM including negligence, or under any other theory of
|
||||
REM liability) for any loss or damage of any kind or nature
|
||||
REM related to, arising under or in connection with these
|
||||
REM materials, including for any direct, or any indirect,
|
||||
REM special, incidental, or consequential loss or damage
|
||||
REM (including loss of data, profits, goodwill, or any type of
|
||||
REM loss or damage suffered as a result of any action brought
|
||||
REM by a third party) even if such damage or loss was
|
||||
REM reasonably foreseeable or Xilinx had been advised of the
|
||||
REM possibility of the same.
|
||||
REM
|
||||
REM CRITICAL APPLICATIONS
|
||||
REM Xilinx products are not designed or intended to be fail-
|
||||
REM safe, or for use in any application requiring fail-safe
|
||||
REM performance, such as life-support or safety devices or
|
||||
REM systems, Class III medical devices, nuclear facilities,
|
||||
REM applications related to the deployment of airbags, or any
|
||||
REM other applications that could lead to death, personal
|
||||
REM injury, or severe property or environmental damage
|
||||
REM (individually and collectively, "Critical
|
||||
REM Applications"). Customer assumes the sole risk and
|
||||
REM liability of any use of Xilinx products in Critical
|
||||
REM Applications, subject only to applicable laws and
|
||||
REM regulations governing limitations on product liability.
|
||||
REM
|
||||
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
REM PART OF THIS FILE AT ALL TIMES.
|
||||
REM
|
||||
|
||||
REM-----------------------------------------------------------------------------
|
||||
REM Script to synthesize and implement the RTL provided for the clocking wizard
|
||||
REM-----------------------------------------------------------------------------
|
||||
|
||||
del \f results
|
||||
mkdir results
|
||||
cd results
|
||||
|
||||
planAhead -mode batch -source ..\planAhead_ise.tcl
|
||||
@@ -0,0 +1,59 @@
|
||||
#!/bin/sh
|
||||
# file: planAhead_ise.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
#-----------------------------------------------------------------------------
|
||||
# Script to synthesize and implement the RTL provided for the clocking wizard
|
||||
#-----------------------------------------------------------------------------
|
||||
|
||||
rm -rf results
|
||||
mkdir results
|
||||
cd results
|
||||
|
||||
planAhead -mode batch -source ../planAhead_ise.tcl
|
||||
@@ -0,0 +1,78 @@
|
||||
# file: planAhead_ise.tcl
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
set projDir [file dirname [info script]]
|
||||
set projName b200_clk_gen
|
||||
set topName b200_clk_gen_exdes
|
||||
set device xc6slx75csg484-2
|
||||
|
||||
create_project $projName $projDir/results/$projName -part $device
|
||||
|
||||
set_property design_mode RTL [get_filesets sources_1]
|
||||
|
||||
## Source files
|
||||
#set verilogSources [glob $srcDir/*.v]
|
||||
import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/b200_clk_gen_exdes.v
|
||||
import_files -fileset [get_filesets sources_1] -force -norecurse ../../../b200_clk_gen.v
|
||||
|
||||
|
||||
#UCF file
|
||||
import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/b200_clk_gen_exdes.ucf
|
||||
|
||||
set_property top $topName [get_property srcset [current_run]]
|
||||
|
||||
launch_runs -runs synth_1
|
||||
wait_on_run synth_1
|
||||
|
||||
set_property add_step Bitgen [get_runs impl_1]
|
||||
launch_runs -runs impl_1
|
||||
wait_on_run impl_1
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,58 @@
|
||||
REM file: planAhead_rdn.sh
|
||||
REM
|
||||
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
REM
|
||||
REM This file contains confidential and proprietary information
|
||||
REM of Xilinx, Inc. and is protected under U.S. and
|
||||
REM international copyright and other intellectual property
|
||||
REM laws.
|
||||
REM
|
||||
REM DISCLAIMER
|
||||
REM This disclaimer is not a license and does not grant any
|
||||
REM rights to the materials distributed herewith. Except as
|
||||
REM otherwise provided in a valid license issued to you by
|
||||
REM Xilinx, and to the maximum extent permitted by applicable
|
||||
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
REM (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
REM including negligence, or under any other theory of
|
||||
REM liability) for any loss or damage of any kind or nature
|
||||
REM related to, arising under or in connection with these
|
||||
REM materials, including for any direct, or any indirect,
|
||||
REM special, incidental, or consequential loss or damage
|
||||
REM (including loss of data, profits, goodwill, or any type of
|
||||
REM loss or damage suffered as a result of any action brought
|
||||
REM by a third party) even if such damage or loss was
|
||||
REM reasonably foreseeable or Xilinx had been advised of the
|
||||
REM possibility of the same.
|
||||
REM
|
||||
REM CRITICAL APPLICATIONS
|
||||
REM Xilinx products are not designed or intended to be fail-
|
||||
REM safe, or for use in any application requiring fail-safe
|
||||
REM performance, such as life-support or safety devices or
|
||||
REM systems, Class III medical devices, nuclear facilities,
|
||||
REM applications related to the deployment of airbags, or any
|
||||
REM other applications that could lead to death, personal
|
||||
REM injury, or severe property or environmental damage
|
||||
REM (individually and collectively, "Critical
|
||||
REM Applications"). Customer assumes the sole risk and
|
||||
REM liability of any use of Xilinx products in Critical
|
||||
REM Applications, subject only to applicable laws and
|
||||
REM regulations governing limitations on product liability.
|
||||
REM
|
||||
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
REM PART OF THIS FILE AT ALL TIMES.
|
||||
REM
|
||||
|
||||
REM-----------------------------------------------------------------------------
|
||||
REM Script to synthesize and implement the RTL provided for the XADC wizard
|
||||
REM-----------------------------------------------------------------------------
|
||||
|
||||
del \f results
|
||||
mkdir results
|
||||
cd results
|
||||
|
||||
planAhead -mode batch -source ..\planAhead_rdn.tcl
|
||||
@@ -0,0 +1,57 @@
|
||||
#!/bin/sh
|
||||
# file: planAhead_rdn.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
#-----------------------------------------------------------------------------
|
||||
# Script to synthesize and implement the RTL provided for the XADC wizard
|
||||
#-----------------------------------------------------------------------------
|
||||
rm -rf results
|
||||
mkdir results
|
||||
cd results
|
||||
planAhead -mode batch -source ../planAhead_rdn.tcl
|
||||
@@ -0,0 +1,69 @@
|
||||
# file : planAhead_rdn.tcl
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
set device xc6slx75csg484-2
|
||||
set projName b200_clk_gen
|
||||
set design b200_clk_gen
|
||||
set projDir [file dirname [info script]]
|
||||
create_project $projName $projDir/results/$projName -part $device -force
|
||||
set_property design_mode RTL [current_fileset -srcset]
|
||||
set top_module b200_clk_gen_exdes
|
||||
set_property top b200_clk_gen_exdes [get_property srcset [current_run]]
|
||||
add_files -norecurse {../../../b200_clk_gen.v}
|
||||
add_files -norecurse {../../example_design/b200_clk_gen_exdes.v}
|
||||
import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/b200_clk_gen_exdes.xdc}
|
||||
synth_design
|
||||
opt_design
|
||||
place_design
|
||||
route_design
|
||||
write_sdf -rename_top_module b200_clk_gen_exdes -file routed.sdf
|
||||
write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module b200_clk_gen_exdes -file routed.v
|
||||
report_timing -nworst 30 -path_type full -file routed.twr
|
||||
report_drc -file report.drc
|
||||
write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit
|
||||
+2
@@ -0,0 +1,2 @@
|
||||
verilog work ../../b200_clk_gen.v
|
||||
verilog work ../example_design/b200_clk_gen_exdes.v
|
||||
+9
@@ -0,0 +1,9 @@
|
||||
run
|
||||
-ifmt MIXED
|
||||
-top b200_clk_gen_exdes
|
||||
-p xc6slx75-csg484-2
|
||||
-ifn xst.prj
|
||||
-ofn b200_clk_gen_exdes
|
||||
-keep_hierarchy soft
|
||||
-equivalent_register_removal no
|
||||
-max_fanout 65535
|
||||
+146
@@ -0,0 +1,146 @@
|
||||
// file: b200_clk_gen_tb.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// Clocking wizard demonstration testbench
|
||||
//----------------------------------------------------------------------------
|
||||
// This demonstration testbench instantiates the example design for the
|
||||
// clocking wizard. Input clocks are toggled, which cause the clocking
|
||||
// network to lock and the counters to increment.
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
`define wait_lock @(posedge LOCKED)
|
||||
|
||||
module b200_clk_gen_tb ();
|
||||
|
||||
// Clock to Q delay of 100ps
|
||||
localparam TCQ = 100;
|
||||
|
||||
|
||||
// timescale is 1ps/1ps
|
||||
localparam ONE_NS = 1000;
|
||||
localparam PHASE_ERR_MARGIN = 100; // 100ps
|
||||
// how many cycles to run
|
||||
localparam COUNT_PHASE = 1024;
|
||||
// we'll be using the period in many locations
|
||||
localparam time PER1 = 25.0*ONE_NS;
|
||||
localparam time PER1_1 = PER1/2;
|
||||
localparam time PER1_2 = PER1 - PER1/2;
|
||||
|
||||
// Declare the input clock signals
|
||||
reg CLK_IN1 = 1;
|
||||
wire CLK_IN1_P = CLK_IN1;
|
||||
wire CLK_IN1_N = ~CLK_IN1;
|
||||
|
||||
// The high bits of the sampling counters
|
||||
wire [3:1] COUNT;
|
||||
// Status and control signals
|
||||
reg RESET = 0;
|
||||
wire LOCKED;
|
||||
reg COUNTER_RESET = 0;
|
||||
wire [3:1] CLK_OUT;
|
||||
//Freq Check using the M & D values setting and actual Frequency generated
|
||||
|
||||
|
||||
// Input clock generation
|
||||
//------------------------------------
|
||||
always begin
|
||||
CLK_IN1 = #PER1_1 ~CLK_IN1;
|
||||
CLK_IN1 = #PER1_2 ~CLK_IN1;
|
||||
end
|
||||
|
||||
// Test sequence
|
||||
reg [15*8-1:0] test_phase = "";
|
||||
initial begin
|
||||
// Set up any display statements using time to be readable
|
||||
$timeformat(-12, 2, "ps", 10);
|
||||
COUNTER_RESET = 0;
|
||||
test_phase = "reset";
|
||||
RESET = 1;
|
||||
#(PER1*6);
|
||||
RESET = 0;
|
||||
test_phase = "wait lock";
|
||||
`wait_lock;
|
||||
#(PER1*6);
|
||||
COUNTER_RESET = 1;
|
||||
#(PER1*20)
|
||||
COUNTER_RESET = 0;
|
||||
|
||||
test_phase = "counting";
|
||||
#(PER1*COUNT_PHASE);
|
||||
|
||||
$display("SIMULATION PASSED");
|
||||
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
|
||||
$finish;
|
||||
end
|
||||
|
||||
// Instantiation of the example design containing the clock
|
||||
// network and sampling counters
|
||||
//---------------------------------------------------------
|
||||
b200_clk_gen_exdes
|
||||
#(
|
||||
.TCQ (TCQ)
|
||||
) dut
|
||||
(// Clock in ports
|
||||
.CLK_IN1_P (CLK_IN1_P),
|
||||
.CLK_IN1_N (CLK_IN1_N),
|
||||
// Reset for logic in example design
|
||||
.COUNTER_RESET (COUNTER_RESET),
|
||||
.CLK_OUT (CLK_OUT),
|
||||
// High bits of the counters
|
||||
.COUNT (COUNT),
|
||||
// Status and control signals
|
||||
.RESET (RESET),
|
||||
.LOCKED (LOCKED));
|
||||
|
||||
// Freq Check
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,8 @@
|
||||
# file: simcmds.tcl
|
||||
|
||||
# create the simulation script
|
||||
vcd dumpfile isim.vcd
|
||||
vcd dumpvars -m /b200_clk_gen_tb -l 0
|
||||
wave add /
|
||||
run 50000ns
|
||||
quit
|
||||
@@ -0,0 +1,59 @@
|
||||
REM file: simulate_isim.bat
|
||||
REM
|
||||
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
REM
|
||||
REM This file contains confidential and proprietary information
|
||||
REM of Xilinx, Inc. and is protected under U.S. and
|
||||
REM international copyright and other intellectual property
|
||||
REM laws.
|
||||
REM
|
||||
REM DISCLAIMER
|
||||
REM This disclaimer is not a license and does not grant any
|
||||
REM rights to the materials distributed herewith. Except as
|
||||
REM otherwise provided in a valid license issued to you by
|
||||
REM Xilinx, and to the maximum extent permitted by applicable
|
||||
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
REM (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
REM including negligence, or under any other theory of
|
||||
REM liability) for any loss or damage of any kind or nature
|
||||
REM related to, arising under or in connection with these
|
||||
REM materials, including for any direct, or any indirect,
|
||||
REM special, incidental, or consequential loss or damage
|
||||
REM (including loss of data, profits, goodwill, or any type of
|
||||
REM loss or damage suffered as a result of any action brought
|
||||
REM by a third party) even if such damage or loss was
|
||||
REM reasonably foreseeable or Xilinx had been advised of the
|
||||
REM possibility of the same.
|
||||
REM
|
||||
REM CRITICAL APPLICATIONS
|
||||
REM Xilinx products are not designed or intended to be fail-
|
||||
REM safe, or for use in any application requiring fail-safe
|
||||
REM performance, such as life-support or safety devices or
|
||||
REM systems, Class III medical devices, nuclear facilities,
|
||||
REM applications related to the deployment of airbags, or any
|
||||
REM other applications that could lead to death, personal
|
||||
REM injury, or severe property or environmental damage
|
||||
REM (individually and collectively, "Critical
|
||||
REM Applications"). Customer assumes the sole risk and
|
||||
REM liability of any use of Xilinx products in Critical
|
||||
REM Applications, subject only to applicable laws and
|
||||
REM regulations governing limitations on product liability.
|
||||
REM
|
||||
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
REM PART OF THIS FILE AT ALL TIMES.
|
||||
REM
|
||||
|
||||
vlogcomp -work work %XILINX%\verilog\src\glbl.v
|
||||
vlogcomp -work work ..\..\..\b200_clk_gen.v
|
||||
vlogcomp -work work ..\..\example_design\b200_clk_gen_exdes.v
|
||||
vlogcomp -work work ..\b200_clk_gen_tb.v
|
||||
|
||||
REM compile the project
|
||||
fuse work.b200_clk_gen_tb work.glbl -L unisims_ver -o b200_clk_gen_isim.exe
|
||||
|
||||
REM run the simulation script
|
||||
.\b200_clk_gen_isim.exe -gui -tclbatch simcmds.tcl
|
||||
@@ -0,0 +1,61 @@
|
||||
# file: simulate_isim.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# lin64
|
||||
# create the project
|
||||
vlogcomp -work work ${XILINX}/verilog/src/glbl.v
|
||||
vlogcomp -work work ../../../b200_clk_gen.v
|
||||
vlogcomp -work work ../../example_design/b200_clk_gen_exdes.v
|
||||
vlogcomp -work work ../b200_clk_gen_tb.v
|
||||
|
||||
# compile the project
|
||||
fuse work.b200_clk_gen_tb work.glbl -L unisims_ver -o b200_clk_gen_isim.exe
|
||||
|
||||
# run the simulation script
|
||||
./b200_clk_gen_isim.exe -gui -tclbatch simcmds.tcl
|
||||
@@ -0,0 +1,61 @@
|
||||
REM file: simulate_mti.bat
|
||||
REM
|
||||
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
REM
|
||||
REM This file contains confidential and proprietary information
|
||||
REM of Xilinx, Inc. and is protected under U.S. and
|
||||
REM international copyright and other intellectual property
|
||||
REM laws.
|
||||
REM
|
||||
REM DISCLAIMER
|
||||
REM This disclaimer is not a license and does not grant any
|
||||
REM rights to the materials distributed herewith. Except as
|
||||
REM otherwise provided in a valid license issued to you by
|
||||
REM Xilinx, and to the maximum extent permitted by applicable
|
||||
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
REM (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
REM including negligence, or under any other theory of
|
||||
REM liability) for any loss or damage of any kind or nature
|
||||
REM related to, arising under or in connection with these
|
||||
REM materials, including for any direct, or any indirect,
|
||||
REM special, incidental, or consequential loss or damage
|
||||
REM (including loss of data, profits, goodwill, or any type of
|
||||
REM loss or damage suffered as a result of any action brought
|
||||
REM by a third party) even if such damage or loss was
|
||||
REM reasonably foreseeable or Xilinx had been advised of the
|
||||
REM possibility of the same.
|
||||
REM
|
||||
REM CRITICAL APPLICATIONS
|
||||
REM Xilinx products are not designed or intended to be fail-
|
||||
REM safe, or for use in any application requiring fail-safe
|
||||
REM performance, such as life-support or safety devices or
|
||||
REM systems, Class III medical devices, nuclear facilities,
|
||||
REM applications related to the deployment of airbags, or any
|
||||
REM other applications that could lead to death, personal
|
||||
REM injury, or severe property or environmental damage
|
||||
REM (individually and collectively, "Critical
|
||||
REM Applications"). Customer assumes the sole risk and
|
||||
REM liability of any use of Xilinx products in Critical
|
||||
REM Applications, subject only to applicable laws and
|
||||
REM regulations governing limitations on product liability.
|
||||
REM
|
||||
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
REM PART OF THIS FILE AT ALL TIMES.
|
||||
REM
|
||||
|
||||
REM set up the working directory
|
||||
vlib work
|
||||
|
||||
REM compile all of the files
|
||||
vlog -work work %XILINX%\verilog\src\glbl.v
|
||||
vlog -work work ..\..\..\b200_clk_gen.v
|
||||
vlog -work work ..\..\example_design\b200_clk_gen_exdes.v
|
||||
vlog -work work ..\b200_clk_gen_tb.v
|
||||
|
||||
REM run the simulation
|
||||
vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.b200_clk_gen_tb work.glbl
|
||||
|
||||
@@ -0,0 +1,65 @@
|
||||
# file: simulate_mti.do
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# set up the working directory
|
||||
set work work
|
||||
vlib work
|
||||
|
||||
# compile all of the files
|
||||
vlog -work work $env(XILINX)/verilog/src/glbl.v
|
||||
vlog -work work ../../../b200_clk_gen.v
|
||||
vlog -work work ../../example_design/b200_clk_gen_exdes.v
|
||||
vlog -work work ../b200_clk_gen_tb.v
|
||||
|
||||
# run the simulation
|
||||
vsim -t ps -voptargs="+acc" -L unisims_ver work.b200_clk_gen_tb work.glbl
|
||||
do wave.do
|
||||
log b200_clk_gen_tb/dut/counter
|
||||
log -r /*
|
||||
run 50000ns
|
||||
@@ -0,0 +1,61 @@
|
||||
#/bin/sh
|
||||
# file: simulate_mti.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# set up the working directory
|
||||
set work work
|
||||
vlib work
|
||||
|
||||
# compile all of the files
|
||||
vlog -work work $XILINX/verilog/src/glbl.v
|
||||
vlog -work work ../../../b200_clk_gen.v
|
||||
vlog -work work ../../example_design/b200_clk_gen_exdes.v
|
||||
vlog -work work ../b200_clk_gen_tb.v
|
||||
|
||||
# run the simulation
|
||||
vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.b200_clk_gen_tb work.glbl
|
||||
@@ -0,0 +1,62 @@
|
||||
#/bin/sh
|
||||
# file: simulate_ncsim.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# set up the working directory
|
||||
mkdir work
|
||||
|
||||
# compile all of the files
|
||||
ncvlog -work work ${XILINX}/verilog/src/glbl.v
|
||||
ncvlog -work work ../../../b200_clk_gen.v
|
||||
ncvlog -work work ../../example_design/b200_clk_gen_exdes.v
|
||||
ncvlog -work work ../b200_clk_gen_tb.v
|
||||
|
||||
# elaborate and run the simulation
|
||||
ncelab -work work -access +wc work.b200_clk_gen_tb work.glbl
|
||||
ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.b200_clk_gen_tb
|
||||
@@ -0,0 +1,72 @@
|
||||
#!/bin/sh
|
||||
# file: simulate_vcs.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# remove old files
|
||||
rm -rf simv* csrc DVEfiles AN.DB
|
||||
|
||||
# compile all of the files
|
||||
# Note that -sverilog is not strictly required- You can
|
||||
# remove the -sverilog if you change the type of the
|
||||
# localparam for the periods in the testbench file to
|
||||
# [63:0] from time
|
||||
vlogan -sverilog \
|
||||
${XILINX}/verilog/src/glbl.v \
|
||||
../../../b200_clk_gen.v \
|
||||
../../example_design/b200_clk_gen_exdes.v \
|
||||
../b200_clk_gen_tb.v
|
||||
|
||||
# prepare the simulation
|
||||
vcs +vcs+lic+wait -debug b200_clk_gen_tb glbl
|
||||
|
||||
# run the simulation
|
||||
./simv -ucli -i ucli_commands.key
|
||||
|
||||
# launch the viewer
|
||||
dve -vpd vcdplus.vpd -session vcs_session.tcl
|
||||
@@ -0,0 +1,5 @@
|
||||
call {$vcdpluson}
|
||||
call {$vcdplusmemon(b200_clk_gen_tb.dut.counter)}
|
||||
run
|
||||
call {$vcdplusclose}
|
||||
quit
|
||||
@@ -0,0 +1,18 @@
|
||||
gui_open_window Wave
|
||||
gui_sg_create b200_clk_gen_group
|
||||
gui_list_add_group -id Wave.1 {b200_clk_gen_group}
|
||||
gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.test_phase}
|
||||
gui_set_radix -radix {ascii} -signals {b200_clk_gen_tb.test_phase}
|
||||
gui_sg_addsignal -group b200_clk_gen_group {{Input_clocks}} -divider
|
||||
gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.CLK_IN1}
|
||||
gui_sg_addsignal -group b200_clk_gen_group {{Output_clocks}} -divider
|
||||
gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.dut.clk}
|
||||
gui_list_expand -id Wave.1 b200_clk_gen_tb.dut.clk
|
||||
gui_sg_addsignal -group b200_clk_gen_group {{Status_control}} -divider
|
||||
gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.RESET}
|
||||
gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.LOCKED}
|
||||
gui_sg_addsignal -group b200_clk_gen_group {{Counters}} -divider
|
||||
gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.COUNT}
|
||||
gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.dut.counter}
|
||||
gui_list_expand -id Wave.1 b200_clk_gen_tb.dut.counter
|
||||
gui_zoom -window Wave.1 -full
|
||||
@@ -0,0 +1,60 @@
|
||||
# file: wave.do
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
add wave -noupdate -format Literal -radix ascii /b200_clk_gen_tb/test_phase
|
||||
add wave -noupdate -divider {Input clocks}
|
||||
add wave -noupdate -format Logic /b200_clk_gen_tb/CLK_IN1
|
||||
add wave -noupdate -divider {Output clocks}
|
||||
add wave -noupdate -format Literal -expand /b200_clk_gen_tb/dut/clk
|
||||
add wave -noupdate -divider Status/control
|
||||
add wave -noupdate -format Logic /b200_clk_gen_tb/RESET
|
||||
add wave -noupdate -format Logic /b200_clk_gen_tb/LOCKED
|
||||
add wave -noupdate -divider Counters
|
||||
add wave -noupdate -format Literal -radix hexadecimal /b200_clk_gen_tb/COUNT
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /b200_clk_gen_tb/dut/counter
|
||||
+119
@@ -0,0 +1,119 @@
|
||||
# file: wave.sv
|
||||
#
|
||||
# (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# Get the windows set up
|
||||
#
|
||||
if {[catch {window new WatchList -name "Design Browser 1" -geometry 1054x819+536+322}] != ""} {
|
||||
window geometry "Design Browser 1" 1054x819+536+322
|
||||
}
|
||||
window target "Design Browser 1" on
|
||||
browser using {Design Browser 1}
|
||||
browser set \
|
||||
-scope nc::b200_clk_gen_tb
|
||||
browser yview see nc::b200_clk_gen_tb
|
||||
browser timecontrol set -lock 0
|
||||
|
||||
if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1010x600+0+541}] != ""} {
|
||||
window geometry "Waveform 1" 1010x600+0+541
|
||||
}
|
||||
window target "Waveform 1" on
|
||||
waveform using {Waveform 1}
|
||||
waveform sidebar visibility partial
|
||||
waveform set \
|
||||
-primarycursor TimeA \
|
||||
-signalnames name \
|
||||
-signalwidth 175 \
|
||||
-units ns \
|
||||
-valuewidth 75
|
||||
cursor set -using TimeA -time 0
|
||||
waveform baseline set -time 0
|
||||
waveform xview limits 0 20000n
|
||||
|
||||
#
|
||||
# Define signal groups
|
||||
#
|
||||
catch {group new -name {Output clocks} -overlay 0}
|
||||
catch {group new -name {Status/control} -overlay 0}
|
||||
catch {group new -name {Counters} -overlay 0}
|
||||
|
||||
set id [waveform add -signals [list {nc::b200_clk_gen_tb.CLK_IN1}]]
|
||||
|
||||
group using {Output clocks}
|
||||
group set -overlay 0
|
||||
group set -comment {}
|
||||
group clear 0 end
|
||||
|
||||
group insert \
|
||||
{b200_clk_gen_tb.dut.clk[1]} \
|
||||
{b200_clk_gen_tb.dut.clk[2]} \ {b200_clk_gen_tb.dut.clk[3]}
|
||||
group using {Counters}
|
||||
group set -overlay 0
|
||||
group set -comment {}
|
||||
group clear 0 end
|
||||
|
||||
group insert \
|
||||
{b200_clk_gen_tb.dut.counter[1]} \
|
||||
{b200_clk_gen_tb.dut.counter[2]} \ {b200_clk_gen_tb.dut.counter[3]}
|
||||
group using {Status/control}
|
||||
group set -overlay 0
|
||||
group set -comment {}
|
||||
group clear 0 end
|
||||
|
||||
group insert \
|
||||
{nc::b200_clk_gen_tb.RESET} {nc::b200_clk_gen_tb.LOCKED}
|
||||
|
||||
|
||||
set id [waveform add -signals [list {nc::b200_clk_gen_tb.COUNT} ]]
|
||||
|
||||
set id [waveform add -signals [list {nc::b200_clk_gen_tb.test_phase} ]]
|
||||
waveform format $id -radix %a
|
||||
|
||||
set groupId [waveform add -groups {{Input clocks}}]
|
||||
set groupId [waveform add -groups {{Output clocks}}]
|
||||
set groupId [waveform add -groups {{Status/control}}]
|
||||
set groupId [waveform add -groups {{Counters}}]
|
||||
@@ -0,0 +1,160 @@
|
||||
// file: b200_clk_gen_tb.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// Clocking wizard demonstration testbench
|
||||
//----------------------------------------------------------------------------
|
||||
// This demonstration testbench instantiates the example design for the
|
||||
// clocking wizard. Input clocks are toggled, which cause the clocking
|
||||
// network to lock and the counters to increment.
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
`define wait_lock @(posedge LOCKED)
|
||||
|
||||
module b200_clk_gen_tb ();
|
||||
|
||||
// Clock to Q delay of 100ps
|
||||
localparam TCQ = 100;
|
||||
|
||||
|
||||
// timescale is 1ps/1ps
|
||||
localparam ONE_NS = 1000;
|
||||
localparam PHASE_ERR_MARGIN = 100; // 100ps
|
||||
// how many cycles to run
|
||||
localparam COUNT_PHASE = 1024;
|
||||
// we'll be using the period in many locations
|
||||
localparam time PER1 = 25.0*ONE_NS;
|
||||
localparam time PER1_1 = PER1/2;
|
||||
localparam time PER1_2 = PER1 - PER1/2;
|
||||
|
||||
// Declare the input clock signals
|
||||
reg CLK_IN1 = 1;
|
||||
wire CLK_IN1_P = CLK_IN1;
|
||||
wire CLK_IN1_N = ~CLK_IN1;
|
||||
|
||||
// The high bits of the sampling counters
|
||||
wire [3:1] COUNT;
|
||||
// Status and control signals
|
||||
reg RESET = 0;
|
||||
wire LOCKED;
|
||||
reg COUNTER_RESET = 0;
|
||||
wire [3:1] CLK_OUT;
|
||||
//Freq Check using the M & D values setting and actual Frequency generated
|
||||
|
||||
reg [13:0] timeout_counter = 14'b00000000000000;
|
||||
|
||||
// Input clock generation
|
||||
//------------------------------------
|
||||
always begin
|
||||
CLK_IN1 = #PER1_1 ~CLK_IN1;
|
||||
CLK_IN1 = #PER1_2 ~CLK_IN1;
|
||||
end
|
||||
|
||||
// Test sequence
|
||||
reg [15*8-1:0] test_phase = "";
|
||||
initial begin
|
||||
// Set up any display statements using time to be readable
|
||||
$timeformat(-12, 2, "ps", 10);
|
||||
$display ("Timing checks are not valid");
|
||||
COUNTER_RESET = 0;
|
||||
test_phase = "reset";
|
||||
RESET = 1;
|
||||
#(PER1*6);
|
||||
RESET = 0;
|
||||
test_phase = "wait lock";
|
||||
`wait_lock;
|
||||
#(PER1*6);
|
||||
COUNTER_RESET = 1;
|
||||
#(PER1*19.5)
|
||||
COUNTER_RESET = 0;
|
||||
#(PER1*1)
|
||||
$display ("Timing checks are valid");
|
||||
test_phase = "counting";
|
||||
#(PER1*COUNT_PHASE);
|
||||
|
||||
$display("SIMULATION PASSED");
|
||||
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
|
||||
$finish;
|
||||
end
|
||||
|
||||
|
||||
always@(posedge CLK_IN1) begin
|
||||
timeout_counter <= timeout_counter + 1'b1;
|
||||
if (timeout_counter == 14'b10000000000000) begin
|
||||
if (LOCKED != 1'b1) begin
|
||||
$display("ERROR : NO LOCK signal");
|
||||
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Instantiation of the example design containing the clock
|
||||
// network and sampling counters
|
||||
//---------------------------------------------------------
|
||||
b200_clk_gen_exdes
|
||||
dut
|
||||
(// Clock in ports
|
||||
.CLK_IN1_P (CLK_IN1_P),
|
||||
.CLK_IN1_N (CLK_IN1_N),
|
||||
// Reset for logic in example design
|
||||
.COUNTER_RESET (COUNTER_RESET),
|
||||
.CLK_OUT (CLK_OUT),
|
||||
// High bits of the counters
|
||||
.COUNT (COUNT),
|
||||
// Status and control signals
|
||||
.RESET (RESET),
|
||||
.LOCKED (LOCKED));
|
||||
|
||||
|
||||
// Freq Check
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,2 @@
|
||||
COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X",
|
||||
SCOPE = b200_clk_gen_tb.dut;
|
||||
@@ -0,0 +1,9 @@
|
||||
# file: simcmds.tcl
|
||||
|
||||
# create the simulation script
|
||||
vcd dumpfile isim.vcd
|
||||
vcd dumpvars -m /b200_clk_gen_tb -l 0
|
||||
wave add /
|
||||
run 50000ns
|
||||
quit
|
||||
|
||||
@@ -0,0 +1,62 @@
|
||||
# file: simulate_isim.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# create the project
|
||||
vlogcomp -work work ${XILINX}/verilog/src/glbl.v
|
||||
vlogcomp -work work ../../implement/results/routed.v
|
||||
vlogcomp -work work b200_clk_gen_tb.v
|
||||
|
||||
# compile the project
|
||||
fuse work.b200_clk_gen_tb work.glbl -L secureip -L simprims_ver -o b200_clk_gen_isim.exe
|
||||
|
||||
# run the simulation script
|
||||
./b200_clk_gen_isim.exe -tclbatch simcmds.tcl -sdfmax /b200_clk_gen_tb/dut=../../implement/results/routed.sdf
|
||||
|
||||
# run the simulation script
|
||||
#./b200_clk_gen_isim.exe -gui -tclbatch simcmds.tcl
|
||||
@@ -0,0 +1,59 @@
|
||||
REM file: simulate_mti.bat
|
||||
REM
|
||||
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
REM
|
||||
REM This file contains confidential and proprietary information
|
||||
REM of Xilinx, Inc. and is protected under U.S. and
|
||||
REM international copyright and other intellectual property
|
||||
REM laws.
|
||||
REM
|
||||
REM DISCLAIMER
|
||||
REM This disclaimer is not a license and does not grant any
|
||||
REM rights to the materials distributed herewith. Except as
|
||||
REM otherwise provided in a valid license issued to you by
|
||||
REM Xilinx, and to the maximum extent permitted by applicable
|
||||
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
REM (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
REM including negligence, or under any other theory of
|
||||
REM liability) for any loss or damage of any kind or nature
|
||||
REM related to, arising under or in connection with these
|
||||
REM materials, including for any direct, or any indirect,
|
||||
REM special, incidental, or consequential loss or damage
|
||||
REM (including loss of data, profits, goodwill, or any type of
|
||||
REM loss or damage suffered as a result of any action brought
|
||||
REM by a third party) even if such damage or loss was
|
||||
REM reasonably foreseeable or Xilinx had been advised of the
|
||||
REM possibility of the same.
|
||||
REM
|
||||
REM CRITICAL APPLICATIONS
|
||||
REM Xilinx products are not designed or intended to be fail-
|
||||
REM safe, or for use in any application requiring fail-safe
|
||||
REM performance, such as life-support or safety devices or
|
||||
REM systems, Class III medical devices, nuclear facilities,
|
||||
REM applications related to the deployment of airbags, or any
|
||||
REM other applications that could lead to death, personal
|
||||
REM injury, or severe property or environmental damage
|
||||
REM (individually and collectively, "Critical
|
||||
REM Applications"). Customer assumes the sole risk and
|
||||
REM liability of any use of Xilinx products in Critical
|
||||
REM Applications, subject only to applicable laws and
|
||||
REM regulations governing limitations on product liability.
|
||||
REM
|
||||
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
REM PART OF THIS FILE AT ALL TIMES.
|
||||
REM
|
||||
# set up the working directory
|
||||
set work work
|
||||
vlib work
|
||||
|
||||
REM compile all of the files
|
||||
vlog -work work %XILINX%\verilog\src\glbl.v
|
||||
vlog -work work ..\..\implement\results\routed.v
|
||||
vlog -work work b200_clk_gen_tb.v
|
||||
|
||||
REM run the simulation
|
||||
vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax b200_clk_gen_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.b200_clk_gen_tb work.glbl
|
||||
@@ -0,0 +1,65 @@
|
||||
# file: simulate_mti.do
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# set up the working directory
|
||||
set work work
|
||||
vlib work
|
||||
|
||||
# compile all of the files
|
||||
vlog -work work $env(XILINX)/verilog/src/glbl.v
|
||||
vlog -work work ../../implement/results/routed.v
|
||||
vlog -work work b200_clk_gen_tb.v
|
||||
|
||||
# run the simulation
|
||||
vsim -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax b200_clk_gen_tb/dut=../../implement/results/routed.sdf +no_notifier work.b200_clk_gen_tb work.glbl
|
||||
#do wave.do
|
||||
#log -r /*
|
||||
run 50000ns
|
||||
|
||||
|
||||
@@ -0,0 +1,61 @@
|
||||
#/bin/sh
|
||||
# file: simulate_mti.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# set up the working directory
|
||||
set work work
|
||||
vlib work
|
||||
|
||||
# compile all of the files
|
||||
vlog -work work $XILINX/verilog/src/glbl.v
|
||||
vlog -work work ../../implement/results/routed.v
|
||||
vlog -work work b200_clk_gen_tb.v
|
||||
|
||||
# run the simulation
|
||||
vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax b200_clk_gen_tb/dut=../../implement/results/routed.sdf +no_notifier work.b200_clk_gen_tb work.glbl
|
||||
@@ -0,0 +1,64 @@
|
||||
#!/bin/sh
|
||||
# file: simulate_ncsim.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# set up the working directory
|
||||
mkdir work
|
||||
|
||||
# compile all of the files
|
||||
ncvlog -work work ${XILINX}/verilog/src/glbl.v
|
||||
ncvlog -work work ../../implement/results/routed.v
|
||||
ncvlog -work work b200_clk_gen_tb.v
|
||||
|
||||
# elaborate and run the simulation
|
||||
ncsdfc ../../implement/results/routed.sdf
|
||||
|
||||
ncelab -work work -access +wc -pulse_r 10 -nonotifier work.b200_clk_gen_tb work.glbl -sdf_cmd_file sdf_cmd_file
|
||||
ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.b200_clk_gen_tb
|
||||
|
||||
@@ -0,0 +1,72 @@
|
||||
#!/bin/sh
|
||||
# file: simulate_vcs.sh
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# remove old files
|
||||
rm -rf simv* csrc DVEfiles AN.DB
|
||||
|
||||
# compile all of the files
|
||||
# Note that -sverilog is not strictly required- You can
|
||||
# remove the -sverilog if you change the type of the
|
||||
# localparam for the periods in the testbench file to
|
||||
# [63:0] from time
|
||||
vlogan -sverilog \
|
||||
b200_clk_gen_tb.v \
|
||||
../../implement/results/routed.v
|
||||
|
||||
|
||||
# prepare the simulation
|
||||
vcs -sdf max:b200_clk_gen_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \
|
||||
+libext+.v -debug b200_clk_gen_tb.v ../../implement/results/routed.v
|
||||
|
||||
# run the simulation
|
||||
./simv -ucli -i ucli_commands.key
|
||||
|
||||
# launch the viewer
|
||||
#dve -vpd vcdplus.vpd -session vcs_session.tcl
|
||||
@@ -0,0 +1,5 @@
|
||||
|
||||
call {$vcdpluson}
|
||||
run 50000ns
|
||||
call {$vcdplusclose}
|
||||
quit
|
||||
@@ -0,0 +1 @@
|
||||
gui_open_window Wave
|
||||
+72
@@ -0,0 +1,72 @@
|
||||
# file: wave.do
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate /b200_clk_gen_tb/CLK_IN1
|
||||
add wave -noupdate /b200_clk_gen_tb/COUNT
|
||||
add wave -noupdate /b200_clk_gen_tb/LOCKED
|
||||
add wave -noupdate /b200_clk_gen_tb/RESET
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {3223025 ps} 0}
|
||||
configure wave -namecolwidth 238
|
||||
configure wave -valuecolwidth 107
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ps
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {74848022 ps}
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user