fpga: e31x: Add DRAM support
This adds DRAM support to E31x devices. Due to the size of the DDR3 memory controller, it is not enabled by default. You can include the memory controller IP in the build by adding the DRAM environment variable to your build. For example: DRAM=1 make E310_SG3 Original-commit: 788fef11ef890c6dcee3be495fc381bcf2990d3b
This commit is contained in:
Wade Fife
@@ -35,6 +35,7 @@ module e31x_core #(
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input wire bus_clk,
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input wire bus_rst,
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input wire clk40,
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input wire clk200,
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// Motherboard Registers: AXI lite interface
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input wire s_axi_aclk,
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@@ -95,6 +96,25 @@ module e31x_core #(
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input wire [32*NUM_CHANNELS-1:0] rx,
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output wire [32*NUM_CHANNELS-1:0] tx,
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// DRAM Controller Clock
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input wire ddr3_sys_clk,
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// DRAM Chip Interface
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output wire [14:0] ddr3_addr,
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output wire [ 2:0] ddr3_ba,
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output wire ddr3_cas_n,
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output wire [ 0:0] ddr3_ck_n,
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output wire [ 0:0] ddr3_ck_p,
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output wire [ 0:0] ddr3_cke,
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output wire ddr3_ras_n,
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output wire ddr3_reset_n,
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output wire ddr3_we_n,
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inout wire [15:0] ddr3_dq,
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inout wire [ 1:0] ddr3_dqs_n,
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inout wire [ 1:0] ddr3_dqs_p,
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output wire [ 1:0] ddr3_dm,
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output wire [ 0:0] ddr3_odt,
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// DMA xport adapter to PS
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input wire [63:0] s_dma_tdata,
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input wire s_dma_tlast,
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@@ -657,6 +677,134 @@ module e31x_core #(
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.tb_period_ns_q32 ()
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);
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/////////////////////////////////////////////////////////////////////////////
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// PL DDR3 Memory Interface
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/////////////////////////////////////////////////////////////////////////////
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localparam NUM_PORTS = 2;
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localparam AXI_DWIDTH = 64;
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wire [ 32*NUM_PORTS-1:0] dram_axi_araddr;
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wire [ 2*NUM_PORTS-1:0] dram_axi_arburst;
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wire [ 4*NUM_PORTS-1:0] dram_axi_arcache;
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wire [ 1*NUM_PORTS-1:0] dram_axi_arid;
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wire [ 8*NUM_PORTS-1:0] dram_axi_arlen;
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wire [ 1*NUM_PORTS-1:0] dram_axi_arlock;
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wire [ 3*NUM_PORTS-1:0] dram_axi_arprot;
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wire [ 4*NUM_PORTS-1:0] dram_axi_arqos;
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wire [ 1*NUM_PORTS-1:0] dram_axi_arready;
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wire [ 4*NUM_PORTS-1:0] dram_axi_arregion;
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wire [ 3*NUM_PORTS-1:0] dram_axi_arsize;
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wire [ 1*NUM_PORTS-1:0] dram_axi_arvalid;
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wire [ 32*NUM_PORTS-1:0] dram_axi_awaddr;
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wire [ 2*NUM_PORTS-1:0] dram_axi_awburst;
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wire [ 4*NUM_PORTS-1:0] dram_axi_awcache;
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wire [ 1*NUM_PORTS-1:0] dram_axi_awid;
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wire [ 8*NUM_PORTS-1:0] dram_axi_awlen;
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wire [ 1*NUM_PORTS-1:0] dram_axi_awlock;
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wire [ 3*NUM_PORTS-1:0] dram_axi_awprot;
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wire [ 4*NUM_PORTS-1:0] dram_axi_awqos;
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wire [ 1*NUM_PORTS-1:0] dram_axi_awready;
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wire [ 4*NUM_PORTS-1:0] dram_axi_awregion;
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wire [ 3*NUM_PORTS-1:0] dram_axi_awsize;
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wire [ 1*NUM_PORTS-1:0] dram_axi_awvalid;
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wire [ 1*NUM_PORTS-1:0] dram_axi_bid;
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wire [ 1*NUM_PORTS-1:0] dram_axi_bready;
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wire [ 2*NUM_PORTS-1:0] dram_axi_bresp;
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wire [ 1*NUM_PORTS-1:0] dram_axi_bvalid;
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wire [ AXI_DWIDTH*NUM_PORTS-1:0] dram_axi_rdata;
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wire [ 1*NUM_PORTS-1:0] dram_axi_rid;
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wire [ 1*NUM_PORTS-1:0] dram_axi_rlast;
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wire [ 1*NUM_PORTS-1:0] dram_axi_rready;
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wire [ 2*NUM_PORTS-1:0] dram_axi_rresp;
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wire [ 1*NUM_PORTS-1:0] dram_axi_rvalid;
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wire [ AXI_DWIDTH*NUM_PORTS-1:0] dram_axi_wdata;
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wire [ 1*NUM_PORTS-1:0] dram_axi_wlast;
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wire [ 1*NUM_PORTS-1:0] dram_axi_wready;
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wire [AXI_DWIDTH/8*NUM_PORTS-1:0] dram_axi_wstrb;
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wire [ 1*NUM_PORTS-1:0] dram_axi_wvalid;
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wire dram_clk;
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wire dram_rst;
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`ifdef ENABLE_DRAM
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begin : gen_dram
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wire clk200_rst;
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synchronizer synchronizer_clk200_rst (
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.clk(clk200 ),
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.rst(1'b0 ),
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.in (bus_rst ),
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.out(clk200_rst)
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);
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e31x_dram #(
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.AXI_DWIDTH(AXI_DWIDTH),
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.NUM_PORTS (NUM_PORTS )
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) e31x_dram_i (
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.sys_rst (bus_rst ),
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.ddr3_sys_clk (ddr3_sys_clk ),
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.clk200 (clk200 ),
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.clk200_rst (clk200_rst ),
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.ddr3_addr (ddr3_addr ),
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.ddr3_ba (ddr3_ba ),
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.ddr3_cas_n (ddr3_cas_n ),
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.ddr3_ck_n (ddr3_ck_n ),
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.ddr3_ck_p (ddr3_ck_p ),
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.ddr3_cke (ddr3_cke ),
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.ddr3_ras_n (ddr3_ras_n ),
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.ddr3_reset_n (ddr3_reset_n ),
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.ddr3_we_n (ddr3_we_n ),
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.ddr3_dq (ddr3_dq ),
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.ddr3_dqs_n (ddr3_dqs_n ),
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.ddr3_dqs_p (ddr3_dqs_p ),
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.ddr3_dm (ddr3_dm ),
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.ddr3_odt (ddr3_odt ),
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.dram_clk (dram_clk ),
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.dram_rst (dram_rst ),
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.dram_axi_araddr (dram_axi_araddr ),
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.dram_axi_arburst (dram_axi_arburst ),
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.dram_axi_arcache (dram_axi_arcache ),
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.dram_axi_arid (dram_axi_arid ),
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.dram_axi_arlen (dram_axi_arlen ),
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.dram_axi_arlock (dram_axi_arlock ),
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.dram_axi_arprot (dram_axi_arprot ),
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.dram_axi_arqos (dram_axi_arqos ),
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.dram_axi_arready (dram_axi_arready ),
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.dram_axi_arregion(dram_axi_arregion),
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.dram_axi_arsize (dram_axi_arsize ),
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.dram_axi_arvalid (dram_axi_arvalid ),
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.dram_axi_awaddr (dram_axi_awaddr ),
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.dram_axi_awburst (dram_axi_awburst ),
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.dram_axi_awcache (dram_axi_awcache ),
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.dram_axi_awid (dram_axi_awid ),
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.dram_axi_awlen (dram_axi_awlen ),
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.dram_axi_awlock (dram_axi_awlock ),
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.dram_axi_awprot (dram_axi_awprot ),
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.dram_axi_awqos (dram_axi_awqos ),
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.dram_axi_awready (dram_axi_awready ),
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.dram_axi_awregion(dram_axi_awregion),
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.dram_axi_awsize (dram_axi_awsize ),
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.dram_axi_awvalid (dram_axi_awvalid ),
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.dram_axi_bid (dram_axi_bid ),
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.dram_axi_bready (dram_axi_bready ),
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.dram_axi_bresp (dram_axi_bresp ),
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.dram_axi_bvalid (dram_axi_bvalid ),
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.dram_axi_rdata (dram_axi_rdata ),
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.dram_axi_rid (dram_axi_rid ),
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.dram_axi_rlast (dram_axi_rlast ),
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.dram_axi_rready (dram_axi_rready ),
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.dram_axi_rresp (dram_axi_rresp ),
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.dram_axi_rvalid (dram_axi_rvalid ),
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.dram_axi_wdata (dram_axi_wdata ),
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.dram_axi_wlast (dram_axi_wlast ),
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.dram_axi_wready (dram_axi_wready ),
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.dram_axi_wstrb (dram_axi_wstrb ),
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.dram_axi_wvalid (dram_axi_wvalid )
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);
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end // gen_dram
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`endif
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/////////////////////////////////////////////////////////////////////////////
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//
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// RFNoC Image Core
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@@ -671,6 +819,7 @@ module e31x_core #(
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.core_arst (bus_rst ),
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.device_id (device_id ),
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.radio_clk (radio_clk ),
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.dram_clk (dram_clk ),
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.m_ctrlport_req_wr (m_ctrlport_req_wr ),
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.m_ctrlport_req_rd (m_ctrlport_req_rd ),
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.m_ctrlport_req_addr (m_ctrlport_req_addr ),
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@@ -688,6 +837,51 @@ module e31x_core #(
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.radio_tx_stb ({tx_stb[1], tx_stb[0] }),
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.radio_tx_data ({tx_data[1], tx_data[0] }),
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.radio_tx_running ({tx_running[1], tx_running[0]}),
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.axi_rst (dram_rst),
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.m_axi_awid (dram_axi_awid),
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.m_axi_awaddr (dram_axi_awaddr),
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.m_axi_awlen (dram_axi_awlen),
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.m_axi_awsize (dram_axi_awsize),
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.m_axi_awburst (dram_axi_awburst),
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.m_axi_awlock (dram_axi_awlock),
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.m_axi_awcache (dram_axi_awcache),
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.m_axi_awprot (dram_axi_awprot),
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.m_axi_awqos (dram_axi_awqos),
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.m_axi_awregion (dram_axi_awregion),
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.m_axi_awuser (),
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.m_axi_awvalid (dram_axi_awvalid),
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.m_axi_awready (dram_axi_awready),
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.m_axi_wdata (dram_axi_wdata),
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.m_axi_wstrb (dram_axi_wstrb),
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.m_axi_wlast (dram_axi_wlast),
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.m_axi_wuser (),
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.m_axi_wvalid (dram_axi_wvalid),
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.m_axi_wready (dram_axi_wready),
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.m_axi_bid (dram_axi_bid),
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.m_axi_bresp (dram_axi_bresp),
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.m_axi_buser (4'b0),
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.m_axi_bvalid (dram_axi_bvalid),
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.m_axi_bready (dram_axi_bready),
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.m_axi_arid (dram_axi_arid),
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.m_axi_araddr (dram_axi_araddr),
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.m_axi_arlen (dram_axi_arlen),
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.m_axi_arsize (dram_axi_arsize),
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.m_axi_arburst (dram_axi_arburst),
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.m_axi_arlock (dram_axi_arlock),
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.m_axi_arcache (dram_axi_arcache),
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.m_axi_arprot (dram_axi_arprot),
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.m_axi_arqos (dram_axi_arqos),
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.m_axi_arregion (dram_axi_arregion),
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.m_axi_aruser (),
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.m_axi_arvalid (dram_axi_arvalid),
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.m_axi_arready (dram_axi_arready),
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.m_axi_rid (dram_axi_rid),
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.m_axi_rdata (dram_axi_rdata),
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.m_axi_rresp (dram_axi_rresp),
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.m_axi_rlast (dram_axi_rlast),
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.m_axi_ruser (4'b0),
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.m_axi_rvalid (dram_axi_rvalid),
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.m_axi_rready (dram_axi_rready),
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.s_dma_tdata (s_dma_tdata),
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.s_dma_tlast (s_dma_tlast),
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.s_dma_tvalid (s_dma_tvalid),
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