diff --git a/top/e31x/Makefile b/top/e31x/Makefile index 80752d7..d5131c8 100644 --- a/top/e31x/Makefile +++ b/top/e31x/Makefile @@ -63,12 +63,12 @@ E310_SG3_IDLE E3XX_idle_sg3: build/usrp_e310_sg3_idle_fpga.dts ##E310_SG1: Build USRP E3XX (Speed Grade 1). E310_SG1 E310: build/usrp_e310_sg1_fpga.dts - $(call vivado_build,E310_SG1, E310_SG1=1) + $(call vivado_build,E310_SG1, E310_SG1=1 $(if $(DRAM),ENABLE_DRAM=1,)) $(call post_build,$@,E310_SG1) ##E310_SG3: Build USRP E3XX (Speed Grade 3). E310_SG3 E310_sg3: build/usrp_e310_sg3_fpga.dts - $(call vivado_build,E310_SG3, E310_SG3=1) + $(call vivado_build,E310_SG3, E310_SG3=1 $(if $(DRAM),ENABLE_DRAM=1,)) $(call post_build,$@,E310_SG3) @@ -93,6 +93,8 @@ help: ##Show this help message. ## ##Supported Options ##----------------- +##DRAM=1 Include DDR3 SDRAM memory controller IP in the FPGA build. +## Note: The RFNoC image core must also be configured to use DRAM. ##GUI=1 Launch the build in the Vivado GUI. ##CHECK=1 Launch the syntax checker instead of building a bitfile. ##SYNTH=1 Launch the build but stop after synthesis. diff --git a/top/e31x/Makefile.e31x.inc b/top/e31x/Makefile.e31x.inc index 5e0f2ce..4e017ca 100644 --- a/top/e31x/Makefile.e31x.inc +++ b/top/e31x/Makefile.e31x.inc @@ -32,11 +32,13 @@ include $(LIB_DIR)/dsp/Makefile.srcs include $(LIB_DIR)/io_cap_gen/Makefile.srcs include $(LIB_DIR)/rfnoc/Makefile.srcs # For the sake of convenience, we include the Makefile.srcs for the DDC, DUC, -# and the radio. Any other block needs to use the RFNOC_OOT_MAKEFILE_SRCS -# variable (see below). +# radio, replay and FIFO blocks. Any other block needs to use the +# RFNOC_OOT_MAKEFILE_SRCS variable (see below). include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs +include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_replay/Makefile.srcs +include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs # If out-of-tree modules want to be compiled into this image, then they need to # pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files. # Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual @@ -58,6 +60,7 @@ spi_slave.v ifneq (IDLE,$(findstring IDLE, $(EXTRA_DEFS))) TOP_SRCS += e31x.v TOP_SRCS += e31x_core.v +TOP_SRCS += e31x_dram.v TOP_SRCS += e310_io.v TOP_SRCS += $(EDGE_FILE) $(IMAGE_CORE) MB_XDC = \ @@ -69,6 +72,8 @@ MB_XDC = \ e31x_idle_pins.xdc endif +DRAM_SRCS = $(IP_DRAM_XCI_SRCS) + # The XDC files must be read in a specific order, motherboard first and then daughterboard. # Outside of that, all the other sources can be read in any order desired. DESIGN_SRCS = \ @@ -96,6 +101,8 @@ $(CAP_GEN_GENERIC_SRCS) \ $(RFNOC_OOT_SRCS)\ $(RFNOC_FRAMEWORK_SRCS) $(RFNOC_BLOCK_NULL_SRC_SINK_SRCS) \ $(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) $(RFNOC_BLOCK_RADIO_SRCS) \ +$(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \ +$(RFNOC_BLOCK_REPLAY_SRCS) \ $(RFNOC_BLOCK_EXAMPLE_SRCS) \ $(abspath $(MB_XDC)) diff --git a/top/e31x/e310_rfnoc_image_core.v b/top/e31x/e310_rfnoc_image_core.v index 5d3e47f..81c6784 100644 --- a/top/e31x/e310_rfnoc_image_core.v +++ b/top/e31x/e310_rfnoc_image_core.v @@ -1,5 +1,5 @@ // -// Copyright 2021 Ettus Research, A National Instruments Brand +// Copyright 2022 Ettus Research, A National Instruments Brand // // SPDX-License-Identifier: LGPL-3.0-or-later // @@ -13,7 +13,7 @@ // This file was automatically generated by the RFNoC image builder tool. // Re-running that tool will overwrite this file! // -// File generated on: 2021-05-03T08:51:11.395850 +// File generated on: 2022-02-07T19:18:27.980096 // Source: e310_rfnoc_image_core.yml // Source SHA256: 7fef622f1ae280dd7573abd823c7a6bbecf51921a74cea948e6bfb9f8f65e2cc // @@ -32,6 +32,7 @@ module rfnoc_image_core #( input wire ctrl_aclk, input wire core_arst, input wire radio_clk, + input wire dram_clk, // Basic input wire [ 15:0] device_id, @@ -57,6 +58,52 @@ module rfnoc_image_core #( output wire [ 63:0] radio_tx_data, input wire [ 1:0] radio_tx_stb, output wire [ 1:0] radio_tx_running, + // dram + input wire [ 0:0] axi_rst, + output wire [ 3:0] m_axi_awid, + output wire [ 127:0] m_axi_awaddr, + output wire [ 31:0] m_axi_awlen, + output wire [ 11:0] m_axi_awsize, + output wire [ 7:0] m_axi_awburst, + output wire [ 3:0] m_axi_awlock, + output wire [ 15:0] m_axi_awcache, + output wire [ 11:0] m_axi_awprot, + output wire [ 15:0] m_axi_awqos, + output wire [ 15:0] m_axi_awregion, + output wire [ 3:0] m_axi_awuser, + output wire [ 3:0] m_axi_awvalid, + input wire [ 3:0] m_axi_awready, + output wire [ 255:0] m_axi_wdata, + output wire [ 31:0] m_axi_wstrb, + output wire [ 3:0] m_axi_wlast, + output wire [ 3:0] m_axi_wuser, + output wire [ 3:0] m_axi_wvalid, + input wire [ 3:0] m_axi_wready, + input wire [ 3:0] m_axi_bid, + input wire [ 7:0] m_axi_bresp, + input wire [ 3:0] m_axi_buser, + input wire [ 3:0] m_axi_bvalid, + output wire [ 3:0] m_axi_bready, + output wire [ 3:0] m_axi_arid, + output wire [ 127:0] m_axi_araddr, + output wire [ 31:0] m_axi_arlen, + output wire [ 11:0] m_axi_arsize, + output wire [ 7:0] m_axi_arburst, + output wire [ 3:0] m_axi_arlock, + output wire [ 15:0] m_axi_arcache, + output wire [ 11:0] m_axi_arprot, + output wire [ 15:0] m_axi_arqos, + output wire [ 15:0] m_axi_arregion, + output wire [ 3:0] m_axi_aruser, + output wire [ 3:0] m_axi_arvalid, + input wire [ 3:0] m_axi_arready, + input wire [ 3:0] m_axi_rid, + input wire [ 255:0] m_axi_rdata, + input wire [ 7:0] m_axi_rresp, + input wire [ 3:0] m_axi_rlast, + input wire [ 3:0] m_axi_ruser, + input wire [ 3:0] m_axi_rvalid, + output wire [ 3:0] m_axi_rready, // Transport Adapters /////////////// diff --git a/top/e31x/e310_rfnoc_image_core.vh b/top/e31x/e310_rfnoc_image_core.vh index 83ff837..8ea5b7c 100644 --- a/top/e31x/e310_rfnoc_image_core.vh +++ b/top/e31x/e310_rfnoc_image_core.vh @@ -1,5 +1,5 @@ // -// Copyright 2021 Ettus Research, A National Instruments Brand +// Copyright 2022 Ettus Research, A National Instruments Brand // // SPDX-License-Identifier: LGPL-3.0-or-later // @@ -12,7 +12,7 @@ // This file was automatically generated by the RFNoC image builder tool. // Re-running that tool will overwrite this file! // -// File generated on: 2021-05-03T08:51:11.441866 +// File generated on: 2022-02-07T19:18:28.012652 // Source: e310_rfnoc_image_core.yml // Source SHA256: 7fef622f1ae280dd7573abd823c7a6bbecf51921a74cea948e6bfb9f8f65e2cc // diff --git a/top/e31x/e31x.v b/top/e31x/e31x.v index b303f9a..57c1346 100644 --- a/top/e31x/e31x.v +++ b/top/e31x/e31x.v @@ -36,22 +36,24 @@ module e31x ( inout DDR_VRP, inout DDR_VRN, - // PL DDR - //input PL_DDR3_SYSCLK, - //output PL_DDR3_RESET_N, - //inout [15:0] PL_DDR3_DQ, - //inout [1:0] PL_DDR3_DQS_N, - //inout [1:0] PL_DDR3_DQS_P, - //output [14:0] PL_DDR3_ADDR, - //output [2:0] PL_DDR3_BA, - //output PL_DDR3_RAS_N, - //output PL_DDR3_CAS_N, - //output PL_DDR3_WE_N, - //output [0:0] PL_DDR3_CK_P, - //output [0:0] PL_DDR3_CK_N, - //output [0:0] PL_DDR3_CKE, - //output [1:0] PL_DDR3_DM, - //output [0:0] PL_DDR3_ODT, + // PL DRAM +`ifdef ENABLE_DRAM + input PL_DDR3_SYSCLK, + output PL_DDR3_RESET_N, + inout [15:0] PL_DDR3_DQ, + inout [ 1:0] PL_DDR3_DQS_N, + inout [ 1:0] PL_DDR3_DQS_P, + output [14:0] PL_DDR3_ADDR, + output [ 2:0] PL_DDR3_BA, + output PL_DDR3_RAS_N, + output PL_DDR3_CAS_N, + output PL_DDR3_WE_N, + output [ 0:0] PL_DDR3_CK_P, + output [ 0:0] PL_DDR3_CK_N, + output [ 0:0] PL_DDR3_CKE, + output [ 1:0] PL_DDR3_DM, + output [ 0:0] PL_DDR3_ODT, +`endif //AVR SPI IO input AVR_CS_R, @@ -154,6 +156,8 @@ module e31x ( wire radio_clk; wire reg_clk; wire clk40; + wire clk166; + wire clk200; wire FCLK_CLK0; wire FCLK_CLK1; wire FCLK_CLK2; @@ -307,9 +311,10 @@ module e31x ( wire [1:0] pps_select; - assign clk40 = FCLK_CLK1; // 40 MHz assign bus_clk = FCLK_CLK0; // 100 MHz - //assign bus_clk = FCLK_CLK3; // 200 MHz + assign clk40 = FCLK_CLK1; // 40 MHz + assign clk166 = FCLK_CLK2; // 166.666 MHz + assign clk200 = FCLK_CLK3; // 200 MHz assign reg_clk = clk40; wire pps; @@ -802,7 +807,7 @@ module e31x ( // when only using radio core 1. assign TX_BANDSEL = TX1_BANDSEL | TX2_BANDSEL; - ///////////////////////////////////////////////////////////////////// + ///////////////////////////////////////////////////////////////////// // // Front-Panel GPIO // @@ -850,6 +855,7 @@ module e31x ( .bus_clk(bus_clk), .bus_rst(bus_rst), .clk40(clk40), + .clk200(clk200), // Clocking and PPS Controls/Indicators .pps_refclk(pps), @@ -912,6 +918,25 @@ module e31x ( .rx(rx_flat), .tx(tx_flat), + // DRAM Controller Clock + .ddr3_sys_clk(PL_DDR3_SYSCLK), + + // DRAM Chip Interface + .ddr3_addr(PL_DDR3_ADDR), + .ddr3_ba(PL_DDR3_BA), + .ddr3_cas_n(PL_DDR3_CAS_N), + .ddr3_ck_n(PL_DDR3_CK_N), + .ddr3_ck_p(PL_DDR3_CK_P), + .ddr3_cke(PL_DDR3_CKE), + .ddr3_ras_n(PL_DDR3_RAS_N), + .ddr3_reset_n(PL_DDR3_RESET_N), + .ddr3_we_n(PL_DDR3_WE_N), + .ddr3_dq(PL_DDR3_DQ), + .ddr3_dqs_n(PL_DDR3_DQS_N), + .ddr3_dqs_p(PL_DDR3_DQS_P), + .ddr3_dm(PL_DDR3_DM), + .ddr3_odt(PL_DDR3_ODT), + // Internal DMA to PS .m_dma_tdata(s_axis_dma_tdata), .m_dma_tlast(s_axis_dma_tlast), @@ -932,38 +957,6 @@ module e31x ( .device_id(device_id) ); - ///////////////////////////////////////////////////////////////////// - // - // PL DDR3 Memory Interface - // - ///////////////////////////////////////////////////////////////////// - - //wire pl_dram_clk = FCLK_CLK3; - //wire pl_dram_rst = ~FCLK_RESET0_N; - - //example_top inst_example_top - //( - // .ddr3_dq (PL_DDR3_DQ), - // .ddr3_dqs_n (PL_DDR3_DQS_N), - // .ddr3_dqs_p (PL_DDR3_DQS_P), - // .ddr3_addr (PL_DDR3_ADDR), - // .ddr3_ba (PL_DDR3_BA), - // .ddr3_ras_n (PL_DDR3_RAS_N), - // .ddr3_cas_n (PL_DDR3_CAS_N), - // .ddr3_we_n (PL_DDR3_WE_N), - // .ddr3_reset_n (PL_DDR3_RESET_N), - // .ddr3_ck_p (PL_DDR3_CK_P), - // .ddr3_ck_n (PL_DDR3_CK_N), - // .ddr3_cke (PL_DDR3_CKE), - // .ddr3_dm (PL_DDR3_DM), - // .ddr3_odt (PL_DDR3_ODT), - // .sys_clk_i (PL_DDR3_SYSCLK), - // .clk_ref_i (pl_dram_clk), - // .tg_compare_error (), - // .init_calib_complete (), - // .sys_rst (pl_dram_rst) - //); - // PMU axi_pmu inst_axi_pmu ( .s_axi_aclk(clk40), // TODO: Original design used bus_clk diff --git a/top/e31x/e31x_core.v b/top/e31x/e31x_core.v index 6e1d2ed..9967526 100644 --- a/top/e31x/e31x_core.v +++ b/top/e31x/e31x_core.v @@ -35,6 +35,7 @@ module e31x_core #( input wire bus_clk, input wire bus_rst, input wire clk40, + input wire clk200, // Motherboard Registers: AXI lite interface input wire s_axi_aclk, @@ -95,6 +96,25 @@ module e31x_core #( input wire [32*NUM_CHANNELS-1:0] rx, output wire [32*NUM_CHANNELS-1:0] tx, + // DRAM Controller Clock + input wire ddr3_sys_clk, + + // DRAM Chip Interface + output wire [14:0] ddr3_addr, + output wire [ 2:0] ddr3_ba, + output wire ddr3_cas_n, + output wire [ 0:0] ddr3_ck_n, + output wire [ 0:0] ddr3_ck_p, + output wire [ 0:0] ddr3_cke, + output wire ddr3_ras_n, + output wire ddr3_reset_n, + output wire ddr3_we_n, + inout wire [15:0] ddr3_dq, + inout wire [ 1:0] ddr3_dqs_n, + inout wire [ 1:0] ddr3_dqs_p, + output wire [ 1:0] ddr3_dm, + output wire [ 0:0] ddr3_odt, + // DMA xport adapter to PS input wire [63:0] s_dma_tdata, input wire s_dma_tlast, @@ -657,6 +677,134 @@ module e31x_core #( .tb_period_ns_q32 () ); + ///////////////////////////////////////////////////////////////////////////// + // PL DDR3 Memory Interface + ///////////////////////////////////////////////////////////////////////////// + + localparam NUM_PORTS = 2; + localparam AXI_DWIDTH = 64; + + wire [ 32*NUM_PORTS-1:0] dram_axi_araddr; + wire [ 2*NUM_PORTS-1:0] dram_axi_arburst; + wire [ 4*NUM_PORTS-1:0] dram_axi_arcache; + wire [ 1*NUM_PORTS-1:0] dram_axi_arid; + wire [ 8*NUM_PORTS-1:0] dram_axi_arlen; + wire [ 1*NUM_PORTS-1:0] dram_axi_arlock; + wire [ 3*NUM_PORTS-1:0] dram_axi_arprot; + wire [ 4*NUM_PORTS-1:0] dram_axi_arqos; + wire [ 1*NUM_PORTS-1:0] dram_axi_arready; + wire [ 4*NUM_PORTS-1:0] dram_axi_arregion; + wire [ 3*NUM_PORTS-1:0] dram_axi_arsize; + wire [ 1*NUM_PORTS-1:0] dram_axi_arvalid; + wire [ 32*NUM_PORTS-1:0] dram_axi_awaddr; + wire [ 2*NUM_PORTS-1:0] dram_axi_awburst; + wire [ 4*NUM_PORTS-1:0] dram_axi_awcache; + wire [ 1*NUM_PORTS-1:0] dram_axi_awid; + wire [ 8*NUM_PORTS-1:0] dram_axi_awlen; + wire [ 1*NUM_PORTS-1:0] dram_axi_awlock; + wire [ 3*NUM_PORTS-1:0] dram_axi_awprot; + wire [ 4*NUM_PORTS-1:0] dram_axi_awqos; + wire [ 1*NUM_PORTS-1:0] dram_axi_awready; + wire [ 4*NUM_PORTS-1:0] dram_axi_awregion; + wire [ 3*NUM_PORTS-1:0] dram_axi_awsize; + wire [ 1*NUM_PORTS-1:0] dram_axi_awvalid; + wire [ 1*NUM_PORTS-1:0] dram_axi_bid; + wire [ 1*NUM_PORTS-1:0] dram_axi_bready; + wire [ 2*NUM_PORTS-1:0] dram_axi_bresp; + wire [ 1*NUM_PORTS-1:0] dram_axi_bvalid; + wire [ AXI_DWIDTH*NUM_PORTS-1:0] dram_axi_rdata; + wire [ 1*NUM_PORTS-1:0] dram_axi_rid; + wire [ 1*NUM_PORTS-1:0] dram_axi_rlast; + wire [ 1*NUM_PORTS-1:0] dram_axi_rready; + wire [ 2*NUM_PORTS-1:0] dram_axi_rresp; + wire [ 1*NUM_PORTS-1:0] dram_axi_rvalid; + wire [ AXI_DWIDTH*NUM_PORTS-1:0] dram_axi_wdata; + wire [ 1*NUM_PORTS-1:0] dram_axi_wlast; + wire [ 1*NUM_PORTS-1:0] dram_axi_wready; + wire [AXI_DWIDTH/8*NUM_PORTS-1:0] dram_axi_wstrb; + wire [ 1*NUM_PORTS-1:0] dram_axi_wvalid; + + wire dram_clk; + wire dram_rst; + + `ifdef ENABLE_DRAM + begin : gen_dram + wire clk200_rst; + + synchronizer synchronizer_clk200_rst ( + .clk(clk200 ), + .rst(1'b0 ), + .in (bus_rst ), + .out(clk200_rst) + ); + + e31x_dram #( + .AXI_DWIDTH(AXI_DWIDTH), + .NUM_PORTS (NUM_PORTS ) + ) e31x_dram_i ( + .sys_rst (bus_rst ), + .ddr3_sys_clk (ddr3_sys_clk ), + .clk200 (clk200 ), + .clk200_rst (clk200_rst ), + .ddr3_addr (ddr3_addr ), + .ddr3_ba (ddr3_ba ), + .ddr3_cas_n (ddr3_cas_n ), + .ddr3_ck_n (ddr3_ck_n ), + .ddr3_ck_p (ddr3_ck_p ), + .ddr3_cke (ddr3_cke ), + .ddr3_ras_n (ddr3_ras_n ), + .ddr3_reset_n (ddr3_reset_n ), + .ddr3_we_n (ddr3_we_n ), + .ddr3_dq (ddr3_dq ), + .ddr3_dqs_n (ddr3_dqs_n ), + .ddr3_dqs_p (ddr3_dqs_p ), + .ddr3_dm (ddr3_dm ), + .ddr3_odt (ddr3_odt ), + .dram_clk (dram_clk ), + .dram_rst (dram_rst ), + .dram_axi_araddr (dram_axi_araddr ), + .dram_axi_arburst (dram_axi_arburst ), + .dram_axi_arcache (dram_axi_arcache ), + .dram_axi_arid (dram_axi_arid ), + .dram_axi_arlen (dram_axi_arlen ), + .dram_axi_arlock (dram_axi_arlock ), + .dram_axi_arprot (dram_axi_arprot ), + .dram_axi_arqos (dram_axi_arqos ), + .dram_axi_arready (dram_axi_arready ), + .dram_axi_arregion(dram_axi_arregion), + .dram_axi_arsize (dram_axi_arsize ), + .dram_axi_arvalid (dram_axi_arvalid ), + .dram_axi_awaddr (dram_axi_awaddr ), + .dram_axi_awburst (dram_axi_awburst ), + .dram_axi_awcache (dram_axi_awcache ), + .dram_axi_awid (dram_axi_awid ), + .dram_axi_awlen (dram_axi_awlen ), + .dram_axi_awlock (dram_axi_awlock ), + .dram_axi_awprot (dram_axi_awprot ), + .dram_axi_awqos (dram_axi_awqos ), + .dram_axi_awready (dram_axi_awready ), + .dram_axi_awregion(dram_axi_awregion), + .dram_axi_awsize (dram_axi_awsize ), + .dram_axi_awvalid (dram_axi_awvalid ), + .dram_axi_bid (dram_axi_bid ), + .dram_axi_bready (dram_axi_bready ), + .dram_axi_bresp (dram_axi_bresp ), + .dram_axi_bvalid (dram_axi_bvalid ), + .dram_axi_rdata (dram_axi_rdata ), + .dram_axi_rid (dram_axi_rid ), + .dram_axi_rlast (dram_axi_rlast ), + .dram_axi_rready (dram_axi_rready ), + .dram_axi_rresp (dram_axi_rresp ), + .dram_axi_rvalid (dram_axi_rvalid ), + .dram_axi_wdata (dram_axi_wdata ), + .dram_axi_wlast (dram_axi_wlast ), + .dram_axi_wready (dram_axi_wready ), + .dram_axi_wstrb (dram_axi_wstrb ), + .dram_axi_wvalid (dram_axi_wvalid ) + ); + end // gen_dram + `endif + ///////////////////////////////////////////////////////////////////////////// // // RFNoC Image Core @@ -671,6 +819,7 @@ module e31x_core #( .core_arst (bus_rst ), .device_id (device_id ), .radio_clk (radio_clk ), + .dram_clk (dram_clk ), .m_ctrlport_req_wr (m_ctrlport_req_wr ), .m_ctrlport_req_rd (m_ctrlport_req_rd ), .m_ctrlport_req_addr (m_ctrlport_req_addr ), @@ -688,6 +837,51 @@ module e31x_core #( .radio_tx_stb ({tx_stb[1], tx_stb[0] }), .radio_tx_data ({tx_data[1], tx_data[0] }), .radio_tx_running ({tx_running[1], tx_running[0]}), + .axi_rst (dram_rst), + .m_axi_awid (dram_axi_awid), + .m_axi_awaddr (dram_axi_awaddr), + .m_axi_awlen (dram_axi_awlen), + .m_axi_awsize (dram_axi_awsize), + .m_axi_awburst (dram_axi_awburst), + .m_axi_awlock (dram_axi_awlock), + .m_axi_awcache (dram_axi_awcache), + .m_axi_awprot (dram_axi_awprot), + .m_axi_awqos (dram_axi_awqos), + .m_axi_awregion (dram_axi_awregion), + .m_axi_awuser (), + .m_axi_awvalid (dram_axi_awvalid), + .m_axi_awready (dram_axi_awready), + .m_axi_wdata (dram_axi_wdata), + .m_axi_wstrb (dram_axi_wstrb), + .m_axi_wlast (dram_axi_wlast), + .m_axi_wuser (), + .m_axi_wvalid (dram_axi_wvalid), + .m_axi_wready (dram_axi_wready), + .m_axi_bid (dram_axi_bid), + .m_axi_bresp (dram_axi_bresp), + .m_axi_buser (4'b0), + .m_axi_bvalid (dram_axi_bvalid), + .m_axi_bready (dram_axi_bready), + .m_axi_arid (dram_axi_arid), + .m_axi_araddr (dram_axi_araddr), + .m_axi_arlen (dram_axi_arlen), + .m_axi_arsize (dram_axi_arsize), + .m_axi_arburst (dram_axi_arburst), + .m_axi_arlock (dram_axi_arlock), + .m_axi_arcache (dram_axi_arcache), + .m_axi_arprot (dram_axi_arprot), + .m_axi_arqos (dram_axi_arqos), + .m_axi_arregion (dram_axi_arregion), + .m_axi_aruser (), + .m_axi_arvalid (dram_axi_arvalid), + .m_axi_arready (dram_axi_arready), + .m_axi_rid (dram_axi_rid), + .m_axi_rdata (dram_axi_rdata), + .m_axi_rresp (dram_axi_rresp), + .m_axi_rlast (dram_axi_rlast), + .m_axi_ruser (4'b0), + .m_axi_rvalid (dram_axi_rvalid), + .m_axi_rready (dram_axi_rready), .s_dma_tdata (s_dma_tdata), .s_dma_tlast (s_dma_tlast), .s_dma_tvalid (s_dma_tvalid), diff --git a/top/e31x/e31x_dram.v b/top/e31x/e31x_dram.v new file mode 100644 index 0000000..2918f91 --- /dev/null +++ b/top/e31x/e31x_dram.v @@ -0,0 +1,422 @@ +// +// Copyright 2022 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: e31x_dram +// +// Description: +// +// Includes the AXI interconnect and DRAM IP to allow two AXI ports to share +// the DRAM on E31x devices. +// +// Two configurations are currently supported, as shown below. +// +// AXI_DWIDTH NUM_PORTS dram_clk +// --------------------------------------- +// 128 1 100 MHz (ui_clk) +// 64 2 200 MHz (clk200) +// +// Parameters: +// +// AXI_DWIDTH : Width of the dram_axi_* data bus. Can be 64 or 128-bit. +// NUM_PORTS : Number of AXI ports to make available through the dram_axi_* +// bus. Can be 1 or 2. +// + + +module e31x_dram #( + parameter AXI_DWIDTH = 64, + parameter NUM_PORTS = 2 +) ( + // Asynchronous reset for DDR3 controller + input wire sys_rst, + + // Clock for DDR3 controller + input wire ddr3_sys_clk, + + // 200 MHz clock + input wire clk200, + input wire clk200_rst, + + //--------------------------------------------------------------------------- + // DRAM Chip Interface + //--------------------------------------------------------------------------- + + output wire [14:0] ddr3_addr, + output wire [2:0] ddr3_ba, + output wire ddr3_cas_n, + output wire [0:0] ddr3_ck_n, + output wire [0:0] ddr3_ck_p, + output wire [0:0] ddr3_cke, + output wire ddr3_ras_n, + output wire ddr3_reset_n, + output wire ddr3_we_n, + inout wire [15:0] ddr3_dq, + inout wire [1:0] ddr3_dqs_n, + inout wire [1:0] ddr3_dqs_p, + output wire [1:0] ddr3_dm, + output wire [0:0] ddr3_odt, + + //--------------------------------------------------------------------------- + // DRAM User Interfaces (Synchronous to dram_clk) + //--------------------------------------------------------------------------- + + output wire dram_clk, + output wire dram_rst, + + input wire [ 29*NUM_PORTS-1:0] dram_axi_araddr, + input wire [ 2*NUM_PORTS-1:0] dram_axi_arburst, + input wire [ 4*NUM_PORTS-1:0] dram_axi_arcache, + input wire [ 1*NUM_PORTS-1:0] dram_axi_arid, + input wire [ 8*NUM_PORTS-1:0] dram_axi_arlen, + input wire [ 1*NUM_PORTS-1:0] dram_axi_arlock, + input wire [ 3*NUM_PORTS-1:0] dram_axi_arprot, + input wire [ 4*NUM_PORTS-1:0] dram_axi_arqos, + output wire [ 1*NUM_PORTS-1:0] dram_axi_arready, + input wire [ 4*NUM_PORTS-1:0] dram_axi_arregion, + input wire [ 3*NUM_PORTS-1:0] dram_axi_arsize, + input wire [ 1*NUM_PORTS-1:0] dram_axi_arvalid, + input wire [ 29*NUM_PORTS-1:0] dram_axi_awaddr, + input wire [ 2*NUM_PORTS-1:0] dram_axi_awburst, + input wire [ 4*NUM_PORTS-1:0] dram_axi_awcache, + input wire [ 1*NUM_PORTS-1:0] dram_axi_awid, + input wire [ 8*NUM_PORTS-1:0] dram_axi_awlen, + input wire [ 1*NUM_PORTS-1:0] dram_axi_awlock, + input wire [ 3*NUM_PORTS-1:0] dram_axi_awprot, + input wire [ 4*NUM_PORTS-1:0] dram_axi_awqos, + output wire [ 1*NUM_PORTS-1:0] dram_axi_awready, + input wire [ 4*NUM_PORTS-1:0] dram_axi_awregion, + input wire [ 3*NUM_PORTS-1:0] dram_axi_awsize, + input wire [ 1*NUM_PORTS-1:0] dram_axi_awvalid, + output wire [ 1*NUM_PORTS-1:0] dram_axi_bid, + input wire [ 1*NUM_PORTS-1:0] dram_axi_bready, + output wire [ 2*NUM_PORTS-1:0] dram_axi_bresp, + output wire [ 1*NUM_PORTS-1:0] dram_axi_bvalid, + output wire [ AXI_DWIDTH*NUM_PORTS-1:0] dram_axi_rdata, + output wire [ 1*NUM_PORTS-1:0] dram_axi_rid, + output wire [ 1*NUM_PORTS-1:0] dram_axi_rlast, + input wire [ 1*NUM_PORTS-1:0] dram_axi_rready, + output wire [ 2*NUM_PORTS-1:0] dram_axi_rresp, + output wire [ 1*NUM_PORTS-1:0] dram_axi_rvalid, + input wire [ AXI_DWIDTH*NUM_PORTS-1:0] dram_axi_wdata, + input wire [ 1*NUM_PORTS-1:0] dram_axi_wlast, + output wire [ 1*NUM_PORTS-1:0] dram_axi_wready, + input wire [AXI_DWIDTH/8*NUM_PORTS-1:0] dram_axi_wstrb, + input wire [ 1*NUM_PORTS-1:0] dram_axi_wvalid +); + + //--------------------------------------------------------------------------- + // Assertions + //--------------------------------------------------------------------------- + + if (!( + (NUM_PORTS == 1 && AXI_DWIDTH == 128) || + (NUM_PORTS == 2 && AXI_DWIDTH == 64) + )) begin : check_parameters + ERROR_Unsupported_combination_of_parameters_on_e31x_dram(); + end + + //--------------------------------------------------------------------------- + // AXI Interconnect + //--------------------------------------------------------------------------- + + wire ui_clk; + wire ui_rst; + + // DDR3 Memory Controller AXI Interface + wire [11:0] ddr3_axi_awid; + wire [28:0] ddr3_axi_awaddr; + wire [ 7:0] ddr3_axi_awlen; + wire [ 2:0] ddr3_axi_awsize; + wire [ 1:0] ddr3_axi_awburst; + wire [ 0:0] ddr3_axi_awlock; + wire [ 3:0] ddr3_axi_awcache; + wire [ 2:0] ddr3_axi_awprot; + wire [ 3:0] ddr3_axi_awqos; + wire ddr3_axi_awvalid; + wire ddr3_axi_awready; + wire [127:0] ddr3_axi_wdata; + wire [ 15:0] ddr3_axi_wstrb; + wire ddr3_axi_wlast; + wire ddr3_axi_wvalid; + wire ddr3_axi_wready; + wire [11:0] ddr3_axi_bid; + wire [ 1:0] ddr3_axi_bresp; + wire ddr3_axi_bvalid; + wire ddr3_axi_bready; + wire [11:0] ddr3_axi_arid; + wire [28:0] ddr3_axi_araddr; + wire [ 7:0] ddr3_axi_arlen; + wire [ 2:0] ddr3_axi_arsize; + wire [ 1:0] ddr3_axi_arburst; + wire [ 0:0] ddr3_axi_arlock; + wire [ 3:0] ddr3_axi_arcache; + wire [ 2:0] ddr3_axi_arprot; + wire [ 3:0] ddr3_axi_arqos; + wire ddr3_axi_arvalid; + wire ddr3_axi_arready; + wire [ 11:0] ddr3_axi_rid; + wire [127:0] ddr3_axi_rdata; + wire [ 1:0] ddr3_axi_rresp; + wire ddr3_axi_rlast; + wire ddr3_axi_rvalid; + wire ddr3_axi_rready; + + if (NUM_PORTS == 1 && AXI_DWIDTH == 128) begin : gen_single_port + assign dram_clk = ui_clk; + assign dram_rst = ui_rst; + + assign ddr3_axi_awid = dram_axi_awid; + assign ddr3_axi_awaddr = dram_axi_awaddr; + assign ddr3_axi_awlen = dram_axi_awlen; + assign ddr3_axi_awsize = dram_axi_awsize; + assign ddr3_axi_awburst = dram_axi_awburst; + assign ddr3_axi_awlock = dram_axi_awlock; + assign ddr3_axi_awcache = dram_axi_awcache; + assign ddr3_axi_awprot = dram_axi_awprot; + assign ddr3_axi_awqos = dram_axi_awqos; + assign ddr3_axi_awvalid = dram_axi_awvalid; + assign dram_axi_awready = ddr3_axi_awready; + assign ddr3_axi_wdata = dram_axi_wdata; + assign ddr3_axi_wstrb = dram_axi_wstrb; + assign ddr3_axi_wlast = dram_axi_wlast; + assign ddr3_axi_wvalid = dram_axi_wvalid; + assign dram_axi_wready = ddr3_axi_wready; + assign dram_axi_bid = ddr3_axi_bid; + assign dram_axi_bresp = ddr3_axi_bresp; + assign dram_axi_bvalid = ddr3_axi_bvalid; + assign ddr3_axi_bready = dram_axi_bready; + assign ddr3_axi_arid = dram_axi_arid; + assign ddr3_axi_araddr = dram_axi_araddr; + assign ddr3_axi_arlen = dram_axi_arlen; + assign ddr3_axi_arsize = dram_axi_arsize; + assign ddr3_axi_arburst = dram_axi_arburst; + assign ddr3_axi_arlock = dram_axi_arlock; + assign ddr3_axi_arcache = dram_axi_arcache; + assign ddr3_axi_arprot = dram_axi_arprot; + assign ddr3_axi_arqos = dram_axi_arqos; + assign ddr3_axi_arvalid = dram_axi_arvalid; + assign dram_axi_arready = ddr3_axi_arready; + assign dram_axi_rid = ddr3_axi_rid; + assign dram_axi_rdata = ddr3_axi_rdata; + assign dram_axi_rresp = ddr3_axi_rresp; + assign dram_axi_rlast = ddr3_axi_rlast; + assign dram_axi_rvalid = ddr3_axi_rvalid; + assign ddr3_axi_rready = dram_axi_rready; + + end else if (NUM_PORTS == 2 && AXI_DWIDTH == 64) begin : gen_dual_port + assign dram_clk = clk200; + assign dram_rst = clk200_rst; + + axi_inter_2x64_128_bd axi_inter_2x64_128_bd_i ( + .M00_AXI_ACLK (ui_clk ), + .M00_AXI_ARESETN (~ui_rst ), + .M00_AXI_araddr (ddr3_axi_araddr ), + .M00_AXI_arburst (ddr3_axi_arburst ), + .M00_AXI_arcache (ddr3_axi_arcache ), + .M00_AXI_arid (ddr3_axi_arid ), + .M00_AXI_arlen (ddr3_axi_arlen ), + .M00_AXI_arlock (ddr3_axi_arlock ), + .M00_AXI_arprot (ddr3_axi_arprot ), + .M00_AXI_arqos (ddr3_axi_arqos ), + .M00_AXI_arready (ddr3_axi_arready ), + .M00_AXI_arregion( ), + .M00_AXI_arsize (ddr3_axi_arsize ), + .M00_AXI_arvalid (ddr3_axi_arvalid ), + .M00_AXI_awaddr (ddr3_axi_awaddr ), + .M00_AXI_awburst (ddr3_axi_awburst ), + .M00_AXI_awcache (ddr3_axi_awcache ), + .M00_AXI_awid (ddr3_axi_awid ), + .M00_AXI_awlen (ddr3_axi_awlen ), + .M00_AXI_awlock (ddr3_axi_awlock ), + .M00_AXI_awprot (ddr3_axi_awprot ), + .M00_AXI_awqos (ddr3_axi_awqos ), + .M00_AXI_awready (ddr3_axi_awready ), + .M00_AXI_awregion( ), + .M00_AXI_awsize (ddr3_axi_awsize ), + .M00_AXI_awvalid (ddr3_axi_awvalid ), + .M00_AXI_bid (ddr3_axi_bid ), + .M00_AXI_bready (ddr3_axi_bready ), + .M00_AXI_bresp (ddr3_axi_bresp ), + .M00_AXI_bvalid (ddr3_axi_bvalid ), + .M00_AXI_rdata (ddr3_axi_rdata ), + .M00_AXI_rid (ddr3_axi_rid ), + .M00_AXI_rlast (ddr3_axi_rlast ), + .M00_AXI_rready (ddr3_axi_rready ), + .M00_AXI_rresp (ddr3_axi_rresp ), + .M00_AXI_rvalid (ddr3_axi_rvalid ), + .M00_AXI_wdata (ddr3_axi_wdata ), + .M00_AXI_wlast (ddr3_axi_wlast ), + .M00_AXI_wready (ddr3_axi_wready ), + .M00_AXI_wstrb (ddr3_axi_wstrb ), + .M00_AXI_wvalid (ddr3_axi_wvalid ), + .S00_AXI_ACLK (dram_clk ), + .S00_AXI_ARESETN (~dram_rst ), + .S00_AXI_araddr (dram_axi_araddr [29*0 +: 29]), + .S00_AXI_arburst (dram_axi_arburst [ 2*0 +: 2]), + .S00_AXI_arcache (dram_axi_arcache [ 4*0 +: 4]), + .S00_AXI_arid (dram_axi_arid [ 1*0 +: 1]), + .S00_AXI_arlen (dram_axi_arlen [ 8*0 +: 8]), + .S00_AXI_arlock (dram_axi_arlock [ 1*0 +: 1]), + .S00_AXI_arprot (dram_axi_arprot [ 3*0 +: 3]), + .S00_AXI_arqos (dram_axi_arqos [ 4*0 +: 4]), + .S00_AXI_arready (dram_axi_arready [ 1*0 +: 1]), + .S00_AXI_arregion(dram_axi_arregion [ 4*0 +: 4]), + .S00_AXI_arsize (dram_axi_arsize [ 3*0 +: 3]), + .S00_AXI_arvalid (dram_axi_arvalid [ 1*0 +: 1]), + .S00_AXI_awaddr (dram_axi_awaddr [29*0 +: 29]), + .S00_AXI_awburst (dram_axi_awburst [ 2*0 +: 2]), + .S00_AXI_awcache (dram_axi_awcache [ 4*0 +: 4]), + .S00_AXI_awid (dram_axi_awid [ 1*0 +: 1]), + .S00_AXI_awlen (dram_axi_awlen [ 8*0 +: 8]), + .S00_AXI_awlock (dram_axi_awlock [ 1*0 +: 1]), + .S00_AXI_awprot (dram_axi_awprot [ 3*0 +: 3]), + .S00_AXI_awqos (dram_axi_awqos [ 4*0 +: 4]), + .S00_AXI_awready (dram_axi_awready [ 1*0 +: 1]), + .S00_AXI_awregion(dram_axi_awregion [ 4*0 +: 4]), + .S00_AXI_awsize (dram_axi_awsize [ 3*0 +: 3]), + .S00_AXI_awvalid (dram_axi_awvalid [ 1*0 +: 1]), + .S00_AXI_bid (dram_axi_bid [ 1*0 +: 1]), + .S00_AXI_bready (dram_axi_bready [ 1*0 +: 1]), + .S00_AXI_bresp (dram_axi_bresp [ 2*0 +: 2]), + .S00_AXI_bvalid (dram_axi_bvalid [ 1*0 +: 1]), + .S00_AXI_rdata (dram_axi_rdata [64*0 +: 64]), + .S00_AXI_rid (dram_axi_rid [ 1*0 +: 1]), + .S00_AXI_rlast (dram_axi_rlast [ 1*0 +: 1]), + .S00_AXI_rready (dram_axi_rready [ 1*0 +: 1]), + .S00_AXI_rresp (dram_axi_rresp [ 2*0 +: 2]), + .S00_AXI_rvalid (dram_axi_rvalid [ 1*0 +: 1]), + .S00_AXI_wdata (dram_axi_wdata [64*0 +: 64]), + .S00_AXI_wlast (dram_axi_wlast [ 1*0 +: 1]), + .S00_AXI_wready (dram_axi_wready [ 1*0 +: 1]), + .S00_AXI_wstrb (dram_axi_wstrb [ 8*0 +: 8]), + .S00_AXI_wvalid (dram_axi_wvalid [ 1*0 +: 1]), + .S01_AXI_ACLK (dram_clk ), + .S01_AXI_ARESETN (~dram_rst ), + .S01_AXI_araddr (dram_axi_araddr [29*1 +: 29]), + .S01_AXI_arburst (dram_axi_arburst [ 2*1 +: 2]), + .S01_AXI_arcache (dram_axi_arcache [ 4*1 +: 4]), + .S01_AXI_arid (dram_axi_arid [ 1*1 +: 1]), + .S01_AXI_arlen (dram_axi_arlen [ 8*1 +: 8]), + .S01_AXI_arlock (dram_axi_arlock [ 1*1 +: 1]), + .S01_AXI_arprot (dram_axi_arprot [ 3*1 +: 3]), + .S01_AXI_arqos (dram_axi_arqos [ 4*1 +: 4]), + .S01_AXI_arready (dram_axi_arready [ 1*1 +: 1]), + .S01_AXI_arregion(dram_axi_arregion [ 4*1 +: 4]), + .S01_AXI_arsize (dram_axi_arsize [ 3*1 +: 3]), + .S01_AXI_arvalid (dram_axi_arvalid [ 1*1 +: 1]), + .S01_AXI_awaddr (dram_axi_awaddr [29*1 +: 29]), + .S01_AXI_awburst (dram_axi_awburst [ 2*1 +: 2]), + .S01_AXI_awcache (dram_axi_awcache [ 4*1 +: 4]), + .S01_AXI_awid (dram_axi_awid [ 1*1 +: 1]), + .S01_AXI_awlen (dram_axi_awlen [ 8*1 +: 8]), + .S01_AXI_awlock (dram_axi_awlock [ 1*1 +: 1]), + .S01_AXI_awprot (dram_axi_awprot [ 3*1 +: 3]), + .S01_AXI_awqos (dram_axi_awqos [ 4*1 +: 4]), + .S01_AXI_awready (dram_axi_awready [ 1*1 +: 1]), + .S01_AXI_awregion(dram_axi_awregion [ 4*1 +: 4]), + .S01_AXI_awsize (dram_axi_awsize [ 3*1 +: 3]), + .S01_AXI_awvalid (dram_axi_awvalid [ 1*1 +: 1]), + .S01_AXI_bid (dram_axi_bid [ 1*1 +: 1]), + .S01_AXI_bready (dram_axi_bready [ 1*1 +: 1]), + .S01_AXI_bresp (dram_axi_bresp [ 2*1 +: 2]), + .S01_AXI_bvalid (dram_axi_bvalid [ 1*1 +: 1]), + .S01_AXI_rdata (dram_axi_rdata [64*1 +: 64]), + .S01_AXI_rid (dram_axi_rid [ 1*1 +: 1]), + .S01_AXI_rlast (dram_axi_rlast [ 1*1 +: 1]), + .S01_AXI_rready (dram_axi_rready [ 1*1 +: 1]), + .S01_AXI_rresp (dram_axi_rresp [ 2*1 +: 2]), + .S01_AXI_rvalid (dram_axi_rvalid [ 1*1 +: 1]), + .S01_AXI_wdata (dram_axi_wdata [64*1 +: 64]), + .S01_AXI_wlast (dram_axi_wlast [ 1*1 +: 1]), + .S01_AXI_wready (dram_axi_wready [ 1*1 +: 1]), + .S01_AXI_wstrb (dram_axi_wstrb [ 8*1 +: 8]), + .S01_AXI_wvalid (dram_axi_wvalid [ 1*1 +: 1]) + ); + end + + //--------------------------------------------------------------------------- + // DDR3 Memory Controller + //--------------------------------------------------------------------------- + + ddr3_16bit ddr3_16bit_i ( + // Memory interface ports + .ddr3_addr (ddr3_addr ), // output [14:0] ddr3_addr + .ddr3_ba (ddr3_ba ), // output [2:0] ddr3_ba + .ddr3_cas_n (ddr3_cas_n ), // output ddr3_cas_n + .ddr3_ck_n (ddr3_ck_n ), // output [0:0] ddr3_ck_n + .ddr3_ck_p (ddr3_ck_p ), // output [0:0] ddr3_ck_p + .ddr3_cke (ddr3_cke ), // output [0:0] ddr3_cke + .ddr3_ras_n (ddr3_ras_n ), // output ddr3_ras_n + .ddr3_reset_n (ddr3_reset_n ), // output ddr3_reset_n + .ddr3_we_n (ddr3_we_n ), // output ddr3_we_n + .ddr3_dq (ddr3_dq ), // inout [15:0] ddr3_dq + .ddr3_dqs_n (ddr3_dqs_n ), // inout [1:0] ddr3_dqs_n + .ddr3_dqs_p (ddr3_dqs_p ), // inout [1:0] ddr3_dqs_p + .ddr3_dm (ddr3_dm ), // output [1:0] ddr3_dm + .ddr3_odt (ddr3_odt ), // output [0:0] ddr3_odt + // Application interface ports + .init_calib_complete( ), // output init_calib_complete + .device_temp ( ), // output [11:0] device_temp; + .ui_clk (ui_clk ), // output ui_clk + .ui_clk_sync_rst (ui_rst ), // output ui_clk_sync_rst + .mmcm_locked ( ), // output mmcm_locked + .app_sr_req (1'b0 ), // input app_sr_req + .app_ref_req (1'b0 ), // input app_ref_req + .app_zq_req (1'b0 ), // input app_zq_req + .app_sr_active ( ), // output app_sr_active + .app_ref_ack ( ), // output app_ref_ack + .app_zq_ack ( ), // output app_zq_ack + // AXI Interface Reset + .aresetn (~ui_rst ), // input aresetn + // Slave Interface Write Address Ports + .s_axi_awid (ddr3_axi_awid ), // input [11:0] s_axi_awid + .s_axi_awaddr (ddr3_axi_awaddr ), // input [28:0] s_axi_awaddr + .s_axi_awlen (ddr3_axi_awlen ), // input [7:0] s_axi_awlen + .s_axi_awsize (ddr3_axi_awsize ), // input [2:0] s_axi_awsize + .s_axi_awburst (ddr3_axi_awburst), // input [1:0] s_axi_awburst + .s_axi_awlock (ddr3_axi_awlock ), // input [0:0] s_axi_awlock + .s_axi_awcache (ddr3_axi_awcache), // input [3:0] s_axi_awcache + .s_axi_awprot (ddr3_axi_awprot ), // input [2:0] s_axi_awprot + .s_axi_awqos (ddr3_axi_awqos ), // input [3:0] s_axi_awqos + .s_axi_awvalid (ddr3_axi_awvalid), // input s_axi_awvalid + .s_axi_awready (ddr3_axi_awready), // output s_axi_awready + // Slave Interface Write Data Ports + .s_axi_wdata (ddr3_axi_wdata ), // input [127:0] s_axi_wdata + .s_axi_wstrb (ddr3_axi_wstrb ), // input [15:0] s_axi_wstrb + .s_axi_wlast (ddr3_axi_wlast ), // input s_axi_wlast + .s_axi_wvalid (ddr3_axi_wvalid ), // input s_axi_wvalid + .s_axi_wready (ddr3_axi_wready ), // output s_axi_wready + // Slave Interface Write Response Ports + .s_axi_bid (ddr3_axi_bid ), // output [11:0] s_axi_bid + .s_axi_bresp (ddr3_axi_bresp ), // output [1:0] s_axi_bresp + .s_axi_bvalid (ddr3_axi_bvalid ), // output s_axi_bvalid + .s_axi_bready (ddr3_axi_bready ), // input s_axi_bready + // Slave Interface Read Address Ports + .s_axi_arid (ddr3_axi_arid ), // input [11:0] s_axi_arid + .s_axi_araddr (ddr3_axi_araddr ), // input [28:0] s_axi_araddr + .s_axi_arlen (ddr3_axi_arlen ), // input [7:0] s_axi_arlen + .s_axi_arsize (ddr3_axi_arsize ), // input [2:0] s_axi_arsize + .s_axi_arburst (ddr3_axi_arburst), // input [1:0] s_axi_arburst + .s_axi_arlock (ddr3_axi_arlock ), // input [0:0] s_axi_arlock + .s_axi_arcache (ddr3_axi_arcache), // input [3:0] s_axi_arcache + .s_axi_arprot (ddr3_axi_arprot ), // input [2:0] s_axi_arprot + .s_axi_arqos (ddr3_axi_arqos ), // input [3:0] s_axi_arqos + .s_axi_arvalid (ddr3_axi_arvalid), // input s_axi_arvalid + .s_axi_arready (ddr3_axi_arready), // output s_axi_arready + // Slave Interface Read Data Ports + .s_axi_rid (ddr3_axi_rid ), // output [11:0] s_axi_rid + .s_axi_rdata (ddr3_axi_rdata ), // output [127:0] s_axi_rdata + .s_axi_rresp (ddr3_axi_rresp ), // output [1:0] s_axi_rresp + .s_axi_rlast (ddr3_axi_rlast ), // output s_axi_rlast + .s_axi_rvalid (ddr3_axi_rvalid ), // output s_axi_rvalid + .s_axi_rready (ddr3_axi_rready ), // input s_axi_rready + // System Clock Ports + .sys_clk_i (ddr3_sys_clk ), // input sys_clk_i + // Reference Clock Ports + .clk_ref_i (clk200 ), + .sys_rst (sys_rst ) // input sys_rst + ); + +endmodule diff --git a/top/e31x/ip/Makefile.inc b/top/e31x/ip/Makefile.inc index 76bec9c..f2ddd05 100644 --- a/top/e31x/ip/Makefile.inc +++ b/top/e31x/ip/Makefile.inc @@ -16,10 +16,11 @@ include $(IP_DIR)/fifo_short_2clk/Makefile.inc #include $(IP_DIR)/axi4_to_axi3_protocol_converter_32/Makefile.inc #include $(IP_DIR)/axi4_to_axi3_protocol_converter_64/Makefile.inc include $(IP_DIR)/e31x_ps_bd/Makefile.inc -include $(IP_DIR)/mig_7series_0/Makefile.inc +include $(IP_DIR)/ddr3_16bit/Makefile.inc +include $(IP_DIR)/axi_inter_2x64_128_bd/Makefile.inc BD_SRCS = \ -$(IP_AXI_INTERCON_4X64_256_BD_SRCS) \ +$(IP_AXI_INTER_2X64_128_BD_SRCS) \ $(IP_E31X_PS_BD_SRCS) IP_XCI_SRCS = \ @@ -36,7 +37,7 @@ $(IP_FIFO_4K_2CLK_SRCS) \ #$(IP_MISC_CLOCK_GEN_SRCS) \ IP_DRAM_XCI_SRCS = \ -$(IP_DDR3_32BIT_SRCS) +$(IP_DDR3_16BIT_SRCS) ## Currently unused ## $(IP_INPUT_SAMPLE_FIFO_SRCS) \ @@ -55,7 +56,7 @@ $(IP_MIG_7SERIES_0_OUTS) \ #$(IP_AXIS_FIFO_TO_AXI4LITE_OUTS) \ BD_OUTPUTS = \ -$(IP_AXI_INTERCON_4X64_256_BD_OUTS) \ +$(IP_AXI_INTER_2X64_128_BD_OUTS) \ $(IP_E31X_PS_BD_OUTS) # Currently unused diff --git a/top/e31x/ip/axi_inter_2x64_128_bd/Makefile.inc b/top/e31x/ip/axi_inter_2x64_128_bd/Makefile.inc new file mode 100644 index 0000000..bc8038e --- /dev/null +++ b/top/e31x/ip/axi_inter_2x64_128_bd/Makefile.inc @@ -0,0 +1,26 @@ +# +# Copyright 2022 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +IP_AXI_INTER_2X64_128_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_inter_2x64_128_bd/, \ +axi_inter_2x64_128_bd.tcl \ +) + +IP_AXI_INTER_2X64_128_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_2x64_128_bd/, \ +axi_inter_2x64_128_bd.tcl \ +) + +IP_AXI_INTER_2X64_128_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_2x64_128_bd/, \ +axi_inter_2x64_128_bd/axi_inter_2x64_128_bd.bd \ +) + +BD_AXI_INTER_2X64_128_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_inter_2x64_128_bd/, \ +axi_inter_2x64_128_bd.bd.out \ +axi_inter_2x64_128_bd/axi_inter_2x64_128_bd_ooc.xdc \ +axi_inter_2x64_128_bd/synth/axi_inter_2x64_128_bd.v \ +) + +$(IP_AXI_INTER_2X64_128_BD_SRCS) $(BD_AXI_INTER_2X64_128_BD_OUTS) $(IP_AXI_INTER_2X64_128_BDTCL_SRCS): $(IP_AXI_INTER_2X64_128_ORIG_SRCS) + $(call BUILD_VIVADO_BDTCL,axi_inter_2x64_128_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi) diff --git a/top/e31x/ip/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd.tcl b/top/e31x/ip/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd.tcl new file mode 100644 index 0000000..e0eb550 --- /dev/null +++ b/top/e31x/ip/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd.tcl @@ -0,0 +1,707 @@ + +################################################################ +# This is a generated script based on design: axi_inter_2x64_128_bd +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2019.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source axi_inter_2x64_128_bd_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xc7z020clg484-3 +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name axi_inter_2x64_128_bd + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:axi_dwidth_converter:2.1\ +xilinx.com:ip:axi_crossbar:2.1\ +" + + set list_ips_missing "" + common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +if { $bCheckIPsPassed != 1 } { + common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set M00_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {29} \ + CONFIG.CLK_DOMAIN {axi_inter_2x64_128_bd_M00_ACLK} \ + CONFIG.DATA_WIDTH {128} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.PROTOCOL {AXI4} \ + ] $M00_AXI + + set S00_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {29} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.CLK_DOMAIN {axi_inter_2x64_128_bd_S00_ACLK} \ + CONFIG.DATA_WIDTH {64} \ + CONFIG.FREQ_HZ {200000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {1} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {1} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $S00_AXI + + set S01_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S01_AXI ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {29} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.CLK_DOMAIN {axi_inter_2x64_128_bd_S01_ACLK} \ + CONFIG.DATA_WIDTH {64} \ + CONFIG.FREQ_HZ {200000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {1} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {1} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $S01_AXI + + + # Create ports + set M00_AXI_ACLK [ create_bd_port -dir I -type clk M00_AXI_ACLK ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M00_AXI} \ + CONFIG.ASSOCIATED_RESET {M00_AXI_ARESETN} \ + CONFIG.CLK_DOMAIN {axi_inter_2x64_128_bd_M00_ACLK} \ + ] $M00_AXI_ACLK + set M00_AXI_ARESETN [ create_bd_port -dir I -type rst M00_AXI_ARESETN ] + set S00_AXI_ACLK [ create_bd_port -dir I -type clk S00_AXI_ACLK ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S00_AXI} \ + CONFIG.ASSOCIATED_RESET {S00_AXI_ARESETN} \ + CONFIG.CLK_DOMAIN {axi_inter_2x64_128_bd_S00_ACLK} \ + CONFIG.FREQ_HZ {200000000} \ + ] $S00_AXI_ACLK + set S00_AXI_ARESETN [ create_bd_port -dir I -type rst S00_AXI_ARESETN ] + set S01_AXI_ACLK [ create_bd_port -dir I -type clk S01_AXI_ACLK ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S01_AXI} \ + CONFIG.ASSOCIATED_RESET {S01_AXI_ARESETN} \ + CONFIG.CLK_DOMAIN {axi_inter_2x64_128_bd_S01_ACLK} \ + CONFIG.FREQ_HZ {200000000} \ + ] $S01_AXI_ACLK + set S01_AXI_ARESETN [ create_bd_port -dir I -type rst S01_AXI_ARESETN ] + + # Create instance: s00_width_conv, and set properties + set s00_width_conv [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 s00_width_conv ] + set_property -dict [ list \ + CONFIG.ACLK_ASYNC {1} \ + CONFIG.FIFO_MODE {2} \ + CONFIG.MI_DATA_WIDTH {128} \ + CONFIG.SI_DATA_WIDTH {64} \ + CONFIG.SYNCHRONIZATION_STAGES {2} \ + ] $s00_width_conv + + # Create instance: s01_width_conv, and set properties + set s01_width_conv [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 s01_width_conv ] + set_property -dict [ list \ + CONFIG.ACLK_ASYNC {1} \ + CONFIG.FIFO_MODE {2} \ + CONFIG.MI_DATA_WIDTH {128} \ + CONFIG.SI_DATA_WIDTH {64} \ + CONFIG.SYNCHRONIZATION_STAGES {2} \ + ] $s01_width_conv + + # Create instance: xbar, and set properties + set xbar [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 xbar ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {128} \ + CONFIG.ID_WIDTH {1} \ + CONFIG.M00_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_READ_ISSUING {8} \ + CONFIG.M00_WRITE_ISSUING {8} \ + CONFIG.M01_A00_ADDR_WIDTH {0} \ + CONFIG.M01_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_READ_ISSUING {8} \ + CONFIG.M01_WRITE_ISSUING {8} \ + CONFIG.M02_A00_ADDR_WIDTH {0} \ + CONFIG.M02_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_READ_ISSUING {8} \ + CONFIG.M02_WRITE_ISSUING {8} \ + CONFIG.M03_A00_ADDR_WIDTH {0} \ + CONFIG.M03_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_READ_ISSUING {8} \ + CONFIG.M03_WRITE_ISSUING {8} \ + CONFIG.M04_A00_ADDR_WIDTH {0} \ + CONFIG.M04_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_READ_ISSUING {8} \ + CONFIG.M04_WRITE_ISSUING {8} \ + CONFIG.M05_A00_ADDR_WIDTH {0} \ + CONFIG.M05_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_READ_ISSUING {8} \ + CONFIG.M05_WRITE_ISSUING {8} \ + CONFIG.M06_A00_ADDR_WIDTH {0} \ + CONFIG.M06_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_READ_ISSUING {8} \ + CONFIG.M06_WRITE_ISSUING {8} \ + CONFIG.M07_A00_ADDR_WIDTH {0} \ + CONFIG.M07_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_READ_ISSUING {8} \ + CONFIG.M07_WRITE_ISSUING {8} \ + CONFIG.M08_A00_ADDR_WIDTH {0} \ + CONFIG.M08_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_READ_ISSUING {8} \ + CONFIG.M08_WRITE_ISSUING {8} \ + CONFIG.M09_A00_ADDR_WIDTH {0} \ + CONFIG.M09_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_READ_ISSUING {8} \ + CONFIG.M09_WRITE_ISSUING {8} \ + CONFIG.M10_A00_ADDR_WIDTH {0} \ + CONFIG.M10_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_READ_ISSUING {8} \ + CONFIG.M10_WRITE_ISSUING {8} \ + CONFIG.M11_A00_ADDR_WIDTH {0} \ + CONFIG.M11_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_READ_ISSUING {8} \ + CONFIG.M11_WRITE_ISSUING {8} \ + CONFIG.M12_A00_ADDR_WIDTH {0} \ + CONFIG.M12_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_READ_ISSUING {8} \ + CONFIG.M12_WRITE_ISSUING {8} \ + CONFIG.M13_A00_ADDR_WIDTH {0} \ + CONFIG.M13_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_READ_ISSUING {8} \ + CONFIG.M13_WRITE_ISSUING {8} \ + CONFIG.M14_A00_ADDR_WIDTH {0} \ + CONFIG.M14_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_READ_ISSUING {8} \ + CONFIG.M14_WRITE_ISSUING {8} \ + CONFIG.M15_A00_ADDR_WIDTH {0} \ + CONFIG.M15_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_READ_ISSUING {8} \ + CONFIG.M15_WRITE_ISSUING {8} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {2} \ + CONFIG.S00_READ_ACCEPTANCE {4} \ + CONFIG.S00_WRITE_ACCEPTANCE {4} \ + CONFIG.S01_BASE_ID {0x00000001} \ + CONFIG.S01_READ_ACCEPTANCE {4} \ + CONFIG.S01_WRITE_ACCEPTANCE {4} \ + CONFIG.S02_BASE_ID {0x00000002} \ + CONFIG.S02_READ_ACCEPTANCE {4} \ + CONFIG.S02_WRITE_ACCEPTANCE {4} \ + CONFIG.S03_BASE_ID {0x00000003} \ + CONFIG.S03_READ_ACCEPTANCE {4} \ + CONFIG.S03_WRITE_ACCEPTANCE {4} \ + CONFIG.S04_BASE_ID {0x00000004} \ + CONFIG.S04_READ_ACCEPTANCE {4} \ + CONFIG.S04_WRITE_ACCEPTANCE {4} \ + CONFIG.S05_BASE_ID {0x00000005} \ + CONFIG.S05_READ_ACCEPTANCE {4} \ + CONFIG.S05_WRITE_ACCEPTANCE {4} \ + CONFIG.S06_BASE_ID {0x00000006} \ + CONFIG.S06_READ_ACCEPTANCE {4} \ + CONFIG.S06_WRITE_ACCEPTANCE {4} \ + CONFIG.S07_BASE_ID {0x00000007} \ + CONFIG.S07_READ_ACCEPTANCE {4} \ + CONFIG.S07_WRITE_ACCEPTANCE {4} \ + CONFIG.S08_BASE_ID {0x00000008} \ + CONFIG.S08_READ_ACCEPTANCE {4} \ + CONFIG.S08_WRITE_ACCEPTANCE {4} \ + CONFIG.S09_BASE_ID {0x00000009} \ + CONFIG.S09_READ_ACCEPTANCE {4} \ + CONFIG.S09_WRITE_ACCEPTANCE {4} \ + CONFIG.S10_BASE_ID {0x0000000a} \ + CONFIG.S10_READ_ACCEPTANCE {4} \ + CONFIG.S10_WRITE_ACCEPTANCE {4} \ + CONFIG.S11_BASE_ID {0x0000000b} \ + CONFIG.S11_READ_ACCEPTANCE {4} \ + CONFIG.S11_WRITE_ACCEPTANCE {4} \ + CONFIG.S12_BASE_ID {0x0000000c} \ + CONFIG.S12_READ_ACCEPTANCE {4} \ + CONFIG.S12_WRITE_ACCEPTANCE {4} \ + CONFIG.S13_BASE_ID {0x0000000d} \ + CONFIG.S13_READ_ACCEPTANCE {4} \ + CONFIG.S13_WRITE_ACCEPTANCE {4} \ + CONFIG.S14_BASE_ID {0x0000000e} \ + CONFIG.S14_READ_ACCEPTANCE {4} \ + CONFIG.S14_WRITE_ACCEPTANCE {4} \ + CONFIG.S15_BASE_ID {0x0000000f} \ + CONFIG.S15_READ_ACCEPTANCE {4} \ + CONFIG.S15_WRITE_ACCEPTANCE {4} \ + CONFIG.STRATEGY {2} \ + ] $xbar + + # Create interface connections + connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_ports S00_AXI] [get_bd_intf_pins s00_width_conv/S_AXI] + connect_bd_intf_net -intf_net S01_AXI_1 [get_bd_intf_ports S01_AXI] [get_bd_intf_pins s01_width_conv/S_AXI] + connect_bd_intf_net -intf_net s00_width_conv_M_AXI [get_bd_intf_pins s00_width_conv/M_AXI] [get_bd_intf_pins xbar/S00_AXI] + connect_bd_intf_net -intf_net s01_width_conv_M_AXI [get_bd_intf_pins s01_width_conv/M_AXI] [get_bd_intf_pins xbar/S01_AXI] + connect_bd_intf_net -intf_net xbar_M00_AXI [get_bd_intf_ports M00_AXI] [get_bd_intf_pins xbar/M00_AXI] + + # Create port connections + connect_bd_net -net M00_AXI_ACLK_1 [get_bd_ports M00_AXI_ACLK] [get_bd_pins s00_width_conv/m_axi_aclk] [get_bd_pins s01_width_conv/m_axi_aclk] [get_bd_pins xbar/aclk] + connect_bd_net -net M00_AXI_ARESETN_1 [get_bd_ports M00_AXI_ARESETN] [get_bd_pins s00_width_conv/m_axi_aresetn] [get_bd_pins s01_width_conv/m_axi_aresetn] [get_bd_pins xbar/aresetn] + connect_bd_net -net S00_AXI_ACLK_1 [get_bd_ports S00_AXI_ACLK] [get_bd_pins s00_width_conv/s_axi_aclk] + connect_bd_net -net S00_AXI_ARESETN_1 [get_bd_ports S00_AXI_ARESETN] [get_bd_pins s00_width_conv/s_axi_aresetn] + connect_bd_net -net S01_AXI_ACLK_1 [get_bd_ports S01_AXI_ACLK] [get_bd_pins s01_width_conv/s_axi_aclk] + connect_bd_net -net S01_AXI_ARESETN_1 [get_bd_ports S01_AXI_ARESETN] [get_bd_pins s01_width_conv/s_axi_aresetn] + + # Create address segments + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces S00_AXI] [get_bd_addr_segs M00_AXI/Reg] SEG_M00_AXI_Reg + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces S01_AXI] [get_bd_addr_segs M00_AXI/Reg] SEG_M00_AXI_Reg + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/top/e31x/ip/ddr3_16bit/Makefile.inc b/top/e31x/ip/ddr3_16bit/Makefile.inc new file mode 100644 index 0000000..66187c6 --- /dev/null +++ b/top/e31x/ip/ddr3_16bit/Makefile.inc @@ -0,0 +1,32 @@ +# +# Copyright 2022 Ettus Research, a National Instruments Brand +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_DDR3_16BIT_SRCS = $(IP_BUILD_DIR)/ddr3_16bit/ddr3_16bit.xci + +IP_DDR3_16BIT_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_16bit/, \ +ddr3_16bit.xci.out \ +ddr3_16bit/user_design/rtl/ddr3_16bit.v \ +ddr3_16bit/user_design/rtl/ddr3_16bit_mig.v \ +) + +IP_MIG_7SERIES_TG_SRCS = $(addprefix $(IP_BUILD_DIR)/ddr3_16bit/, \ +ddr3_16bit/example_design/rtl/example_top.v \ +ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_tg.v \ +ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_wrapper.v \ +ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_cmd_prbs_gen_axi.v \ +ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_data_gen_chk.v \ +ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_tg.v \ +) + +IP_DDR3_16BIT_SIM_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_16bit/, \ +ddr3_16bit/example_design/sim/ddr3_model.sv \ +ddr3_16bit/example_design/sim/ddr3_model_parameters.vh \ +) + +$(IP_DDR3_16BIT_SRCS) $(IP_DDR3_16BIT_OUTS) : $(IP_DIR)/ddr3_16bit/ddr3_16bit.xci $(IP_DIR)/ddr3_16bit/mig_*.prj + cp -f $(IP_DIR)/ddr3_16bit/mig_$(subst /,,$(PART_ID)).prj $(IP_DIR)/ddr3_16bit/mig_a.prj # Note: This won't allow parallel IP builds + $(call BUILD_VIVADO_IP,ddr3_16bit,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) + rm -f $(IP_DIR)/ddr3_16bit/mig_a.prj diff --git a/top/e31x/ip/mig_7series_0/mig_7series_0.xci b/top/e31x/ip/ddr3_16bit/ddr3_16bit.xci similarity index 99% rename from top/e31x/ip/mig_7series_0/mig_7series_0.xci rename to top/e31x/ip/ddr3_16bit/ddr3_16bit.xci index 5b99fe2..7d467a8 100644 --- a/top/e31x/ip/mig_7series_0/mig_7series_0.xci +++ b/top/e31x/ip/ddr3_16bit/ddr3_16bit.xci @@ -6,7 +6,7 @@ 1.0 - mig_7series_0 + ddr3_16bit 0 @@ -2300,7 +2300,7 @@ FALSE 1 Custom - mig_7series_0 + ddr3_16bit Custom Custom mig_a.prj @@ -2646,3 +2646,4 @@ + diff --git a/top/e31x/ip/mig_7series_0/mig_xc7z020clg484-1.prj b/top/e31x/ip/ddr3_16bit/mig_xc7z020clg484-1.prj similarity index 99% rename from top/e31x/ip/mig_7series_0/mig_xc7z020clg484-1.prj rename to top/e31x/ip/ddr3_16bit/mig_xc7z020clg484-1.prj index f8c6732..74d75d1 100644 --- a/top/e31x/ip/mig_7series_0/mig_xc7z020clg484-1.prj +++ b/top/e31x/ip/ddr3_16bit/mig_xc7z020clg484-1.prj @@ -1,7 +1,7 @@ - mig_7series_0 + ddr3_16bit 1 1 OFF diff --git a/top/e31x/ip/mig_7series_0/mig_xc7z020clg484-3.prj b/top/e31x/ip/ddr3_16bit/mig_xc7z020clg484-3.prj similarity index 99% rename from top/e31x/ip/mig_7series_0/mig_xc7z020clg484-3.prj rename to top/e31x/ip/ddr3_16bit/mig_xc7z020clg484-3.prj index 635ea14..9494d07 100644 --- a/top/e31x/ip/mig_7series_0/mig_xc7z020clg484-3.prj +++ b/top/e31x/ip/ddr3_16bit/mig_xc7z020clg484-3.prj @@ -1,7 +1,7 @@ - mig_7series_0 + ddr3_16bit 1 1 OFF diff --git a/top/e31x/ip/mig_7series_0/Makefile.inc b/top/e31x/ip/mig_7series_0/Makefile.inc deleted file mode 100644 index 87dd395..0000000 --- a/top/e31x/ip/mig_7series_0/Makefile.inc +++ /dev/null @@ -1,32 +0,0 @@ -# -# Copyright 2015 Ettus Research -# - -include $(TOOLS_DIR)/make/viv_ip_builder.mak - -IP_MIG_7SERIES_0_SRCS = $(IP_BUILD_DIR)/mig_7series_0/mig_7series_0.xci - -IP_MIG_7SERIES_0_OUTS = $(addprefix $(IP_BUILD_DIR)/mig_7series_0/, \ -mig_7series_0.xci.out \ -mig_7series_0/user_design/rtl/mig_7series_0.v \ -mig_7series_0/user_design/rtl/mig_7series_0_mig.v \ -) - -IP_MIG_7SERIES_TG_SRCS = $(addprefix $(IP_BUILD_DIR)/mig_7series_0/, \ -mig_7series_0/example_design/rtl/example_top.v \ -mig_7series_0/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_tg.v \ -mig_7series_0/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_wrapper.v \ -mig_7series_0/example_design/rtl/traffic_gen/mig_7series_v4_2_cmd_prbs_gen_axi.v \ -mig_7series_0/example_design/rtl/traffic_gen/mig_7series_v4_2_data_gen_chk.v \ -mig_7series_0/example_design/rtl/traffic_gen/mig_7series_v4_2_tg.v \ -) - -IP_MIG_7SERIES_0_SIM_OUTS = $(addprefix $(IP_BUILD_DIR)/mig_7series_0/, \ -mig_7series_0/example_design/sim/ddr3_model.sv \ -mig_7series_0/example_design/sim/ddr3_model_parameters.vh \ -) - -$(IP_MIG_7SERIES_0_SRCS) $(IP_MIG_7SERIES_0_OUTS) : $(IP_DIR)/mig_7series_0/mig_7series_0.xci $(IP_DIR)/mig_7series_0/mig_*.prj - cp -f $(IP_DIR)/mig_7series_0/mig_$(subst /,,$(PART_ID)).prj $(IP_DIR)/mig_7series_0/mig_a.prj # Note: This won't allow parallel IP builds - $(call BUILD_VIVADO_IP,mig_7series_0,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) - rm -f $(IP_DIR)/mig_7series_0/mig_a.prj