fpga: e31x: Add DRAM support

This adds DRAM support to E31x devices. Due to the size of the DDR3
memory controller, it is not enabled by default. You can include the
memory controller IP in the build by adding the DRAM environment
variable to your build. For example:

DRAM=1 make E310_SG3


Original-commit: 788fef11ef890c6dcee3be495fc381bcf2990d3b

top/e31x/e310_rfnoc_image_core.v

@@ -1,5 +1,5 @@
 //
-// Copyright 2021 Ettus Research, A National Instruments Brand
+// Copyright 2022 Ettus Research, A National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
@@ -13,7 +13,7 @@
 //   This file was automatically generated by the RFNoC image builder tool.
 //   Re-running that tool will overwrite this file!
 //
-// File generated on: 2021-05-03T08:51:11.395850
+// File generated on: 2022-02-07T19:18:27.980096
 // Source: e310_rfnoc_image_core.yml
 // Source SHA256: 7fef622f1ae280dd7573abd823c7a6bbecf51921a74cea948e6bfb9f8f65e2cc
 //
@@ -32,6 +32,7 @@ module rfnoc_image_core #(
   input  wire         ctrl_aclk,
   input  wire         core_arst,
   input  wire         radio_clk,
+  input  wire         dram_clk,
   // Basic
   input  wire [  15:0] device_id,
 
@@ -57,6 +58,52 @@ module rfnoc_image_core #(
   output wire [  63:0] radio_tx_data,
   input  wire [   1:0] radio_tx_stb,
   output wire [   1:0] radio_tx_running,
+  // dram
+  input  wire [   0:0] axi_rst,
+  output wire [   3:0] m_axi_awid,
+  output wire [ 127:0] m_axi_awaddr,
+  output wire [  31:0] m_axi_awlen,
+  output wire [  11:0] m_axi_awsize,
+  output wire [   7:0] m_axi_awburst,
+  output wire [   3:0] m_axi_awlock,
+  output wire [  15:0] m_axi_awcache,
+  output wire [  11:0] m_axi_awprot,
+  output wire [  15:0] m_axi_awqos,
+  output wire [  15:0] m_axi_awregion,
+  output wire [   3:0] m_axi_awuser,
+  output wire [   3:0] m_axi_awvalid,
+  input  wire [   3:0] m_axi_awready,
+  output wire [ 255:0] m_axi_wdata,
+  output wire [  31:0] m_axi_wstrb,
+  output wire [   3:0] m_axi_wlast,
+  output wire [   3:0] m_axi_wuser,
+  output wire [   3:0] m_axi_wvalid,
+  input  wire [   3:0] m_axi_wready,
+  input  wire [   3:0] m_axi_bid,
+  input  wire [   7:0] m_axi_bresp,
+  input  wire [   3:0] m_axi_buser,
+  input  wire [   3:0] m_axi_bvalid,
+  output wire [   3:0] m_axi_bready,
+  output wire [   3:0] m_axi_arid,
+  output wire [ 127:0] m_axi_araddr,
+  output wire [  31:0] m_axi_arlen,
+  output wire [  11:0] m_axi_arsize,
+  output wire [   7:0] m_axi_arburst,
+  output wire [   3:0] m_axi_arlock,
+  output wire [  15:0] m_axi_arcache,
+  output wire [  11:0] m_axi_arprot,
+  output wire [  15:0] m_axi_arqos,
+  output wire [  15:0] m_axi_arregion,
+  output wire [   3:0] m_axi_aruser,
+  output wire [   3:0] m_axi_arvalid,
+  input  wire [   3:0] m_axi_arready,
+  input  wire [   3:0] m_axi_rid,
+  input  wire [ 255:0] m_axi_rdata,
+  input  wire [   7:0] m_axi_rresp,
+  input  wire [   3:0] m_axi_rlast,
+  input  wire [   3:0] m_axi_ruser,
+  input  wire [   3:0] m_axi_rvalid,
+  output wire [   3:0] m_axi_rready,
 
   // Transport Adapters ///////////////