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fpga: e31x: Add DRAM support

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This adds DRAM support to E31x devices. Due to the size of the DDR3
memory controller, it is not enabled by default. You can include the
memory controller IP in the build by adding the DRAM environment
variable to your build. For example:

DRAM=1 make E310_SG3


Original-commit: 788fef11ef890c6dcee3be495fc381bcf2990d3b
This commit is contained in:
Wade Fife
2022-02-10 18:13:44 -07:00
parent 83ad8e36ba
commit c322899053
15 changed files with 1499 additions and 99 deletions
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top/e31x/Makefile.e31x.inc
+9 -2
View File
@@ -32,11 +32,13 @@ include $(LIB_DIR)/dsp/Makefile.srcs
include $(LIB_DIR)/io_cap_gen/Makefile.srcs
include $(LIB_DIR)/rfnoc/Makefile.srcs
# For the sake of convenience, we include the Makefile.srcs for the DDC, DUC,
# and the radio. Any other block needs to use the RFNOC_OOT_MAKEFILE_SRCS
# variable (see below).
# radio, replay and FIFO blocks. Any other block needs to use the
# RFNOC_OOT_MAKEFILE_SRCS variable (see below).
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_replay/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs
# If out-of-tree modules want to be compiled into this image, then they need to
# pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files.
# Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual
@@ -58,6 +60,7 @@ spi_slave.v
ifneq (IDLE,$(findstring IDLE, $(EXTRA_DEFS)))
TOP_SRCS += e31x.v
TOP_SRCS += e31x_core.v
TOP_SRCS += e31x_dram.v
TOP_SRCS += e310_io.v
TOP_SRCS += $(EDGE_FILE) $(IMAGE_CORE)
MB_XDC = \
@@ -69,6 +72,8 @@ MB_XDC = \
e31x_idle_pins.xdc
endif
DRAM_SRCS = $(IP_DRAM_XCI_SRCS)
# The XDC files must be read in a specific order, motherboard first and then daughterboard.
# Outside of that, all the other sources can be read in any order desired.
DESIGN_SRCS = \
@@ -96,6 +101,8 @@ $(CAP_GEN_GENERIC_SRCS) \
$(RFNOC_OOT_SRCS)\
$(RFNOC_FRAMEWORK_SRCS) $(RFNOC_BLOCK_NULL_SRC_SINK_SRCS) \
$(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) $(RFNOC_BLOCK_RADIO_SRCS) \
$(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \
$(RFNOC_BLOCK_REPLAY_SRCS) \
$(RFNOC_BLOCK_EXAMPLE_SRCS) \
$(abspath $(MB_XDC))