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mpm/fpga: x4xx: Major updates in preparation for future devices

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FPGA:
- Split up MB registers that control daughterboard specific settings so
  that daughterboards 0 and 1 could have different setings, in
  preparation for future devices that require different settings.
  This requires a compat number bump to 8.0.
- Add registers for additional RFDC information, including the
  block/tile mapping of the individual channels, and information about
  resampling capabilities
- Identify sections of code that would be specific to X410/ZBX and move
  them to their own headers, so it's trivial to add device-specific
  sections of code instead for other devices in the future.
  - This includes constraints for clocks and I/O pins.
- Remove ability to do timed ctrlport transactions to the MB CPLD, this
  was unused and possibly broken.
- Move daughterboard-specific code into its own code location
  (dboards/zbx)
- Move X410-specific register documentation to its own location
  (doc/X410)
- Refactor Makefiles to split out X410/ZBX specific components and allow
  switching between device types
- Add 512-bit AXI interconnects
- Make number of timekeepers configurable (X410 keeps the single
  timekeeper)

MPM:
- Required compat is bumped to 8.0
- Now supports new registers for detecting DSP capabilities and
  multi-rate settings for the daughterboards
- Adds MMCM controls (currently unused)

Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>


Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
This commit is contained in:
Javier Valenzuela
2023-05-23 09:06:17 +02:00
committed by Martin Braun
co-authored by Wade Fife Ryan Marlow Martin Braun Humberto Jimenez
parent ffdcc016cc
commit adf6f576c6
79 changed files with 41079 additions and 2315 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/x400/rf/sim/Makefile
+14 -13
View File
@@ -36,8 +36,9 @@ include ../200m/Makefile.srcs
include ../400m/Makefile.srcs
DESIGN_SRCS += $(abspath \
../../regmap/PkgRFDC_REGS_REGMAP.vhd \
../../regmap/x410/PkgRFDC_REGS_REGMAP.vhd \
$(RF_COMMON_SRCS) \
$(RF_X410_SRCS) \
$(RF_100M_SRCS) \
$(RF_200M_SRCS) \
$(RF_400M_SRCS) \
@@ -68,18 +69,18 @@ SIM_TOP = rf_all_tb
SIM_RUNTIME_US = 1000
SIM_SRCS = \
$(abspath tb_adc_gearbox_2x1.vhd ) \
$(abspath tb_adc_gearbox_2x4.vhd ) \
$(abspath tb_adc_gearbox_8x4.vhd ) \
$(abspath tb_capture_sysref.vhd ) \
$(abspath tb_dac_gearbox_12x8.vhd ) \
$(abspath tb_dac_gearbox_4x2.vhd ) \
$(abspath tb_dac_gearbox_6x12.vhd ) \
$(abspath tb_ddc_400m_saturate.vhd ) \
$(abspath tb_duc_400m_saturate.vhd ) \
$(abspath tb_rf_nco_reset.vhd ) \
$(abspath tb_rf_reset_controller.vhd) \
$(abspath rf_all_tb.sv ) \
$(abspath tb_adc_gearbox_2x1.vhd ) \
$(abspath tb_adc_gearbox_2x4.vhd ) \
$(abspath tb_adc_gearbox_8x4.vhd ) \
$(abspath tb_capture_sysref.vhd ) \
$(abspath tb_dac_gearbox_12x8.vhd ) \
$(abspath tb_dac_gearbox_4x2.vhd ) \
$(abspath tb_dac_gearbox_6x12.vhd ) \
$(abspath tb_ddc_400m_saturate.vhd ) \
$(abspath tb_duc_400m_saturate.vhd ) \
$(abspath tb_rf_nco_reset.vhd ) \
$(abspath tb_x410_rf_reset_controller.vhd ) \
$(abspath rf_all_tb.sv ) \
#-------------------------------------------------
# Bottom-of-Makefile
top/x400/rf/sim/rf_all_tb.sv
+22 -22
View File
@@ -15,17 +15,17 @@ module rf_all_tb;
`include "test_exec.svh"
import PkgTestExec::*;
tb_adc_gearbox_2x1 tb_adc_gearbox_2x1_i ();
tb_adc_gearbox_2x4 tb_adc_gearbox_2x4_i ();
tb_adc_gearbox_8x4 tb_adc_gearbox_8x4_i ();
tb_capture_sysref tb_capture_sysref_i ();
tb_dac_gearbox_12x8 tb_dac_gearbox_12x8_i ();
tb_dac_gearbox_4x2 tb_dac_gearbox_4x2_i ();
tb_dac_gearbox_6x12 tb_dac_gearbox_6x12_i ();
tb_ddc_400m_saturate tb_ddc_400m_saturate_i ();
tb_duc_400m_saturate tb_duc_400m_saturate_i ();
tb_rf_nco_reset tb_rf_nco_reset_i ();
tb_rf_reset_controller tb_rf_reset_controller_i ();
tb_adc_gearbox_2x1 tb_adc_gearbox_2x1_i ();
tb_adc_gearbox_2x4 tb_adc_gearbox_2x4_i ();
tb_adc_gearbox_8x4 tb_adc_gearbox_8x4_i ();
tb_capture_sysref tb_capture_sysref_i ();
tb_dac_gearbox_12x8 tb_dac_gearbox_12x8_i ();
tb_dac_gearbox_4x2 tb_dac_gearbox_4x2_i ();
tb_dac_gearbox_6x12 tb_dac_gearbox_6x12_i ();
tb_ddc_400m_saturate tb_ddc_400m_saturate_i ();
tb_duc_400m_saturate tb_duc_400m_saturate_i ();
tb_rf_nco_reset tb_rf_nco_reset_i ();
tb_x410_rf_reset_controller tb_x410_rf_reset_controller_i ();
initial begin
test.start_tb("rf_all_tb", 1ms);
@@ -34,17 +34,17 @@ module rf_all_tb;
forever begin
#100ns;
if (
tb_adc_gearbox_2x1_i.StopSim &&
tb_adc_gearbox_2x4_i.StopSim &&
tb_adc_gearbox_8x4_i.StopSim &&
tb_capture_sysref_i.StopSim &&
tb_dac_gearbox_12x8_i.StopSim &&
tb_dac_gearbox_4x2_i.StopSim &&
tb_dac_gearbox_6x12_i.StopSim &&
tb_ddc_400m_saturate_i.StopSim &&
tb_duc_400m_saturate_i.StopSim &&
tb_rf_nco_reset_i.StopSim &&
tb_rf_reset_controller_i.StopSim
tb_adc_gearbox_2x1_i.StopSim &&
tb_adc_gearbox_2x4_i.StopSim &&
tb_adc_gearbox_8x4_i.StopSim &&
tb_capture_sysref_i.StopSim &&
tb_dac_gearbox_12x8_i.StopSim &&
tb_dac_gearbox_4x2_i.StopSim &&
tb_dac_gearbox_6x12_i.StopSim &&
tb_ddc_400m_saturate_i.StopSim &&
tb_duc_400m_saturate_i.StopSim &&
tb_rf_nco_reset_i.StopSim &&
tb_x410_rf_reset_controller_i.StopSim
) break;
end
test.end_test();
top/x400/rf/sim/tb_rf_nco_reset.vhd
+12
View File
@@ -21,7 +21,9 @@ end tb_rf_nco_reset;
architecture RTL of tb_rf_nco_reset is
signal cAdc0xNcoUpdateReq : std_logic;
signal cAdc1xNcoUpdateReq : std_logic;
signal cAdc2xNcoUpdateReq : std_logic;
signal cAdc3xNcoUpdateReq : std_logic;
signal cDac0xNcoUpdateReq : std_logic;
signal cDac0xSysrefIntGating : std_logic;
signal cDac0xSysrefIntReenable : std_logic;
@@ -33,7 +35,9 @@ architecture RTL of tb_rf_nco_reset is
signal cDac0xNcoUpdateBusy : std_logic_vector(1 downto 0) := "00";
signal dStartNcoReset : std_logic := '0';
signal cAdc0xNcoUpdateBusy : std_logic := '0';
signal cAdc1xNcoUpdateBusy : std_logic := '0';
signal cAdc2xNcoUpdateBusy : std_logic := '0';
signal cAdc3xNcoUpdateBusy : std_logic := '0';
signal cDac1xNcoUpdateBusy : std_logic := '0';
signal cSysref_ms, cSysref : std_logic := '0';
@@ -100,8 +104,12 @@ begin
cDac1xNcoUpdateReq => cDac1xNcoUpdateReq,
cAdc0xNcoUpdateBusy => cAdc0xNcoUpdateBusy,
cAdc0xNcoUpdateReq => cAdc0xNcoUpdateReq,
cAdc1xNcoUpdateBusy => cAdc1xNcoUpdateBusy,
cAdc1xNcoUpdateReq => cAdc1xNcoUpdateReq,
cAdc2xNcoUpdateBusy => cAdc2xNcoUpdateBusy,
cAdc2xNcoUpdateReq => cAdc2xNcoUpdateReq,
cAdc3xNcoUpdateBusy => cAdc3xNcoUpdateBusy,
cAdc3xNcoUpdateReq => cAdc3xNcoUpdateReq,
cNcoPhaseRst => cNcoPhaseRst,
cNcoUpdateEn => cNcoUpdateEn,
dNcoResetDone => dNcoResetDone
@@ -180,7 +188,9 @@ begin
cRfdcNcoState <= CheckUpdate;
cDac1xNcoUpdateBusy <= cDac1xNcoUpdateReq;
cAdc0xNcoUpdateBusy <= cAdc0xNcoUpdateReq;
cAdc1xNcoUpdateBusy <= cAdc1xNcoUpdateReq;
cAdc2xNcoUpdateBusy <= cAdc2xNcoUpdateReq;
cAdc3xNcoUpdateBusy <= cAdc3xNcoUpdateReq;
-- It takes 5 clock cycles to update each RFDC internal registers with
-- the used request change. In rf_nco_reset entity, we only want to
@@ -194,7 +204,9 @@ begin
cDac0xNcoUpdateBusy <= "10"; --Indicates that SYSREF is gated.
cDac1xNcoUpdateBusy <= '0';
cAdc0xNcoUpdateBusy <= '0';
cAdc1xNcoUpdateBusy <= '0';
cAdc2xNcoUpdateBusy <= '0';
cAdc3xNcoUpdateBusy <= '0';
end if;
cWrCount <= cWrCount + 1;
top/x400/rf/sim/tb_rf_reset_controller.vhd → top/x400/rf/sim/tb_x410_rf_reset_controller.vhd
+7 -7
View File
@@ -3,11 +3,11 @@
--
-- SPDX-License-Identifier: LGPL-3.0-or-later
--
-- Module: tb_rf_reset_controller
-- Module: tb_x410_rf_reset_controller
--
-- Description:
--
-- Testbench for rf_reset_controller.
-- Testbench for x410_rf_reset_controller.
--
library IEEE;
@@ -17,13 +17,13 @@ library IEEE;
library WORK;
use WORK.PkgRFDC_REGS_REGMAP.all;
entity tb_rf_reset_controller is
end tb_rf_reset_controller;
entity tb_x410_rf_reset_controller is
end tb_x410_rf_reset_controller;
architecture RTL of tb_rf_reset_controller is
architecture RTL of tb_x410_rf_reset_controller is
component rf_reset_controller
component x410_rf_reset_controller
port (
ConfigClk : in std_logic;
DataClk : in std_logic;
@@ -185,7 +185,7 @@ begin
PllRefClk <= not PllRefClk after kPllRefClkPer/2 when not StopSim else '0';
-- rAdcEnableData is a constant and is not tested.
dut: rf_reset_controller
dut: x410_rf_reset_controller
port map (
ConfigClk => ConfigClk,
DataClk => DataClk,