miegl/b210-k7-fpga
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mpm/fpga: x4xx: Major updates in preparation for future devices

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FPGA:
- Split up MB registers that control daughterboard specific settings so
  that daughterboards 0 and 1 could have different setings, in
  preparation for future devices that require different settings.
  This requires a compat number bump to 8.0.
- Add registers for additional RFDC information, including the
  block/tile mapping of the individual channels, and information about
  resampling capabilities
- Identify sections of code that would be specific to X410/ZBX and move
  them to their own headers, so it's trivial to add device-specific
  sections of code instead for other devices in the future.
  - This includes constraints for clocks and I/O pins.
- Remove ability to do timed ctrlport transactions to the MB CPLD, this
  was unused and possibly broken.
- Move daughterboard-specific code into its own code location
  (dboards/zbx)
- Move X410-specific register documentation to its own location
  (doc/X410)
- Refactor Makefiles to split out X410/ZBX specific components and allow
  switching between device types
- Add 512-bit AXI interconnects
- Make number of timekeepers configurable (X410 keeps the single
  timekeeper)

MPM:
- Required compat is bumped to 8.0
- Now supports new registers for detecting DSP capabilities and
  multi-rate settings for the daughterboards
- Adds MMCM controls (currently unused)

Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>


Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
This commit is contained in:
Javier Valenzuela
2023-05-23 09:06:17 +02:00
committed by Martin Braun
co-authored by Wade Fife Ryan Marlow Martin Braun Humberto Jimenez
parent ffdcc016cc
commit adf6f576c6
79 changed files with 41079 additions and 2315 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/x400/ip/Makefile.inc
+48 -20
View File
@@ -5,7 +5,6 @@
#
include $(IP_DIR)/xge_pcs_pma/Makefile.inc
include $(IP_DIR)/x4xx_ps_rfdc_bd/Makefile.inc
include $(IP_DIR)/axi_interconnect_app_bd/Makefile.inc
include $(IP_DIR)/axi_interconnect_eth_bd/Makefile.inc
include $(IP_DIR)/axi_interconnect_dma_bd/Makefile.inc
@@ -14,11 +13,9 @@ include $(IP_DIR)/axi_inter_2x64_512_bd/Makefile.inc
include $(IP_DIR)/axi_inter_4x64_512_bd/Makefile.inc
include $(IP_DIR)/axi_inter_1x128_512_bd/Makefile.inc
include $(IP_DIR)/axi_inter_2x128_512_bd/Makefile.inc
include $(IP_DIR)/ddr4_64bits/Makefile.inc
include $(IP_DIR)/adc_100m_bd/Makefile.inc
include $(IP_DIR)/adc_400m_bd/Makefile.inc
include $(IP_DIR)/dac_100m_bd/Makefile.inc
include $(IP_DIR)/dac_400m_bd/Makefile.inc
include $(IP_DIR)/axi_inter_4x128_512_bd/Makefile.inc
include $(IP_DIR)/axi_inter_1x512_512_bd/Makefile.inc
include $(IP_DIR)/axi_inter_2x512_512_bd/Makefile.inc
include $(IP_DIR)/axi64_4k_2clk_fifo/Makefile.inc
include $(IP_DIR)/fifo_short_2clk/Makefile.inc
include $(IP_DIR)/fifo_4k_2clk/Makefile.inc
@@ -27,6 +24,15 @@ include $(IP_DIR)/axi_eth_dma_bd/Makefile.inc
include $(IP_DIR)/hb47_1to2/Makefile.inc
include $(IP_DIR)/hb47_2to1/Makefile.inc
ifdef X410
include $(IP_DIR)/ddr4_64bits/Makefile.inc
include $(IP_DIR)/adc_100m_bd/Makefile.inc
include $(IP_DIR)/adc_400m_bd/Makefile.inc
include $(IP_DIR)/dac_100m_bd/Makefile.inc
include $(IP_DIR)/dac_400m_bd/Makefile.inc
include $(IP_DIR)/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/Makefile.inc
endif
BD_SRCS = \
$(IP_X4XX_PS_RFDC_BD_SRCS) \
$(IP_X4XX_PS_RFDC_HDL_SRCS) \
@@ -40,21 +46,27 @@ $(IP_AXI_INTER_2X64_512_BD_SRCS) \
$(IP_AXI_INTER_4X64_512_BD_SRCS) \
$(IP_AXI_INTER_1X128_512_BD_SRCS) \
$(IP_AXI_INTER_2X128_512_BD_SRCS) \
$(IP_ADC_100M_BD_SRCS) \
$(IP_ADC_100M_HDL_SRCS) \
$(IP_DAC_100M_BD_SRCS) \
$(IP_DAC_100M_HDL_SRCS) \
$(IP_ADC_400M_BD_SRCS) \
$(IP_ADC_400M_HDL_SRCS) \
$(IP_DAC_400M_BD_SRCS) \
$(IP_DAC_400M_HDL_SRCS) \
$(IP_AXI_INTER_4X128_512_BD_SRCS) \
$(IP_AXI_INTER_1X512_512_BD_SRCS) \
$(IP_AXI_INTER_2X512_512_BD_SRCS) \
$(IP_100G_BD_SRCS) \
$(IP_100G_HDL_SRCS) \
$(IP_AXI_ETH_DMA_BD_SRCS) \
$(IP_AXI_ETH_DMA_BD_HDL_SRCS)
ifdef X410
BD_SRCS += \
$(IP_ADC_100M_BD_SRCS) \
$(IP_ADC_100M_HDL_SRCS) \
$(IP_DAC_100M_BD_SRCS) \
$(IP_DAC_100M_HDL_SRCS) \
$(IP_ADC_400M_BD_SRCS) \
$(IP_ADC_400M_HDL_SRCS) \
$(IP_DAC_400M_BD_SRCS) \
$(IP_DAC_400M_HDL_SRCS)
endif
IP_XCI_SRCS = \
$(IP_DDR4_64BITS_SRCS) \
$(IP_XGE_PCS_PMA_SRCS) \
$(IP_AXI64_4K_2CLK_FIFO_SRCS) \
$(IP_FIFO_SHORT_2CLK_SRCS) \
@@ -62,6 +74,11 @@ $(IP_FIFO_4K_2CLK_SRCS) \
$(IP_HB47_1TO2_SRCS) \
$(IP_HB47_2TO1_SRCS) \
ifdef X410
IP_XCI_SRCS += \
$(IP_DDR4_64BITS_SRCS)
endif
BD_OUTPUTS = \
$(BD_X4XX_PS_RFDC_BD_OUTS) \
$(BD_AXI_INTERCONNECT_APP_BD_OUTS) \
@@ -72,15 +89,21 @@ $(BD_AXI_INTER_2x64_512_BD_OUTS) \
$(BD_AXI_INTER_4x64_512_BD_OUTS) \
$(BD_AXI_INTER_1X128_512_BD_OUTS) \
$(BD_AXI_INTER_2X128_512_BD_OUTS) \
$(BD_ADC_100M_BD_OUTS) \
$(BD_ADC_400M_BD_OUTS) \
$(BD_DAC_100M_BD_OUTS) \
$(BD_DAC_400M_BD_OUTS) \
$(BD_AXI_INTER_4x128_512_BD_OUTS) \
$(BD_AXI_INTER_1X512_512_BD_OUTS) \
$(BD_AXI_INTER_2X512_512_BD_OUTS) \
$(BD_100G_BD_OUTS) \
$(BD_AXI_ETH_DMA_BD_OUTS)
ifdef X410
BD_OUTPUTS += \
$(BD_ADC_100M_BD_OUTS) \
$(BD_ADC_400M_BD_OUTS) \
$(BD_DAC_100M_BD_OUTS) \
$(BD_DAC_400M_BD_OUTS)
endif
IP_SYNTH_OUTPUTS = \
$(IP_DDR4_64BITS_OUTS) \
$(IP_XGE_PCS_PMA_OUTS) \
$(IP_AXI64_4K_2CLK_FIFO_OUTS) \
$(IP_FIFO_SHORT_2CLK_OUTS) \
@@ -88,6 +111,11 @@ $(IP_FIFO_4K_2CLK_OUTS) \
$(IP_HB47_1TO2_OUTS) \
$(IP_HB47_2TO1_OUTS) \
ifdef X410
IP_SYNTH_OUTPUTS += \
$(IP_DDR4_64BITS_OUTS)
endif
IP_HDL_SIM_SRCS = \
$(IP_AXI64_4K_2CLK_FIFO_HDL_SIM_SRCS) \
$(IP_FIFO_4K_2CLK_HDL_SIM_SRCS) \
top/x400/ip/axi_inter_1x512_512_bd/Makefile.inc
+32
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@@ -0,0 +1,32 @@
#
# Copyright 2022 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_AXI_INTER_1X512_512_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_inter_1x512_512_bd/, \
axi_inter_1x512_512_bd.tcl \
)
IP_AXI_INTER_1X512_512_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_1x512_512_bd/, \
axi_inter_1x512_512_bd.tcl \
)
IP_AXI_INTER_1X512_512_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_1x512_512_bd/, \
axi_inter_1x512_512_bd/axi_inter_1x512_512_bd.bd \
)
BD_AXI_INTER_1X512_512_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_inter_1x512_512_bd/, \
axi_inter_1x512_512_bd.bd.out \
axi_inter_1x512_512_bd/axi_inter_1x512_512_bd_ooc.xdc \
axi_inter_1x512_512_bd/synth/axi_inter_1x512_512_bd.v \
)
.INTERMEDIATE: IP_AXI_INTER_1X512_512_BD_TRGT
$(IP_AXI_INTER_1X512_512_BD_SRCS) $(BD_AXI_INTER_1X512_512_BD_OUTS) $(IP_AXI_INTER_1X512_512_BDTCL_SRCS): IP_AXI_INTER_1X512_512_BD_TRGT
@:
IP_AXI_INTER_1X512_512_BD_TRGT: $(IP_AXI_INTER_1X512_512_ORIG_SRCS)
$(call BUILD_VIVADO_BDTCL,axi_inter_1x512_512_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi)
top/x400/ip/axi_inter_1x512_512_bd/axi_inter_1x512_512_bd.tcl
+314
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@@ -0,0 +1,314 @@
################################################################
# This is a generated script based on design: axi_inter_1x512_512_bd
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
namespace eval _tcl {
proc get_script_folder {} {
set script_path [file normalize [info script]]
set script_folder [file dirname $script_path]
return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2021.1
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
################################################################
# START
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source axi_inter_1x512_512_bd_script.tcl
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project project_1 myproj -part xczu28dr-ffvg1517-2-e
}
# CHANGE DESIGN NAME HERE
variable design_name
set design_name axi_inter_1x512_512_bd
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
return $nRet
}
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
xilinx.com:ip:axi_clock_converter:2.1\
xilinx.com:ip:axi_data_fifo:2.1\
xilinx.com:ip:axi_register_slice:2.1\
"
set list_ips_missing ""
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
if { $ip_obj eq "" } {
lappend list_ips_missing $ip_vlnv
}
}
if { $list_ips_missing ne "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
##################################################################
# DESIGN PROCs
##################################################################
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
variable script_folder
variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
set M_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.DATA_WIDTH {512} \
CONFIG.FREQ_HZ {350000000} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.PROTOCOL {AXI4} \
] $M_AXI
set S_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
CONFIG.DATA_WIDTH {512} \
CONFIG.FREQ_HZ {350000000} \
CONFIG.HAS_BRESP {1} \
CONFIG.HAS_BURST {1} \
CONFIG.HAS_CACHE {1} \
CONFIG.HAS_LOCK {1} \
CONFIG.HAS_PROT {1} \
CONFIG.HAS_QOS {1} \
CONFIG.HAS_REGION {1} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {1} \
CONFIG.ID_WIDTH {1} \
CONFIG.MAX_BURST_LENGTH {256} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_READ_THREADS {1} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.NUM_WRITE_THREADS {1} \
CONFIG.PROTOCOL {AXI4} \
CONFIG.READ_WRITE_MODE {READ_WRITE} \
CONFIG.RUSER_BITS_PER_BYTE {0} \
CONFIG.RUSER_WIDTH {0} \
CONFIG.SUPPORTS_NARROW_BURST {1} \
CONFIG.WUSER_BITS_PER_BYTE {0} \
CONFIG.WUSER_WIDTH {0} \
] $S_AXI
# Create ports
set M_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 M_AXI_ACLK ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {M_AXI} \
CONFIG.ASSOCIATED_RESET {M_AXI_ARESETN} \
] $M_AXI_ACLK
set M_AXI_ARESETN [ create_bd_port -dir I -type rst M_AXI_ARESETN ]
set S_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 S_AXI_ACLK ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {S_AXI} \
CONFIG.ASSOCIATED_RESET {S_AXI_ARESETN} \
] $S_AXI_ACLK
set S_AXI_ARESETN [ create_bd_port -dir I -type rst S_AXI_ARESETN ]
# Create instance: axi_clock_converter_0, and set properties
set axi_clock_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0 ]
# Create instance: axi_data_fifo_0, and set properties
set axi_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_data_fifo:2.1 axi_data_fifo_0 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.READ_FIFO_DEPTH {512} \
CONFIG.WRITE_FIFO_DEPTH {512} \
] $axi_data_fifo_0
# Create instance: axi_data_fifo_1, and set properties
set axi_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_data_fifo:2.1 axi_data_fifo_1 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.READ_FIFO_DEPTH {512} \
CONFIG.WRITE_FIFO_DEPTH {512} \
] $axi_data_fifo_1
# Create instance: axi_register_slice_0, and set properties
set axi_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_0 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.ID_WIDTH {1} \
] $axi_register_slice_0
# Create instance: axi_register_slice_2, and set properties
set axi_register_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_2 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.ID_WIDTH {2} \
] $axi_register_slice_2
# Create interface connections
connect_bd_intf_net -intf_net S_AXI_0_1 [get_bd_intf_ports S_AXI] [get_bd_intf_pins axi_register_slice_0/S_AXI]
connect_bd_intf_net -intf_net axi_clock_converter_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/M_AXI] [get_bd_intf_pins axi_data_fifo_0/S_AXI]
connect_bd_intf_net -intf_net axi_data_fifo_0_M_AXI [get_bd_intf_pins axi_data_fifo_0/M_AXI] [get_bd_intf_pins axi_register_slice_2/S_AXI]
connect_bd_intf_net -intf_net axi_data_fifo_1_M_AXI [get_bd_intf_pins axi_clock_converter_0/S_AXI] [get_bd_intf_pins axi_data_fifo_1/M_AXI]
connect_bd_intf_net -intf_net axi_register_slice_0_M_AXI [get_bd_intf_pins axi_data_fifo_1/S_AXI] [get_bd_intf_pins axi_register_slice_0/M_AXI]
connect_bd_intf_net -intf_net axi_register_slice_2_M_AXI [get_bd_intf_ports M_AXI] [get_bd_intf_pins axi_register_slice_2/M_AXI]
# Create port connections
connect_bd_net -net m_axi_aclk_0_1 [get_bd_ports M_AXI_ACLK] [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_data_fifo_0/aclk] [get_bd_pins axi_register_slice_2/aclk]
connect_bd_net -net m_axi_aresetn_0_1 [get_bd_ports M_AXI_ARESETN] [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axi_data_fifo_0/aresetn] [get_bd_pins axi_register_slice_2/aresetn]
connect_bd_net -net s_axi_aclk_0_1 [get_bd_ports S_AXI_ACLK] [get_bd_pins axi_clock_converter_0/s_axi_aclk] [get_bd_pins axi_data_fifo_1/aclk] [get_bd_pins axi_register_slice_0/aclk]
connect_bd_net -net s_axi_aresetn_0_1 [get_bd_ports S_AXI_ARESETN] [get_bd_pins axi_clock_converter_0/s_axi_aresetn] [get_bd_pins axi_data_fifo_1/aresetn] [get_bd_pins axi_register_slice_0/aresetn]
# Create address segments
# Restore current instance
current_bd_instance $oldCurInst
validate_bd_design
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""
top/x400/ip/axi_inter_2x512_512_bd/Makefile.inc
+32
View File
@@ -0,0 +1,32 @@
#
# Copyright 2022 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_AXI_INTER_2X512_512_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_inter_2x512_512_bd/, \
axi_inter_2x512_512_bd.tcl \
)
IP_AXI_INTER_2X512_512_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_2x512_512_bd/, \
axi_inter_2x512_512_bd.tcl \
)
IP_AXI_INTER_2X512_512_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_2x512_512_bd/, \
axi_inter_2x512_512_bd/axi_inter_2x512_512_bd.bd \
)
BD_AXI_INTER_2X512_512_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_inter_2x512_512_bd/, \
axi_inter_2x512_512_bd.bd.out \
axi_inter_2x512_512_bd/axi_inter_2x512_512_bd_ooc.xdc \
axi_inter_2x512_512_bd/synth/axi_inter_2x512_512_bd.v \
)
.INTERMEDIATE: IP_AXI_INTER_2X512_512_BD_TRGT
$(IP_AXI_INTER_2X512_512_BD_SRCS) $(BD_AXI_INTER_2X512_512_BD_OUTS) $(IP_AXI_INTER_2X512_512_BDTCL_SRCS): IP_AXI_INTER_2X512_512_BD_TRGT
@:
IP_AXI_INTER_2X512_512_BD_TRGT: $(IP_AXI_INTER_2X512_512_ORIG_SRCS)
$(call BUILD_VIVADO_BDTCL,axi_inter_2x512_512_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi)
top/x400/ip/axi_inter_2x512_512_bd/axi_inter_2x512_512_bd.tcl
+380
View File
@@ -0,0 +1,380 @@
################################################################
# This is a generated script based on design: axi_inter_2x512_512_bd
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
namespace eval _tcl {
proc get_script_folder {} {
set script_path [file normalize [info script]]
set script_folder [file dirname $script_path]
return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2021.1
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
################################################################
# START
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source axi_inter_2x512_512_bd_script.tcl
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project project_1 myproj -part xczu28dr-ffvg1517-2-e
}
# CHANGE DESIGN NAME HERE
variable design_name
set design_name axi_inter_2x512_512_bd
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
return $nRet
}
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
xilinx.com:ip:axi_clock_converter:2.1\
xilinx.com:ip:axi_crossbar:2.1\
xilinx.com:ip:axi_data_fifo:2.1\
xilinx.com:ip:axi_register_slice:2.1\
"
set list_ips_missing ""
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
if { $ip_obj eq "" } {
lappend list_ips_missing $ip_vlnv
}
}
if { $list_ips_missing ne "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
##################################################################
# DESIGN PROCs
##################################################################
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
variable script_folder
variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
set M0_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M0_AXI ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.DATA_WIDTH {512} \
CONFIG.FREQ_HZ {350000000} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.PROTOCOL {AXI4} \
] $M0_AXI
set S0_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S0_AXI ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
CONFIG.DATA_WIDTH {512} \
CONFIG.FREQ_HZ {350000000} \
CONFIG.HAS_BRESP {1} \
CONFIG.HAS_BURST {1} \
CONFIG.HAS_CACHE {1} \
CONFIG.HAS_LOCK {1} \
CONFIG.HAS_PROT {1} \
CONFIG.HAS_QOS {1} \
CONFIG.HAS_REGION {1} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {1} \
CONFIG.ID_WIDTH {1} \
CONFIG.MAX_BURST_LENGTH {256} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_READ_THREADS {1} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.NUM_WRITE_THREADS {1} \
CONFIG.PROTOCOL {AXI4} \
CONFIG.READ_WRITE_MODE {READ_WRITE} \
CONFIG.RUSER_BITS_PER_BYTE {0} \
CONFIG.RUSER_WIDTH {0} \
CONFIG.SUPPORTS_NARROW_BURST {1} \
CONFIG.WUSER_BITS_PER_BYTE {0} \
CONFIG.WUSER_WIDTH {0} \
] $S0_AXI
set S1_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S1_AXI ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
CONFIG.DATA_WIDTH {512} \
CONFIG.FREQ_HZ {350000000} \
CONFIG.HAS_BRESP {1} \
CONFIG.HAS_BURST {1} \
CONFIG.HAS_CACHE {1} \
CONFIG.HAS_LOCK {1} \
CONFIG.HAS_PROT {1} \
CONFIG.HAS_QOS {1} \
CONFIG.HAS_REGION {1} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {1} \
CONFIG.ID_WIDTH {1} \
CONFIG.MAX_BURST_LENGTH {256} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_READ_THREADS {1} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.NUM_WRITE_THREADS {1} \
CONFIG.PROTOCOL {AXI4} \
CONFIG.READ_WRITE_MODE {READ_WRITE} \
CONFIG.RUSER_BITS_PER_BYTE {0} \
CONFIG.RUSER_WIDTH {0} \
CONFIG.SUPPORTS_NARROW_BURST {1} \
CONFIG.WUSER_BITS_PER_BYTE {0} \
CONFIG.WUSER_WIDTH {0} \
] $S1_AXI
# Create ports
set M0_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 M0_AXI_ACLK ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {M0_AXI} \
CONFIG.ASSOCIATED_RESET {M0_AXI_ARESETN} \
] $M0_AXI_ACLK
set M0_AXI_ARESETN [ create_bd_port -dir I -type rst M0_AXI_ARESETN ]
set_property -dict [ list \
CONFIG.POLARITY {ACTIVE_LOW} \
] $M0_AXI_ARESETN
set S0_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 S0_AXI_ACLK ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {S0_AXI:S1_AXI} \
CONFIG.ASSOCIATED_RESET {S0_AXI_ARESETN:S0_AXI_ARESETN} \
] $S0_AXI_ACLK
set S0_AXI_ARESETN [ create_bd_port -dir I -type rst S0_AXI_ARESETN ]
# Create instance: axi_clock_converter_0, and set properties
set axi_clock_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0 ]
# Create instance: axi_crossbar_0, and set properties
set axi_crossbar_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 axi_crossbar_0 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.ID_WIDTH {2} \
CONFIG.NUM_MI {1} \
CONFIG.NUM_SI {2} \
] $axi_crossbar_0
# Create instance: axi_data_fifo_0, and set properties
set axi_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_data_fifo:2.1 axi_data_fifo_0 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.READ_FIFO_DEPTH {512} \
CONFIG.WRITE_FIFO_DEPTH {512} \
] $axi_data_fifo_0
# Create instance: axi_data_fifo_1, and set properties
set axi_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_data_fifo:2.1 axi_data_fifo_1 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.READ_FIFO_DEPTH {512} \
CONFIG.WRITE_FIFO_DEPTH {512} \
] $axi_data_fifo_1
# Create instance: axi_data_fifo_2, and set properties
set axi_data_fifo_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_data_fifo:2.1 axi_data_fifo_2 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.READ_FIFO_DEPTH {512} \
CONFIG.WRITE_FIFO_DEPTH {512} \
] $axi_data_fifo_2
# Create instance: axi_register_slice_0, and set properties
set axi_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_0 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.ID_WIDTH {1} \
] $axi_register_slice_0
# Create instance: axi_register_slice_1, and set properties
set axi_register_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_1 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.ID_WIDTH {1} \
] $axi_register_slice_1
# Create instance: axi_register_slice_2, and set properties
set axi_register_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_2 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.ID_WIDTH {2} \
] $axi_register_slice_2
# Create interface connections
connect_bd_intf_net -intf_net S_AXI_0_1 [get_bd_intf_ports S0_AXI] [get_bd_intf_pins axi_register_slice_0/S_AXI]
connect_bd_intf_net -intf_net S_AXI_1_1 [get_bd_intf_ports S1_AXI] [get_bd_intf_pins axi_register_slice_1/S_AXI]
connect_bd_intf_net -intf_net axi_clock_converter_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/M_AXI] [get_bd_intf_pins axi_data_fifo_0/S_AXI]
connect_bd_intf_net -intf_net axi_crossbar_0_M00_AXI [get_bd_intf_pins axi_clock_converter_0/S_AXI] [get_bd_intf_pins axi_crossbar_0/M00_AXI]
connect_bd_intf_net -intf_net axi_data_fifo_0_M_AXI [get_bd_intf_pins axi_data_fifo_0/M_AXI] [get_bd_intf_pins axi_register_slice_2/S_AXI]
connect_bd_intf_net -intf_net axi_data_fifo_1_M_AXI [get_bd_intf_pins axi_crossbar_0/S00_AXI] [get_bd_intf_pins axi_data_fifo_1/M_AXI]
connect_bd_intf_net -intf_net axi_data_fifo_2_M_AXI [get_bd_intf_pins axi_crossbar_0/S01_AXI] [get_bd_intf_pins axi_data_fifo_2/M_AXI]
connect_bd_intf_net -intf_net axi_register_slice_0_M_AXI [get_bd_intf_pins axi_data_fifo_1/S_AXI] [get_bd_intf_pins axi_register_slice_0/M_AXI]
connect_bd_intf_net -intf_net axi_register_slice_1_M_AXI [get_bd_intf_pins axi_data_fifo_2/S_AXI] [get_bd_intf_pins axi_register_slice_1/M_AXI]
connect_bd_intf_net -intf_net axi_register_slice_2_M_AXI [get_bd_intf_ports M0_AXI] [get_bd_intf_pins axi_register_slice_2/M_AXI]
# Create port connections
connect_bd_net -net M0_AXI_ACLK_1 [get_bd_ports M0_AXI_ACLK] [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_data_fifo_0/aclk] [get_bd_pins axi_register_slice_2/aclk]
connect_bd_net -net M0_AXI_ARESETN_1 [get_bd_ports M0_AXI_ARESETN] [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axi_data_fifo_0/aresetn] [get_bd_pins axi_register_slice_2/aresetn]
connect_bd_net -net s_axi_aclk_0_1 [get_bd_ports S0_AXI_ACLK] [get_bd_pins axi_clock_converter_0/s_axi_aclk] [get_bd_pins axi_crossbar_0/aclk] [get_bd_pins axi_data_fifo_1/aclk] [get_bd_pins axi_data_fifo_2/aclk] [get_bd_pins axi_register_slice_0/aclk] [get_bd_pins axi_register_slice_1/aclk]
connect_bd_net -net s_axi_aresetn_0_1 [get_bd_ports S0_AXI_ARESETN] [get_bd_pins axi_clock_converter_0/s_axi_aresetn] [get_bd_pins axi_crossbar_0/aresetn] [get_bd_pins axi_data_fifo_1/aresetn] [get_bd_pins axi_data_fifo_2/aresetn] [get_bd_pins axi_register_slice_0/aresetn] [get_bd_pins axi_register_slice_1/aresetn]
# Create address segments
assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S0_AXI] [get_bd_addr_segs M0_AXI/Reg] -force
assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S1_AXI] [get_bd_addr_segs M0_AXI/Reg] -force
# Restore current instance
current_bd_instance $oldCurInst
validate_bd_design
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""
top/x400/ip/axi_inter_4x128_512_bd/Makefile.inc
+32
View File
@@ -0,0 +1,32 @@
#
# Copyright 2022 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_AXI_INTER_4X128_512_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_inter_4x128_512_bd/, \
axi_inter_4x128_512_bd.tcl \
)
IP_AXI_INTER_4X128_512_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_4x128_512_bd/, \
axi_inter_4x128_512_bd.tcl \
)
IP_AXI_INTER_4X128_512_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_4x128_512_bd/, \
axi_inter_4x128_512_bd/axi_inter_4x128_512_bd.bd \
)
BD_AXI_INTER_4X128_512_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_inter_4x128_512_bd/, \
axi_inter_4x128_512_bd.bd.out \
axi_inter_4x128_512_bd/axi_inter_4x128_512_bd_ooc.xdc \
axi_inter_4x128_512_bd/synth/axi_inter_4x128_512_bd.v \
)
.INTERMEDIATE: IP_AXI_INTER_4X128_512_BD_TRGT
$(IP_AXI_INTER_4X128_512_BD_SRCS) $(BD_AXI_INTER_4X128_512_BD_OUTS) $(IP_AXI_INTER_4X128_512_BDTCL_SRCS): IP_AXI_INTER_4X128_512_BD_TRGT
@:
IP_AXI_INTER_4X128_512_BD_TRGT: $(IP_AXI_INTER_4X128_512_ORIG_SRCS)
$(call BUILD_VIVADO_BDTCL,axi_inter_4x128_512_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi)
top/x400/ip/axi_inter_4x128_512_bd/axi_inter_4x128_512_bd.tcl
+823
View File
@@ -0,0 +1,823 @@
################################################################
# This is a generated script based on design: axi_inter_4x128_512_bd
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
namespace eval _tcl {
proc get_script_folder {} {
set script_path [file normalize [info script]]
set script_folder [file dirname $script_path]
return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2021.1
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
################################################################
# START
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source axi_inter_4x128_512_bd_script.tcl
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project project_1 myproj -part xczu28dr-ffve1156-2-e
}
# CHANGE DESIGN NAME HERE
variable design_name
set design_name axi_inter_4x128_512_bd
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
return $nRet
}
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
xilinx.com:ip:axi_crossbar:2.1\
xilinx.com:ip:axi_dwidth_converter:2.1\
xilinx.com:ip:axi_register_slice:2.1\
"
set list_ips_missing ""
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
if { $ip_obj eq "" } {
lappend list_ips_missing $ip_vlnv
}
}
if { $list_ips_missing ne "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
##################################################################
# DESIGN PROCs
##################################################################
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
variable script_folder
variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
set M0_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M0_AXI ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.DATA_WIDTH {512} \
CONFIG.FREQ_HZ {350000000} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.PROTOCOL {AXI4} \
] $M0_AXI
set S0_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S0_AXI ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
CONFIG.DATA_WIDTH {128} \
CONFIG.FREQ_HZ {350000000} \
CONFIG.HAS_BRESP {1} \
CONFIG.HAS_BURST {1} \
CONFIG.HAS_CACHE {1} \
CONFIG.HAS_LOCK {1} \
CONFIG.HAS_PROT {1} \
CONFIG.HAS_QOS {1} \
CONFIG.HAS_REGION {1} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {1} \
CONFIG.ID_WIDTH {1} \
CONFIG.MAX_BURST_LENGTH {256} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_READ_THREADS {1} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.NUM_WRITE_THREADS {1} \
CONFIG.PROTOCOL {AXI4} \
CONFIG.READ_WRITE_MODE {READ_WRITE} \
CONFIG.RUSER_BITS_PER_BYTE {0} \
CONFIG.RUSER_WIDTH {0} \
CONFIG.SUPPORTS_NARROW_BURST {1} \
CONFIG.WUSER_BITS_PER_BYTE {0} \
CONFIG.WUSER_WIDTH {0} \
] $S0_AXI
set S1_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S1_AXI ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
CONFIG.DATA_WIDTH {128} \
CONFIG.FREQ_HZ {350000000} \
CONFIG.HAS_BRESP {1} \
CONFIG.HAS_BURST {1} \
CONFIG.HAS_CACHE {1} \
CONFIG.HAS_LOCK {1} \
CONFIG.HAS_PROT {1} \
CONFIG.HAS_QOS {1} \
CONFIG.HAS_REGION {1} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {1} \
CONFIG.ID_WIDTH {1} \
CONFIG.MAX_BURST_LENGTH {256} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_READ_THREADS {1} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.NUM_WRITE_THREADS {1} \
CONFIG.PROTOCOL {AXI4} \
CONFIG.READ_WRITE_MODE {READ_WRITE} \
CONFIG.RUSER_BITS_PER_BYTE {0} \
CONFIG.RUSER_WIDTH {0} \
CONFIG.SUPPORTS_NARROW_BURST {1} \
CONFIG.WUSER_BITS_PER_BYTE {0} \
CONFIG.WUSER_WIDTH {0} \
] $S1_AXI
set S2_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S2_AXI ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
CONFIG.DATA_WIDTH {128} \
CONFIG.FREQ_HZ {350000000} \
CONFIG.HAS_BRESP {1} \
CONFIG.HAS_BURST {1} \
CONFIG.HAS_CACHE {1} \
CONFIG.HAS_LOCK {1} \
CONFIG.HAS_PROT {1} \
CONFIG.HAS_QOS {1} \
CONFIG.HAS_REGION {1} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {1} \
CONFIG.ID_WIDTH {1} \
CONFIG.MAX_BURST_LENGTH {256} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_READ_THREADS {1} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.NUM_WRITE_THREADS {1} \
CONFIG.PROTOCOL {AXI4} \
CONFIG.READ_WRITE_MODE {READ_WRITE} \
CONFIG.RUSER_BITS_PER_BYTE {0} \
CONFIG.RUSER_WIDTH {0} \
CONFIG.SUPPORTS_NARROW_BURST {1} \
CONFIG.WUSER_BITS_PER_BYTE {0} \
CONFIG.WUSER_WIDTH {0} \
] $S2_AXI
set S3_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S3_AXI ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
CONFIG.DATA_WIDTH {128} \
CONFIG.FREQ_HZ {350000000} \
CONFIG.HAS_BRESP {1} \
CONFIG.HAS_BURST {1} \
CONFIG.HAS_CACHE {1} \
CONFIG.HAS_LOCK {1} \
CONFIG.HAS_PROT {1} \
CONFIG.HAS_QOS {1} \
CONFIG.HAS_REGION {1} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {1} \
CONFIG.ID_WIDTH {1} \
CONFIG.MAX_BURST_LENGTH {256} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_READ_THREADS {1} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.NUM_WRITE_THREADS {1} \
CONFIG.PROTOCOL {AXI4} \
CONFIG.READ_WRITE_MODE {READ_WRITE} \
CONFIG.RUSER_BITS_PER_BYTE {0} \
CONFIG.RUSER_WIDTH {0} \
CONFIG.SUPPORTS_NARROW_BURST {1} \
CONFIG.WUSER_BITS_PER_BYTE {0} \
CONFIG.WUSER_WIDTH {0} \
] $S3_AXI
# Create ports
set M0_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 M0_AXI_ACLK ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {M0_AXI} \
CONFIG.ASSOCIATED_RESET {M0_AXI_ARESETN} \
] $M0_AXI_ACLK
set M0_AXI_ARESETN [ create_bd_port -dir I -type rst M0_AXI_ARESETN ]
set_property -dict [ list \
CONFIG.POLARITY {ACTIVE_LOW} \
] $M0_AXI_ARESETN
set S0_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 S0_AXI_ACLK ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {S0_AXI:S1_AXI:S2_AXI:S3_AXI} \
CONFIG.ASSOCIATED_RESET {S0_AXI_ARESETN} \
] $S0_AXI_ACLK
set S0_AXI_ARESETN [ create_bd_port -dir I -type rst S0_AXI_ARESETN ]
# Create instance: axi_crossbar_0, and set properties
set axi_crossbar_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 axi_crossbar_0 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.ID_WIDTH {4} \
CONFIG.M00_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M00_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M00_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M00_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M00_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M00_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M00_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M00_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M00_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M00_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M00_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M00_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M00_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M00_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M00_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A00_ADDR_WIDTH {0} \
CONFIG.M01_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A00_ADDR_WIDTH {0} \
CONFIG.M02_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A00_ADDR_WIDTH {0} \
CONFIG.M03_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A00_ADDR_WIDTH {0} \
CONFIG.M04_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A00_ADDR_WIDTH {0} \
CONFIG.M05_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A00_ADDR_WIDTH {0} \
CONFIG.M06_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A00_ADDR_WIDTH {0} \
CONFIG.M07_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A00_ADDR_WIDTH {0} \
CONFIG.M08_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A00_ADDR_WIDTH {0} \
CONFIG.M09_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A00_ADDR_WIDTH {0} \
CONFIG.M10_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A00_ADDR_WIDTH {0} \
CONFIG.M11_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A00_ADDR_WIDTH {0} \
CONFIG.M12_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A00_ADDR_WIDTH {0} \
CONFIG.M13_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A00_ADDR_WIDTH {0} \
CONFIG.M14_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A00_ADDR_WIDTH {0} \
CONFIG.M15_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.NUM_MI {1} \
CONFIG.NUM_SI {4} \
CONFIG.S01_BASE_ID {0x00000004} \
CONFIG.S02_BASE_ID {0x00000008} \
CONFIG.S03_BASE_ID {0x0000000c} \
CONFIG.S04_BASE_ID {0x00000010} \
CONFIG.S05_BASE_ID {0x00000014} \
CONFIG.S06_BASE_ID {0x00000018} \
CONFIG.S07_BASE_ID {0x0000001c} \
CONFIG.S08_BASE_ID {0x00000020} \
CONFIG.S09_BASE_ID {0x00000024} \
CONFIG.S10_BASE_ID {0x00000028} \
CONFIG.S11_BASE_ID {0x0000002c} \
CONFIG.S12_BASE_ID {0x00000030} \
CONFIG.S13_BASE_ID {0x00000034} \
CONFIG.S14_BASE_ID {0x00000038} \
CONFIG.S15_BASE_ID {0x0000003c} \
] $axi_crossbar_0
# Create instance: axi_dwidth_converter_0, and set properties
set axi_dwidth_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_0 ]
set_property -dict [ list \
CONFIG.ACLK_ASYNC {1} \
CONFIG.FIFO_MODE {2} \
CONFIG.MI_DATA_WIDTH {512} \
CONFIG.SI_DATA_WIDTH {128} \
CONFIG.SI_ID_WIDTH {1} \
CONFIG.SYNCHRONIZATION_STAGES {3} \
] $axi_dwidth_converter_0
# Create instance: axi_dwidth_converter_1, and set properties
set axi_dwidth_converter_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_1 ]
set_property -dict [ list \
CONFIG.ACLK_ASYNC {1} \
CONFIG.FIFO_MODE {2} \
CONFIG.MI_DATA_WIDTH {512} \
CONFIG.SI_DATA_WIDTH {128} \
CONFIG.SI_ID_WIDTH {1} \
CONFIG.SYNCHRONIZATION_STAGES {3} \
] $axi_dwidth_converter_1
# Create instance: axi_dwidth_converter_2, and set properties
set axi_dwidth_converter_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_2 ]
set_property -dict [ list \
CONFIG.ACLK_ASYNC {1} \
CONFIG.FIFO_MODE {2} \
CONFIG.MI_DATA_WIDTH {512} \
CONFIG.SI_DATA_WIDTH {128} \
CONFIG.SI_ID_WIDTH {1} \
CONFIG.SYNCHRONIZATION_STAGES {3} \
] $axi_dwidth_converter_2
# Create instance: axi_dwidth_converter_3, and set properties
set axi_dwidth_converter_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_3 ]
set_property -dict [ list \
CONFIG.ACLK_ASYNC {1} \
CONFIG.FIFO_MODE {2} \
CONFIG.MI_DATA_WIDTH {512} \
CONFIG.SI_DATA_WIDTH {128} \
CONFIG.SI_ID_WIDTH {1} \
CONFIG.SYNCHRONIZATION_STAGES {3} \
] $axi_dwidth_converter_3
# Create instance: axi_register_slice_0, and set properties
set axi_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_0 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {128} \
CONFIG.ID_WIDTH {1} \
CONFIG.REG_AR {1} \
CONFIG.REG_AW {1} \
CONFIG.REG_B {1} \
] $axi_register_slice_0
# Create instance: axi_register_slice_1, and set properties
set axi_register_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_1 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {128} \
CONFIG.ID_WIDTH {1} \
CONFIG.REG_AR {1} \
CONFIG.REG_AW {1} \
CONFIG.REG_B {1} \
] $axi_register_slice_1
# Create instance: axi_register_slice_2, and set properties
set axi_register_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_2 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {128} \
CONFIG.ID_WIDTH {1} \
CONFIG.REG_AR {1} \
CONFIG.REG_AW {1} \
CONFIG.REG_B {1} \
] $axi_register_slice_2
# Create instance: axi_register_slice_3, and set properties
set axi_register_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_3 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {128} \
CONFIG.ID_WIDTH {1} \
CONFIG.REG_AR {1} \
CONFIG.REG_AW {1} \
CONFIG.REG_B {1} \
] $axi_register_slice_3
# Create instance: axi_register_slice_4, and set properties
set axi_register_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_4 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.ID_WIDTH {1} \
CONFIG.REG_AR {1} \
CONFIG.REG_AW {1} \
CONFIG.REG_B {1} \
] $axi_register_slice_4
# Create instance: axi_register_slice_5, and set properties
set axi_register_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_5 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.ID_WIDTH {1} \
CONFIG.REG_AR {1} \
CONFIG.REG_AW {1} \
CONFIG.REG_B {1} \
] $axi_register_slice_5
# Create instance: axi_register_slice_6, and set properties
set axi_register_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_6 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.ID_WIDTH {1} \
CONFIG.REG_AR {1} \
CONFIG.REG_AW {1} \
CONFIG.REG_B {1} \
] $axi_register_slice_6
# Create instance: axi_register_slice_7, and set properties
set axi_register_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_7 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.ID_WIDTH {1} \
CONFIG.REG_AR {1} \
CONFIG.REG_AW {1} \
CONFIG.REG_B {1} \
] $axi_register_slice_7
# Create instance: axi_register_slice_8, and set properties
set axi_register_slice_8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_8 ]
set_property -dict [ list \
CONFIG.ID_WIDTH {4} \
CONFIG.REG_AR {1} \
CONFIG.REG_AW {1} \
CONFIG.REG_B {1} \
] $axi_register_slice_8
# Create interface connections
connect_bd_intf_net -intf_net S_AXI_0_1 [get_bd_intf_ports S0_AXI] [get_bd_intf_pins axi_register_slice_0/S_AXI]
connect_bd_intf_net -intf_net S_AXI_1_1 [get_bd_intf_ports S1_AXI] [get_bd_intf_pins axi_register_slice_1/S_AXI]
connect_bd_intf_net -intf_net S_AXI_2_1 [get_bd_intf_ports S2_AXI] [get_bd_intf_pins axi_register_slice_2/S_AXI]
connect_bd_intf_net -intf_net S_AXI_3_1 [get_bd_intf_ports S3_AXI] [get_bd_intf_pins axi_register_slice_3/S_AXI]
connect_bd_intf_net -intf_net axi_crossbar_0_M00_AXI [get_bd_intf_pins axi_crossbar_0/M00_AXI] [get_bd_intf_pins axi_register_slice_8/S_AXI]
connect_bd_intf_net -intf_net axi_dwidth_converter_0_M_AXI [get_bd_intf_pins axi_dwidth_converter_0/M_AXI] [get_bd_intf_pins axi_register_slice_4/S_AXI]
connect_bd_intf_net -intf_net axi_dwidth_converter_1_M_AXI [get_bd_intf_pins axi_dwidth_converter_1/M_AXI] [get_bd_intf_pins axi_register_slice_5/S_AXI]
connect_bd_intf_net -intf_net axi_dwidth_converter_2_M_AXI [get_bd_intf_pins axi_dwidth_converter_2/M_AXI] [get_bd_intf_pins axi_register_slice_6/S_AXI]
connect_bd_intf_net -intf_net axi_dwidth_converter_3_M_AXI [get_bd_intf_pins axi_dwidth_converter_3/M_AXI] [get_bd_intf_pins axi_register_slice_7/S_AXI]
connect_bd_intf_net -intf_net axi_register_slice_0_M_AXI [get_bd_intf_pins axi_dwidth_converter_0/S_AXI] [get_bd_intf_pins axi_register_slice_0/M_AXI]
connect_bd_intf_net -intf_net axi_register_slice_1_M_AXI [get_bd_intf_pins axi_dwidth_converter_1/S_AXI] [get_bd_intf_pins axi_register_slice_1/M_AXI]
connect_bd_intf_net -intf_net axi_register_slice_2_M_AXI [get_bd_intf_pins axi_dwidth_converter_2/S_AXI] [get_bd_intf_pins axi_register_slice_2/M_AXI]
connect_bd_intf_net -intf_net axi_register_slice_3_M_AXI [get_bd_intf_pins axi_dwidth_converter_3/S_AXI] [get_bd_intf_pins axi_register_slice_3/M_AXI]
connect_bd_intf_net -intf_net axi_register_slice_4_M_AXI [get_bd_intf_pins axi_crossbar_0/S00_AXI] [get_bd_intf_pins axi_register_slice_4/M_AXI]
connect_bd_intf_net -intf_net axi_register_slice_5_M_AXI [get_bd_intf_pins axi_crossbar_0/S01_AXI] [get_bd_intf_pins axi_register_slice_5/M_AXI]
connect_bd_intf_net -intf_net axi_register_slice_6_M_AXI [get_bd_intf_pins axi_crossbar_0/S02_AXI] [get_bd_intf_pins axi_register_slice_6/M_AXI]
connect_bd_intf_net -intf_net axi_register_slice_7_M_AXI [get_bd_intf_pins axi_crossbar_0/S03_AXI] [get_bd_intf_pins axi_register_slice_7/M_AXI]
connect_bd_intf_net -intf_net axi_register_slice_8_M_AXI [get_bd_intf_ports M0_AXI] [get_bd_intf_pins axi_register_slice_8/M_AXI]
# Create port connections
connect_bd_net -net S0_AXI_ACLK [get_bd_ports S0_AXI_ACLK] [get_bd_pins axi_dwidth_converter_0/s_axi_aclk] [get_bd_pins axi_dwidth_converter_1/s_axi_aclk] [get_bd_pins axi_dwidth_converter_2/s_axi_aclk] [get_bd_pins axi_dwidth_converter_3/s_axi_aclk] [get_bd_pins axi_register_slice_0/aclk] [get_bd_pins axi_register_slice_1/aclk] [get_bd_pins axi_register_slice_2/aclk] [get_bd_pins axi_register_slice_3/aclk]
connect_bd_net -net S0_AXI_ARESETN_1 [get_bd_ports S0_AXI_ARESETN] [get_bd_pins axi_dwidth_converter_0/s_axi_aresetn] [get_bd_pins axi_dwidth_converter_1/s_axi_aresetn] [get_bd_pins axi_dwidth_converter_2/s_axi_aresetn] [get_bd_pins axi_dwidth_converter_3/s_axi_aresetn] [get_bd_pins axi_register_slice_0/aresetn] [get_bd_pins axi_register_slice_1/aresetn] [get_bd_pins axi_register_slice_2/aresetn] [get_bd_pins axi_register_slice_3/aresetn]
connect_bd_net -net M0_AXI_ACLK_1 [get_bd_ports M0_AXI_ACLK] [get_bd_pins axi_crossbar_0/aclk] [get_bd_pins axi_dwidth_converter_0/m_axi_aclk] [get_bd_pins axi_dwidth_converter_1/m_axi_aclk] [get_bd_pins axi_dwidth_converter_2/m_axi_aclk] [get_bd_pins axi_dwidth_converter_3/m_axi_aclk] [get_bd_pins axi_register_slice_4/aclk] [get_bd_pins axi_register_slice_5/aclk] [get_bd_pins axi_register_slice_6/aclk] [get_bd_pins axi_register_slice_7/aclk] [get_bd_pins axi_register_slice_8/aclk]
connect_bd_net -net M0_AXI_ARESETN_1 [get_bd_ports M0_AXI_ARESETN] [get_bd_pins axi_crossbar_0/aresetn] [get_bd_pins axi_dwidth_converter_0/m_axi_aresetn] [get_bd_pins axi_dwidth_converter_1/m_axi_aresetn] [get_bd_pins axi_dwidth_converter_2/m_axi_aresetn] [get_bd_pins axi_dwidth_converter_3/m_axi_aresetn] [get_bd_pins axi_register_slice_4/aresetn] [get_bd_pins axi_register_slice_5/aresetn] [get_bd_pins axi_register_slice_6/aresetn] [get_bd_pins axi_register_slice_8/aresetn]
# Create address segments
assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S0_AXI] [get_bd_addr_segs M0_AXI/Reg] -force
assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S1_AXI] [get_bd_addr_segs M0_AXI/Reg] -force
assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S2_AXI] [get_bd_addr_segs M0_AXI/Reg] -force
assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S3_AXI] [get_bd_addr_segs M0_AXI/Reg] -force
# Restore current instance
current_bd_instance $oldCurInst
validate_bd_design
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""
top/x400/ip/x4xx_ps_rfdc_bd/common/regmap/common_regs.v
+509
View File
@@ -0,0 +1,509 @@
//
// Copyright 2021 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: common_regs
// Description:
// Common registers definition within the x4xx_ps_rfdc_bd between
// different x4xx variants.
//XmlParse xml_on
//<regmap name="AXI_HPM0_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
// <info>
// This is the map for the register space that the Processing System's
// M_AXI_HPM0_FPD port (AXI4 master interface) has access to.
// This port has a 40-bit address bus.
// </info>
// <group name="COMMON">
// <window name="RPU" offset="0x0080000000" size="0x00010000">
// <info>Space reserved for RPU access</info>
// </window>
// <window name="JTAG_ENGINE" offset="0x1000000000" size="0x1000">
// <info>Register space for the JTAG engine for MB CPLD programming.</info>
// </window>
// <window name="RESERVED" offset="0x100003F000" size="0x1000">
// <info>Register space reserved for future use.</info>
// </window>
// <window name="MPM_ENDPOINT" offset="0x1000080000" size="0x20000"
// targetregmap="PL_CPLD_REGMAP">
// <info>MPM endpoint fro MB/DB communication.</info>
// </window>
// <window name="CORE_REGS" offset="0x10000A0000" size="0x4000"
// targetregmap="CORE_REGS_REGMAP">
// <info>Register space reserved for mboard-regs (Core).</info>
// </window>
// <window name="INT_ETH_DMA" offset="0x10000A4000" size="0x6000"
// targetregmap="ETH_DMA_CTRL_REGMAP">
// <info>AXI DMA engine for internal Ethernet interface.</info>
// </window>
// <window name="INT_ETH_REGS" offset="0x10000AA000" size="0x2000">
// <info>Misc. registers for internal Ethernet.</info>
// </window>
// <window name="RFDC" offset="0x1000100000" size="0x40000">
// <info>Register space occupied by the Xilinx RFDC IP block.</info>
// </window>
// <window name="RFDC_REGS" offset="0x1000140000" size="0x20000"
// targetregmap="RFDC_REGS_REGMAP">
// <info>Register space for RFDC control/status registers.</info>
// </window>
// </group>
//</regmap>
//
//<regmap name="ETH_DMA_CTRL_REGMAP" readablestrobes="false" generatevhdl="true" generateverilog="false" ettusguidelines="true">
// <info>
// This is the map that the nixge driver uses in Ethernet DMA to
// move data between the Processing System's architecture and the fabric.
// This map is a combination of two main components: a Xilix AXI DMA engine
// and some registers for MAC/PHY control.
// </info>
// <group name="ETH_DMA_CTRL">
// <window name="AXI_DMA_CTRL" offset="0x0" size="0x4000">
// <info>
// Refer to Xilinx' AXI DMA v7.1 IP product guide for further
// information on this register map:
// https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf
// </info>
// </window>
// <window name="ETH_IO_CTRL" offset="0x4000" size="0x2000">
// <info>MAC/PHY control for the Ethernet interface.</info>
// </window>
// </group>
//</regmap>
//<regmap name="PL_DMA_MASTER_REGMAP" readablestrobes="false" generatevhdl="true" generateverilog="false" ettusguidelines="true">
// <info>
// This is a regmap to document the different ports that have access to the PS system memory.
// Each port may have different restrictions on system memory. See the corresponding window
// for details
// </info>
// <group name="HPC0_DMA">
// <window name="AXI_HPC0_WINDOW" offset="0x0" size="0x10000000000">
// <info>
// The HPC0 port of the PS is used for general purpose cache-coherent accesses
// to the PS system memory. Different applications may use it for different
// purposes. Its access is configured as follows: {br}
// {table border="1"}
// {tr}{th}Offset{/th} {th}Size{/th} {th}Description{/th}{tr}
// {tr}{td}0x000800000000{/td}{td}0x000800000000{/td}{td}DDR_HIGH{/td}{tr}
// {tr}{td}0x00000000{/td} {td}0x80000000{/td} {td}DDR_LOW{/td}{tr}
// {tr}{td}0xFF000000{/td} {td}0x01000000{/td} {td}LPS_OCM{/td}{tr}
// {tr}{td}0xC0000000{/td} {td}0x20000000{/td} {td}QSPI{/td}{tr}
// {/table}
// </info>
// </window>
// </group>
// <group name="HPC1_DMA">
// <window name="AXI_HPC1_WINDOW" offset="0x0" size="0x1000000000">
// <info>
// The HPC1 port of the PS is connected to the Ethernet DMA module. Three slave
// interfaces are lumped together in this window: scatter-gather, dma-rx, and dma-tx.
// Its access is configured as follows: {br}
// {table border="1"}
// {tr}{th}Offset{/th} {th}Size{/th} {th}Description{/th}{tr}
// {tr}{td}0x000800000000{/td}{td}0x000800000000{/td}{td}DDR_HIGH{/td}{tr}
// {tr}{td}0x00000000{/td} {td}0x80000000{/td} {td}DDR_LOW{/td}{tr}
// {tr}{td}0xC0000000{/td} {td}0x20000000{/td} {td}QSPI{/td}{tr}
// {/table}
// </info>
// </window>
// </group>
//</regmap>
//<regmap name="RFDC_REGS_REGMAP" readablestrobes="false" generatevhdl="true" generateverilog="true" ettusguidelines="true">
// <group name="RFDC_REGS">
// <regtype name="RF_RESET_CONTROL_REGTYPE" size="32">
// <info>
// Control register for the RF reset controller.
// Verify the FSM ID before polling starting any reset sequence.
// To use the SW reset triggers: Wait until DB*_DONE is de-asserted.
// Assert either the *_RESET or *_ENABLE bitfields.
// Wait until DB*_DONE is asserted to release the trigger.
// The DB*_DONE signal should then de-assert.{BR/}
// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is
// merely for documentation.{/b}
// </info>
// <bitfield name="FSM_RESET" range="0">
// <info>
// Write a '1' to this bit to reset the RF reset controller.
// Write a '0' once db0_fsm_reset_done asserts.
// </info>
// </bitfield>
// <bitfield name="ADC_RESET" range="4">
// <info>
// Write a '1' to this bit to trigger a reset for the
// daughterboard 0 ADC chain. Write a '0' once db0_adc_seq_done
// is asserted.
// </info>
// </bitfield>
// <bitfield name="ADC_ENABLE" range="5">
// <info>
// Write a '1' to this bit to trigger the enable sequence for
// the daughterboard 0 ADC chain. Write a '0' once
// db0_adc_seq_done is asserted.
// </info>
// </bitfield>
// <bitfield name="DAC_RESET" range="8">
// <info>
// Write a '1' to this bit to trigger a reset for the
// daughterboard 0 DAC chain. Write a '0' once db0_dac_seq_done
// is asserted.
// </info>
// </bitfield>
// <bitfield name="DAC_ENABLE" range="9">
// <info>
// Write a '1' to this bit to trigger the enable sequence for
// the daughterboard 0 DAC chain. Write a '0' once
// db0_dac_seq_done is asserted.
// </info>
// </bitfield>
// </regtype>
//
// <regtype name="RF_RESET_STATUS_REGTYPE" size="32" writable="false">
// <info>
// Status register for the RF reset controller.
// Verify the FSM ID before polling starting any reset sequence.
// Refer to RF*_RESET_CONTROL_REG for instructions on how to use
// the status bits in this register.{BR/}
// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is
// merely for documentation.{/b}
// </info>
// <bitfield name="FSM_RESET_DONE" range="3">
// <info>
// This bit asserts ('1') when the DB0 RF reset controller FSM
// reset sequence is completed. The bitfield deasserts ('0')
// after deasserting db0_fsm_reset.
// </info>
// </bitfield>
// <bitfield name="ADC_SEQ_DONE" range="7">
// <info>
// This bit asserts ('1') when the DB0 ADC chain reset sequence
// is completed. The bitfield deasserts ('0') after
// deasserting the issued triggered (enable or reset).
// </info>
// </bitfield>
// <bitfield name="DAC_SEQ_DONE" range="11">
// <info>
// This bit asserts ('1') when the DB0 DAC chain reset sequence
// is completed. The bitfield deasserts ('0') after
// deasserting the issued triggered (enable or reset).
// </info>
// </bitfield>
// </regtype>
//
// <regtype name="RF_AXI_STATUS_REGTYPE" size="32" writable="false">
// <info>
// Status register for the RF AXI-Stream interfaces.{BR/}
// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is
// merely for documentation.{/b}
// </info>
// <bitfield name="RFDC_DAC_TREADY" range="1..0">
// <info>
// This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream
// TReady handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_DAC_TVALID" range="3..2">
// <info>
// This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream
// TValid handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_Q_TREADY" range="5..4">
// <info>
// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
// TReady handshake signals (Q portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_I_TREADY" range="7..6">
// <info>
// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
// TReady handshake signals (I portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_Q_TVALID" range="9..8">
// <info>
// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
// TValid handshake signals (Q portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_I_TVALID" range="11..10">
// <info>
// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
// TValid handshake signals (I portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="USER_ADC_TVALID" range="13..12">
// <info>
// This bitfield is wired to the user's ADC (DB0) AXI-Stream
// TValid handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// <bitfield name="USER_ADC_TREADY" range="15..14">
// <info>
// This bitfield is wired to the user's ADC (DB0) AXI-Stream
// TReady handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_DAC_TREADY_DB1" range="17..16">
// <info>
// This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream
// TReady handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_DAC_TVALID_DB1" range="19..18">
// <info>
// This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream
// TValid handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_Q_TREADY_DB1" range="21..20">
// <info>
// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
// TReady handshake signals (Q portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_I_TREADY_DB1" range="23..22">
// <info>
// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
// TReady handshake signals (I portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_Q_TVALID_DB1" range="25..24">
// <info>
// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
// TValid handshake signals (Q portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_I_TVALID_DB1" range="27..26">
// <info>
// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
// TValid handshake signals (I portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="USER_ADC_TVALID_DB1" range="29..28">
// <info>
// This bitfield is wired to the user's ADC (DB1) AXI-Stream
// TValid handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// <bitfield name="USER_ADC_TREADY_DB1" range="31..30">
// <info>
// This bitfield is wired to the user's ADC (DB1) AXI-Stream
// TReady handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// </regtype>
//
// <enumeratedtype name="FABRIC_DSP_BW_ENUM" showhex="true">
// <value name="FABRIC_DSP_BW_NONE" integer="0"/>
// <value name="FABRIC_DSP_BW_100M" integer="100"/>
// <value name="FABRIC_DSP_BW_200M" integer="200"/>
// <value name="FABRIC_DSP_BW_400M" integer="400"/>
// <value name="FABRIC_DSP_BW_FULL" integer="1000"/>
// </enumeratedtype>
//
// <regtype name="FABRIC_DSP_REGTYPE" size="32" writable="false">
// <info>
// This register provides information to the driver on the type
// of DSP that is instantiated in the fabric.{BR/}
// The X410 platform supports multiple RF daughterboards, each requiring
// a different fabric RF DSP chain that works with specific RFDC settings.
// Each bandwidth DSP chain has a unique identifier (BW in MHz), this
// information is conveyed in this register to let the driver
// configure the RFDC with the proper settings.
// Also, channel count for the DSP module is included.{BR/}
// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is
// merely for documentation.{/b}
// </info>
// <bitfield name="FABRIC_DSP_RX_CNT" range="3..0" initialvalue="0">
// <info>Fabric DSP RX channel count for daughterboard 0.</info>
// </bitfield>
// <bitfield name="FABRIC_DSP_TX_CNT" range="7..4" initialvalue="0">
// <info>Fabric DSP TX channel count for daughterboard 0.</info>
// </bitfield>
// <bitfield name="FABRIC_DSP_RESERVED" range="9..8" initialvalue="0">
// <info>Reserved for future use.</info>
// </bitfield>
// <bitfield name="FABRIC_DSP_RX_CNT_DB1" range="13..10" initialvalue="0">
// <info>Fabric DSP RX channel count for daughterboard 0.</info>
// </bitfield>
// <bitfield name="FABRIC_DSP_TX_CNT_DB1" range="17..14" initialvalue="0">
// <info>Fabric DSP TX channel count for daughterboard 0.</info>
// </bitfield>
// <bitfield name="FABRIC_DSP_RESERVED_DB1" range="19..18" initialvalue="0">
// <info>Reserved for future use.</info>
// </bitfield>
// <bitfield name="FABRIC_DSP_BW" range="31..20" type="FABRIC_DSP_BW_ENUM" initialvalue="FABRIC_DSP_BW_NONE">
// <info>Fabric DSP BW in MHz for both daughterboards.</info>
// </bitfield>
// </regtype>
//
// <regtype name="RFDC_INFO_REGTYPE" size="32" writable="false">
// <info>
// This register provides information about how the RFDC is connected to
// the rest of the fabric.{BR/}
// Specifically, between the actual RFDC and the RFNoC infrastructure,
// there may be additional resampling (if the RFDC resampler cannot handle
// all the resampling itself) and it is important to know how wide the
// connection from the RFDC gearbox FIFO to the rest of the design is.
// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is
// merely for documentation.{/b}
// </info>
// <bitfield name="RFDC_INFO_XTRA_RESAMP" range="3..0" initialvalue="1">
// <info>Additional resampling happening outside the RFDC for daughterboard 0.</info>
// </bitfield>
// <bitfield name="RFDC_INFO_SPC_RX" range="6..4" initialvalue="1">
// <info>Log2 of SPC value for RX connection (RFDC into fabric) for daughterboard 0.</info>
// </bitfield>
// <bitfield name="RFDC_INFO_SPC_TX" range="9..7" initialvalue="1">
// <info>Log2 of SPC value for TX connection (fabric into RFDC) for daughterboard 0.</info>
// </bitfield>
// <bitfield name="RFDC_INFO_XTRA_RESAMP_DB1" range="19..16" initialvalue="1">
// <info>Additional resampling happening outside the RFDC for daughterboard 0.</info>
// </bitfield>
// <bitfield name="RFDC_INFO_SPC_RX_DB1" range="22..20" initialvalue="1">
// <info>Log2 of SPC value for RX connection (RFDC into fabric) for daughterboard 1.</info>
// </bitfield>
// <bitfield name="RFDC_INFO_SPC_TX_DB1" range="25..23" initialvalue="1">
// <info>Log2 of SPC value for TX connection (fabric into RFDC) for daughterboard 1.</info>
// </bitfield>
// </regtype>
//
// <regtype name="ADC_TILEMAP_REGTYPE" size="32" writable="false">
// <info>
// This register describes how the ADCs map to the respective tiles. It
// lets us designate an ADC as channel 0, channel 1, etc. depending on
// how those channels are externally connected to the RFSoC.{BR/}
//
// For every channel, this register stores the tile number and the block
// number of the converter. This can be used to then address the correct
// converter in the various Xilinx interfaces/APIs.
// </info>
// <bitfield name="ADC_TILEMAP_DB0_CHAN0_TILE" range="1..0" initialvalue="0">
// <info>Tile number of the ADC for channel 0, daughterboard 0.</info>
// </bitfield>
// <bitfield name="ADC_TILEMAP_DB0_CHAN0_BLOCK" range="3..2" initialvalue="0">
// <info>Block number (within the tile) of the ADC for channel 0, daughterboard 0.</info>
// </bitfield>
// <bitfield name="ADC_TILEMAP_DB0_CHAN1_TILE" range="5..4" initialvalue="0">
// <info>Tile number of the ADC for channel 1, daughterboard 0.</info>
// </bitfield>
// <bitfield name="ADC_TILEMAP_DB0_CHAN1_BLOCK" range="7..6" initialvalue="0">
// <info>Block number (within the tile) of the ADC for channel 1, daughterboard 0.</info>
// </bitfield>
// <bitfield name="ADC_TILEMAP_DB0_CHAN2_TILE" range="9..8" initialvalue="0">
// <info>Tile number of the ADC for channel 2, daughterboard 0.</info>
// </bitfield>
// <bitfield name="ADC_TILEMAP_DB0_CHAN2_BLOCK" range="11..10" initialvalue="0">
// <info>Block number (within the tile) of the ADC for channel 2, daughterboard 0.</info>
// </bitfield>
// <bitfield name="ADC_TILEMAP_DB0_CHAN3_TILE" range="13..12" initialvalue="0">
// <info>Tile number of the ADC for channel 3, daughterboard 0.</info>
// </bitfield>
// <bitfield name="ADC_TILEMAP_DB0_CHAN3_BLOCK" range="15..14" initialvalue="0">
// <info>Block number (within the tile) of the ADC for channel 3, daughterboard 0.</info>
// </bitfield>
// <bitfield name="ADC_TILEMAP_DB1_CHAN0_TILE" range="17..16" initialvalue="0">
// <info>Tile number of the ADC for channel 0, daughterboard 1.</info>
// </bitfield>
// <bitfield name="ADC_TILEMAP_DB1_CHAN0_BLOCK" range="19..18" initialvalue="0">
// <info>Block number (within the tile) of the ADC for channel 0, daughterboard 1.</info>
// </bitfield>
// <bitfield name="ADC_TILEMAP_DB1_CHAN1_TILE" range="21..20" initialvalue="0">
// <info>Tile number of the ADC for channel 1, daughterboard 1.</info>
// </bitfield>
// <bitfield name="ADC_TILEMAP_DB1_CHAN1_BLOCK" range="23..22" initialvalue="0">
// <info>Block number (within the tile) of the ADC for channel 1, daughterboard 1.</info>
// </bitfield>
// <bitfield name="ADC_TILEMAP_DB1_CHAN2_TILE" range="25..24" initialvalue="0">
// <info>Tile number of the ADC for channel 2, daughterboard 1.</info>
// </bitfield>
// <bitfield name="ADC_TILEMAP_DB1_CHAN2_BLOCK" range="27..26" initialvalue="0">
// <info>Block number (within the tile) of the ADC for channel 2, daughterboard 1.</info>
// </bitfield>
// <bitfield name="ADC_TILEMAP_DB1_CHAN3_TILE" range="29..28" initialvalue="0">
// <info>Tile number of the ADC for channel 3, daughterboard 1.</info>
// </bitfield>
// <bitfield name="ADC_TILEMAP_DB1_CHAN3_BLOCK" range="31..30" initialvalue="0">
// <info>Block number (within the tile) of the ADC for channel 3, daughterboard 1.</info>
// </bitfield>
// </regtype>
// <regtype name="DAC_TILEMAP_REGTYPE" size="32" writable="false">
// <info>
// This register describes how the DACs map to the respective tiles. It
// lets us designate an DAC as channel 0, channel 1, etc. depending on
// how those channels are externally connected to the RFSoC.{BR/}
//
// For every channel, this register stores the tile number and the block
// number of the converter. This can be used to then address the correct
// converter in the various Xilinx interfaces/APIs.
// </info>
// <bitfield name="DAC_TILEMAP_DB0_CHAN0_TILE" range="1..0" initialvalue="0">
// <info>Tile number of the DAC for channel 0, daughterboard 0.</info>
// </bitfield>
// <bitfield name="DAC_TILEMAP_DB0_CHAN0_BLOCK" range="3..2" initialvalue="0">
// <info>Block number (within the tile) of the DAC for channel 0, daughterboard 0.</info>
// </bitfield>
// <bitfield name="DAC_TILEMAP_DB0_CHAN1_TILE" range="5..4" initialvalue="0">
// <info>Tile number of the DAC for channel 1, daughterboard 0.</info>
// </bitfield>
// <bitfield name="DAC_TILEMAP_DB0_CHAN1_BLOCK" range="7..6" initialvalue="0">
// <info>Block number (within the tile) of the DAC for channel 1, daughterboard 0.</info>
// </bitfield>
// <bitfield name="DAC_TILEMAP_DB0_CHAN2_TILE" range="9..8" initialvalue="0">
// <info>Tile number of the DAC for channel 2, daughterboard 0.</info>
// </bitfield>
// <bitfield name="DAC_TILEMAP_DB0_CHAN2_BLOCK" range="11..10" initialvalue="0">
// <info>Block number (within the tile) of the DAC for channel 2, daughterboard 0.</info>
// </bitfield>
// <bitfield name="DAC_TILEMAP_DB0_CHAN3_TILE" range="13..12" initialvalue="0">
// <info>Tile number of the DAC for channel 3, daughterboard 0.</info>
// </bitfield>
// <bitfield name="DAC_TILEMAP_DB0_CHAN3_BLOCK" range="15..14" initialvalue="0">
// <info>Block number (within the tile) of the DAC for channel 3, daughterboard 0.</info>
// </bitfield>
// <bitfield name="DAC_TILEMAP_DB1_CHAN0_TILE" range="17..16" initialvalue="0">
// <info>Tile number of the DAC for channel 0, daughterboard 1.</info>
// </bitfield>
// <bitfield name="DAC_TILEMAP_DB1_CHAN0_BLOCK" range="19..18" initialvalue="0">
// <info>Block number (within the tile) of the DAC for channel 0, daughterboard 1.</info>
// </bitfield>
// <bitfield name="DAC_TILEMAP_DB1_CHAN1_TILE" range="21..20" initialvalue="0">
// <info>Tile number of the DAC for channel 1, daughterboard 1.</info>
// </bitfield>
// <bitfield name="DAC_TILEMAP_DB1_CHAN1_BLOCK" range="23..22" initialvalue="0">
// <info>Block number (within the tile) of the DAC for channel 1, daughterboard 1.</info>
// </bitfield>
// <bitfield name="DAC_TILEMAP_DB1_CHAN2_TILE" range="25..24" initialvalue="0">
// <info>Tile number of the DAC for channel 2, daughterboard 1.</info>
// </bitfield>
// <bitfield name="DAC_TILEMAP_DB1_CHAN2_BLOCK" range="27..26" initialvalue="0">
// <info>Block number (within the tile) of the DAC for channel 2, daughterboard 1.</info>
// </bitfield>
// <bitfield name="DAC_TILEMAP_DB1_CHAN3_TILE" range="29..28" initialvalue="0">
// <info>Tile number of the DAC for channel 3, daughterboard 1.</info>
// </bitfield>
// <bitfield name="DAC_TILEMAP_DB1_CHAN3_BLOCK" range="31..30" initialvalue="0">
// <info>Block number (within the tile) of the DAC for channel 3, daughterboard 1.</info>
// </bitfield>
// </regtype>
//
//
// </group>
//</regmap>
//XmlParse xml_off
top/x400/ip/x4xx_ps_rfdc_bd/common/regmap/uhd_regs.v
+336
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@@ -0,0 +1,336 @@
//
// Copyright 2021 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: uhd_regs
// Description:
// Registers definition within the x4xx_ps_rfdc_bd IP.
//XmlParse xml_on
//<regmap name="CMAC_REGMAP" markdown="true" generateverilog="false">
// <group name="XILINX_CMAC_REGISTERS">
// <info>
// 100G MAC ethernet registers (Link 0) defined in the CMAC Manual starting on pg 187.
//
// - http://www.xilinx.com/support/documentation/ip_documentation/cmac_usplus/v2_4/pg203-cmac-usplus.pdf
//
// </info>
// </group>
//</regmap>
//XmlParse xml_on
//<regmap name="XGE_MAC_REGMAP" markdown="true" generateverilog="false">
// <group name="OPENCORE_XGE_REGISTERS">
// <info>
//
// 10G MAC ethernet registers defined in the USRP OSS distribution fpga/usrp3/lib/xge/doc/xge_mac_spec.pdf
//
// </info>
// </group>
//</regmap>
//<regmap name="DMA_REGMAP" markdown="true" generateverilog="false">
// <group name="XILINX_DMA_REGISTERS">
// <info>
// Scatter Gather DMA block defined in Xilinx DMA manual start on pg 11
//
// - https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf
//
// </info>
// </group>
//</regmap>
//<regmap name="NIXGE_REGMAP" markdown="true" generateverilog="false">
// <group name="XGE_MAC_WINDOW">
// <window name="XGE_MAC" offset="0x1000" size="0x1000" targetregmap="XGE_MAC_REGMAP"/>
// </group>
// <group name="XGE_MAC_REGS">
// <info>
// nixge (maps to 10g mac if present)
// </info>
// <register name="PORT_INFO" offset="0x0000">
// <bitfield name="COMPAT_NUM" range="31..24">
// <info>
// Constant indicating version for this space.
// Not used by the NIXGE driver (12/4/2020)
// </info>
// </bitfield>
// <bitfield name="ACTIVITY" range="17">
// <info>
// Generically this mirrors the activity LED. Specific meaning varies based on the MGT_PROTOCOL.
// </info>
// </bitfield>
// <bitfield name="LINK_UP" range="16">
// <info>
// Generically means that a connection with a peer has been established. Specific
// meaning varies based on the MGT_PROTOCOL.
// </info>
// </bitfield>
// <bitfield name="MGT_PROTOCOL" range="15..8">
// <info>
// Constant indicating what flavor of communication this port is using
//
// - 0 = NONE
// - 1 = 1GbE
// - 2 = 10GbE
// - 3 = Aurora
// - 4 = WhiteRabbit
// - 5 = 100GbE
//
// </info>
// </bitfield>
// <bitfield name="PORTNUM" range="7..0">
// <info>
// Constant indicating which port this register is hooked to
//
// - 0 = QSFP0
// - 1 = QSFP1
//
// </info>
// </bitfield>
// </register>
// <register name="MAC_CTRL_STATUS" offset="0x0004">
// <info>
// Definition of this register depends on Protocol
//
// **10GBE**
//
// *READ - Status*
//
// - 0 = status_crc_error
// - 1 = status_fragment_error
// - 2 = status_txdfifo_ovflow
// - 3 = status_txdfifo_udflow
// - 4 = status_rxdfifo_ovflow
// - 5 = status_rxdfifo_udflow
// - 6 = status_pause_frame_rx
// - 7 = status_local_fault
// - 8 = status_remote_fault
//
// *WRITE - Ctl*
//
// - 0 = ctrl_tx_enable
//
// **100 GBE**
//
// *READ - Status*
//
// - 0 = tx_ovfout - Sets if TX overflow reported by CMAC
// (Stays set till MAC is reset). This is a fatal error
// - 1 = tx_unfout - Sets if TX underflow reported by CMAC
// (Stays set till MAC is reset). This is a fatal error
// - 2 = stat_rx_aligned - goes high when CMAC has finished
// alignment, and is ready to start reception of traffic.
// - 3 = mac_dropped_packet - If the mac RX wants to push data(TVALID)
// but upstream is trying to hold(TREADY)off we drop a packet.
// Upstream circuitry should detect this when traffic is forked
// between CHDR and CPU, so this bit will only set if there is a
// HW design error.
// - 4 = auto_config_done - This bit goes high when the auto_config
// state machine finishes operation. It is very similiar to
// stat_rx_alligned, but waits for extra writes which occur
// after allignement to complete.
// - 24:16 = pause_mask - readable version of pause_mask bellow.
//
// *WRITE - Ctl*
//
// - 0 = auto_enable - Defaults to ON after reset - Enables a
// state machine that performs CMAC register writes to
// bring up the MAC without SW intervention.
// - 24:16 = pause_mask - A second layer of enables(the first being
// register in the CMAC) on the pause_request mechanic. Bits
// 7:0 of enable pause on PFC7:0. Bit 8 enables global pause
// request (not priority controlled). The mask is used for TX
// and RX.
// </info>
// </register>
// <register name="MAC_PHY_STATUS" offset="0x0008">
// <info>
//
// Definition of this register depends on Protocol
//
// **10GBE**
//
// *READ - Status *
//
// - 0 = core_status 0 - link_up
// - 1 = core_status 1
// - 2 = core_status 2
// - 3 = core_status 3
// - 4 = core_status 4
// - 5 = core_status 5
// - 6 = core_status 6
// - 7 = core_status 7
//
// **100 GBE**
//
// *READ - Status*
//
// - 0 = usr_tx_reset - TX PLL's have locked - The clock for the 100G mac isn't stable till this bit sets.
// - 1 = usr_rx_reset - RX PLL's have locked
//
// </info>
// </register>
// <register name="MAC_LED_CTL" offset="0x000C">
// <bitfield name="identify_enable" range="0">
// <info>
// When set identify_value is used to control the activity LED.
// When clear the activity LED set on any TX or RX traffic to the mgt
// </info>
// </bitfield>
// <bitfield name="identify_value" range="1">
// <info>
// When identify_enable is set, this value controls the activity LED.
// </info>
// </bitfield>
// </register>
// <register name="ETH_MDIO_BASE" offset="0x0010">
// <info>
// The x4xx family of products does not use MDIO.
// </info>
// </register>
// <register name="AURORA_OVERRUNS" offset="0x0020">
// <info>
// Only valid if the protocol is Aurora.
// </info>
// </register>
// <register name="AURORA_CHECKSUM_ERRORS" offset="0x0024">
// <info>
// Only valid if the protocol is Aurora.
// </info>
// </register>
// <register name="AURORA_BIST_CHECKER_SAMPS" offset="0x0028">
// <info>
// Only valid if the protocol is Aurora.
// </info>
// </register>
// <register name="AURORA_BIST_CHECKER_ERRORS" offset="0x002C">
// <info>
// Only valid if the protocol is Aurora.
// </info>
// </register>
// </group>
//</regmap>
//
//<regmap name="UIO_REGMAP" markdown="true" generateverilog="false">
// <group name="UIO_REGS">
// <info>
// UIO
// </info>
// <register name="IP" offset="0x0000">
// <info>
// Set this port's IP address
// </info>
// </register>
// <register name="UDP" offset="0x0004">
// <info>
// Set the UDP port for CHDR_traffic
// </info>
// </register>
// <register name="BRIDGE_MAC_LSB" offset="0x0010">
// <info>
// If BRIDGE_ENABLE is set use this MAC_ID
// </info>
// </register>
// <register name="BRIDGE_MAC_MSB" offset="0x0014">
// <info>
// If BRIDGE_ENABLE is set use this MAC_ID
// </info>
// </register>
// <register name="BRIDGE_IP" offset="0x0018">
// <info>
// If BRIDGE_ENABLE is set use this IP Address
// </info>
// </register>
// <register name="BRIDGE_UDP" offset="0x001C">
// <info>
// If BRIDGE_ENABLE is set use this UDP Port for CHDR_traffic
// </info>
// </register>
// <register name="BRIDGE_ENABLE" offset="0x0020">
// <info>
// Bit 0 Controls the following logic
//
//```verilog
// always_comb begin : bridge_mux
// my_mac = bridge_en ? bridge_mac_reg : mac_reg;
// my_ip = bridge_en ? bridge_ip_reg : ip_reg;
// my_udp_chdr_port = bridge_en ? bridge_udp_port : udp_port;
// end
//```
//
// </info>
// </register>
// <register name="CHDR_DROPPED" offset="0x0030">
// <info>
// Count the number of Packets dropped that were addressed to the CHDR section.
// </info>
// </register>
// <register name="CPU_DROPPED" offset="0x0034">
// <info>
// Count the number of Packets dropped that were addressed to us, but not to the CHDR section.
// </info>
// </register>
// <register name="PAUSE" offset="0x0038">
// <bitfield name="pause_set" range="15..0">
// <info>
// If the fullness of the CHDR_FIFO in ETH_W words exceeds this value request an ethernet pause. This feature is only
// used with 100Gb ethernet
// </info>
// </bitfield>
// <bitfield name="pause_clear" range="31..16">
// <info>
// If the fullness of the CHDR_FIFO in ETH_W words falls bellow this value stop requesting an ethernet pause.
// *Pause clear must be less than pause set or terrible things will happen.*
// The clearing of the pause request causes the MAC to send a request to resume traffic. This feature is only
// used with 100Gb ethernet
// </info>
// </bitfield>
// </register>
// </group>
//</regmap>
//<regmap name="QSFP_REGMAP" markdown="true" generateverilog="false">
// <group name="QSFP_WINDOWS">
// <info>
// Register space for a single QSFP Communication port. This currently breaks into 2 possible configurations
//
// - 1X10GB Ethernet - Using OpenCore XGE MAC
// - 1x100GB Ethernet - Using Xilinx CMAC
// - (future possible) - Xilinx Aurora (various rates and lane widths)
// - (future possible) - 4X10GB Ethernet
//
// </info>
// <window name="ETH_DMA" offset="0x000" size="0x4000" targetregmap="DMA_REGMAP"/>
// <window name="NIXGE" offset="0x8000" size="0x2000" targetregmap="NIXGE_REGMAP"/>
// <window name="UIO" offset="0xA000" size="0x2000" targetregmap="UIO_REGMAP"/>
// <window name="CMAC" offset="0xC000" size="0x2000" targetregmap="CMAC_REGMAP"/>
// </group>
//</regmap>
//<regmap name="AXI_HPM0_REGMAP" markdown="true" generateverilog="false">
// <group name="UHD_ONLY">
// <info>
// - 0_0 indicates QSFP0 - Lane0 or a 4 LANE QSFP0
// - 0_1 indicates QSFP0 - Lane1
// - 0_2 indicates QSFP0 - Lane2
// - 0_3 indicates QSFP0 - Lane3
// - 1_0 indicates QSFP1 - Lane0 or a 4 LANE QSFP1
// - 1_1 indicates QSFP1 - Lane1
// - 1_2 indicates QSFP1 - Lane2
// - 1_3 indicates QSFP1 - Lane3
// </info>
// <window name="QSFP_0_0" offset="0x1200000000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// <window name="QSFP_0_1" offset="0x1200010000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// <window name="QSFP_0_2" offset="0x1200020000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// <window name="QSFP_0_3" offset="0x1200030000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// <window name="QSFP_1_0" offset="0x1200040000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// <window name="QSFP_1_1" offset="0x1200050000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// <window name="QSFP_1_2" offset="0x1200060000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// <window name="QSFP_1_3" offset="0x1200070000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// </group>
//</regmap>
//XmlParse xml_off
top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/Makefile.inc
+52
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_X4XX_PS_RFDC_ORIG_SRCS = $(addprefix $(IP_DIR)/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/, \
x410_ps_rfdc_bd.tcl \
)
IP_X4XX_PS_RFDC_HDL_SRCS = $(addprefix $(BASE_DIR)/x400/rf/common/, \
capture_sysref.v \
rf_nco_reset.vhd \
rf_reset.vhd \
sync_wrapper.v \
axis_mux.vhd \
gpio_to_axis_mux.vhd \
) \
$(addprefix $(BASE_DIR)/x400/rf/x410/, \
x410_rf_reset_controller.vhd \
x410_clock_gates.vhd \
) \
$(addprefix $(BASE_DIR)/../lib/control/, \
synchronizer.v \
synchronizer_impl.v \
) \
$(addprefix $(BASE_DIR)/x400/regmap/x410/, PkgRFDC_REGS_REGMAP.vhd )
IP_X4XX_PS_RFDC_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/x410_ps_rfdc_bd/, \
x410_ps_rfdc_bd.tcl \
)
IP_X4XX_PS_RFDC_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/x410_ps_rfdc_bd/, \
x410_ps_rfdc_bd/x410_ps_rfdc_bd.bd \
)
BD_X4XX_PS_RFDC_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/x410_ps_rfdc_bd/, \
x410_ps_rfdc_bd.bd.out \
x410_ps_rfdc_bd/x410_ps_rfdc_bd_ooc.xdc \
x410_ps_rfdc_bd/synth/x410_ps_rfdc_bd.v \
)
EMPTY_IP_SRCS =
.INTERMEDIATE: IP_X4XX_PS_RFDC_BD_TRGT
$(IP_X4XX_PS_RFDC_BD_SRCS) $(BD_X4XX_PS_RFDC_BD_OUTS) $(IP_X4XX_PS_RFDC_BDTCL_SRCS): IP_X4XX_PS_RFDC_BD_TRGT
@:
IP_X4XX_PS_RFDC_BD_TRGT: $(IP_X4XX_PS_RFDC_ORIG_SRCS)
$(call BUILD_VIVADO_BDTCL,x410_ps_rfdc_bd,$(ARCH),$(PART_ID),$(IP_DIR)/x4xx_ps_rfdc_bd,$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi,$(IP_X4XX_PS_RFDC_HDL_SRCS))
top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/hdl_sources.tcl
+14
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set script_loc [file normalize [info script]]
set script_dir [file dirname $script_loc]
read_verilog -library work $script_dir/../../../rf/common/capture_sysref.v
read_verilog -library work $script_dir/../../../../../lib/control/synchronizer.v
read_verilog -library work $script_dir/../../../../../lib/control/synchronizer_impl.v
read_verilog -library work $script_dir/../../../rf/common/sync_wrapper.v
read_vhdl -library work $script_dir/../../../rf/common/rf_nco_reset.vhd
read_vhdl -library work $script_dir/../../../regmap/x410/PkgRFDC_REGS_REGMAP.vhd
read_vhdl -library work $script_dir/../../../rf/x410/x410_rf_reset_controller.vhd
read_vhdl -library work $script_dir/../../../rf/common/rf_reset.vhd
read_vhdl -library work $script_dir/../../../rf/x410/x410_clock_gates.vhd
read_vhdl -library work $script_dir/../../../rf/common/axis_mux.vhd
read_vhdl -library work $script_dir/../../../rf/common/gpio_to_axis_mux.vhd
top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/regmap/x410_rfdc_regs.v
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//
// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: x410_rfdc_regs
// Description:
// Registers definition within the x4xx_ps_rfdc_bd IP.
//XmlParse xml_on
//<top name="X410_FPGA">
// <ports>
// <info>
// This section lists all common Processing System ports through
// which the register maps in this project are accessed. Each input
// port to the fabric will point to a regmap.
// </info>
// <port name="ARM_M_AXI_HPM0" targetregmap="AXI_HPM0_REGMAP">
// <info>
// This is the main AXI4-Lite master interface that the PS
// exposes to the kernel to interact with the FPGA fabric.
// There are multiple endpoints connected to this interface.
// </info>
// </port>
// <port name="ARM_S_AXI_HPC0" sourcewindow="PL_DMA_MASTER_REGMAP|AXI_HPC0_WINDOW">
// <info>
// This is one of the two cache-coherent AXI slave ports available to
// communicate from the fabric (master) to the PS (slave).
// </info>
// </port>
// <port name="ARM_S_AXI_HPC1" sourcewindow="PL_DMA_MASTER_REGMAP|AXI_HPC1_WINDOW">
// <info>
// This is one of the two cache-coherent AXI slave ports available to
// communicate from the fabric (master) to the PS (slave).
// </info>
// </port>
// <port name="ARM_SPI1_CS3" targetregmap="MB_CPLD_PS_REGMAP">
// <info>
// This is the SPI1 interface
// (see <a href="https://www.xilinx.com/html_docs/registers/ug1087/mod___spi.html" target="_blank">Zynq UltraScale+ Devices Register Reference</a>)
// of the PS.
// With chip select 3 enabled transactions are targeted for the PS MB CPLD register interface linked here.{br}
// The request format on SPI is defined as.{br}
// {b}Write request:{/b}
// {ul}
// {li}1'b1 = write
// {li}15 bit address
// {li}32 bit data (MOSI)
// {li}8 bit processing gap
// {li}5 bit padding
// {li}1 bit ack
// {li}2 bit status
// {/ul}
// {b}Read request:{/b}
// {ul}
// {li}1'b0 = read
// {li}15 bit address
// {li}8 bit processing gap
// {li}32 bit data (MISO)
// {li}5 bit padding
// {li}1 bit ack
// {li}2 bit status
// {/ul}
// </info>
// </port>
// </ports>
// <regmapcfg readablestrobes="false">
// <map name="AXI_HPM0_REGMAP"/>
// <map name="MB_CPLD_PS_REGMAP"/>
// </regmapcfg>
//</top>
//
//<regmap name="RFDC_REGS_REGMAP" readablestrobes="false" generatevhdl="true" generateverilog="true" ettusguidelines="true">
// <group name="RFDC_REGS">
// <info>
// These are the registers located within the RFDC block design
// that provide control and status support for the RF chain.
// </info>
//
// <window name="MMCM" offset="0x0" size="0x10000">
// <info>
// Register space for controlling the data clock MMCM instance
// within the RFDC block design.
// Refer to Xilinx' Clocking Wizard v6.0 Product Guide for the
// regiter space description in chapter 2.
// (https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v6_0/pg065-clk-wiz.pdf)
// </info>
// </window>
//
// <register name="INVERT_DB0_IQ_REG" offset="0x10000" size="32">
// <info>Control register for inverting I/Q data.</info>
// <bitfield name="INVERT_DB0_ADC0_IQ" range="0"/>
// <bitfield name="INVERT_DB0_ADC1_IQ" range="1"/>
// <bitfield name="INVERT_DB0_ADC2_IQ" range="2"/>
// <bitfield name="INVERT_DB0_ADC3_IQ" range="3"/>
// <bitfield name="INVERT_DB0_DAC0_IQ" range="8"/>
// <bitfield name="INVERT_DB0_DAC1_IQ" range="9"/>
// <bitfield name="INVERT_DB0_DAC2_IQ" range="10"/>
// <bitfield name="INVERT_DB0_DAC3_IQ" range="11"/>
// </register>
//
// <register name="INVERT_DB1_IQ_REG" offset="0x10800" size="32">
// <info>Control register for inverting I/Q data.</info>
// <bitfield name="INVERT_DB1_ADC0_IQ" range="0"/>
// <bitfield name="INVERT_DB1_ADC1_IQ" range="1"/>
// <bitfield name="INVERT_DB1_ADC2_IQ" range="2"/>
// <bitfield name="INVERT_DB1_ADC3_IQ" range="3"/>
// <bitfield name="INVERT_DB1_DAC0_IQ" range="8"/>
// <bitfield name="INVERT_DB1_DAC1_IQ" range="9"/>
// <bitfield name="INVERT_DB1_DAC2_IQ" range="10"/>
// <bitfield name="INVERT_DB1_DAC3_IQ" range="11"/>
// </register>
//
// <register name="MMCM_RESET_REG" offset="0x11000" size="32">
// <info>Control register for resetting the data clock MMCM.</info>
// <bitfield name="RESET_MMCM" range="0">
// <info>
// Write a '1' to this bit to reset the MMCM. Then write a
// '0' to place the MMCM out of reset.
// </info>
// </bitfield>
// </register>
//
// <register name="RF_RESET_CONTROL_REG" offset="0x12000" typename="RF_RESET_CONTROL_REGTYPE"/>
// <register name="RF_RESET_STATUS_REG" offset="0x12008" typename="RF_RESET_STATUS_REGTYPE"/>
//
// <register name="RF_AXI_STATUS_REG" offset="0x13000" typename="RF_AXI_STATUS_REGTYPE"/>
//
// <register name="CALIBRATION_DATA" offset="0x014000">
// <info>
// The fields of this register provide data to all the DAC channels when enabled
// by the CALIBRATION_ENABLE register.
// </info>
// <bitfield name="Q_DATA" range="31..16">
// </bitfield>
// <bitfield name="I_DATA" range="15..00">
// </bitfield>
// </register>
//
// <register name="CALIBRATION_ENABLE" offset="0x014008">
// <info>
// This register enables calibration data in the DAC data path for each of the
// four channels. Each of these bits is normally '0'. When written '1', DAC data
// for the corresponding channel will be constantly driven with the contents of
// the CALIBRATION_DATA register.
// </info>
// <bitfield name="ENABLE_CALIBRATION_DATA_0" range="0">
// <info>
// Enables calibration data for channel 0.
// </info>
// </bitfield>
// <bitfield name="ENABLE_CALIBRATION_DATA_1" range="1">
// <info>
// Enables calibration data for channel 1.
// </info>
// </bitfield>
// <bitfield name="ENABLE_CALIBRATION_DATA_2" range="4">
// <info>
// Enables calibration data for channel 2.
// </info>
// </bitfield>
// <bitfield name="ENABLE_CALIBRATION_DATA_3" range="5">
// <info>
// Enables calibration data for channel 3.
// </info>
// </bitfield>
// </register>
//
// <register name="RF_PLL_CONTROL_REG" offset="0x16000" size="32" writable="true">
// <info>
// Enable RF MMCM outputs.
// </info>
// <bitfield name="ENABLE_DATA_CLK" range="0"/>
// <bitfield name="ENABLE_DATA_CLK_2X" range="4"/>
// <bitfield name="ENABLE_RF_CLK" range="8"/>
// <bitfield name="ENABLE_RF_CLK_2X" range="12"/>
// <bitfield name="CLEAR_DATA_CLK_UNLOCKED" range="16"/>
// </register>
//
// <register name="RF_PLL_STATUS_REG" offset="0x16008" size="32" writable="false">
// <info>
// Data Clk Pll Status Register
// </info>
// <bitfield name="DATA_CLK_PLL_UNLOCKED_STICKY" range="16"/>
// <bitfield name="DATA_CLK_PLL_LOCKED" range="20"/>
// </register>
//
// <register name="THRESHOLD_STATUS" offset="0x015000">
// <info>
// This register shows threshold status for the ADCs. Each bit reflects the
// RFDC's real-time ADC status signals, which will assert when the ADC input
// signal exceeds the programmed threshold value. The status will remain
// asserted until cleared by software.
// The bitfield names follow the pattern ADCX_ZZ_over_threshold(1|2), where X is
// the location of the tile in the converter column and ZZ is either 01 (the
// lower RF-ADC in the tile) or 23 (the upper RF-ADC in the tile).
// See also the Xilinx document PG269.
// </info>
// <bitfield name="ADC0_01_THRESHOLD1" range="0">
// </bitfield>
// <bitfield name="ADC0_01_THRESHOLD2" range="1">
// </bitfield>
// <bitfield name="ADC0_23_THRESHOLD1" range="2">
// </bitfield>
// <bitfield name="ADC0_23_THRESHOLD2" range="3">
// </bitfield>
// <bitfield name="ADC2_01_THRESHOLD1" range="8">
// </bitfield>
// <bitfield name="ADC2_01_THRESHOLD2" range="9">
// </bitfield>
// <bitfield name="ADC2_23_THRESHOLD1" range="10">
// </bitfield>
// <bitfield name="ADC2_23_THRESHOLD2" range="11">
// </bitfield>
// </register>
//
// <register name="FABRIC_DSP_REG" offset="0x13008" typename="FABRIC_DSP_REGTYPE"/>
// <register name="ADC_TILEMAP_REG" offset="0x17000" typename="ADC_TILEMAP_REGTYPE"/>
// <register name="DAC_TILEMAP_REG" offset="0x17008" typename="DAC_TILEMAP_REGTYPE"/>
// <register name="RFDC_INFO_REG" offset="0x18000" typename="RFDC_INFO_REGTYPE"/>
//
// </group>
//</regmap>
//XmlParse xml_off
top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/synthstub/x410_ps_rfdc_bd.vhd
+411
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------------------------------------------------------------------------------------------
--
-- File: x410_ps_rfdc_bd.vhd
-- Author: niBlockDesign::niBdExportStub
-- Original Project: HwBuildTools
-- Date: 27 September 2021
--
------------------------------------------------------------------------------------------
-- (c) Copyright National Instruments Corporation
-- All Rights Reserved
-- National Instruments Internal Information
------------------------------------------------------------------------------------------
--
-- Purpose: This is an automatically generated stub file to match the entity
-- declaration for 'x410_ps_rfdc_bd'. This file was created using niBdExportStub
-- Do not modify this file directly!
--
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity x410_ps_rfdc_bd is
port (
adc_data_out_resetn_dclk : out STD_LOGIC;
adc_enable_data_rclk : out STD_LOGIC;
adc_reset_pulse_dclk : in STD_LOGIC;
adc_rfdc_axi_resetn_rclk : out STD_LOGIC;
bus_clk : in STD_LOGIC;
bus_rstn : in STD_LOGIC;
clk40 : in STD_LOGIC;
clk40_rstn : in STD_LOGIC;
dac_data_in_resetn_dclk : out STD_LOGIC;
dac_data_in_resetn_dclk2x : out STD_LOGIC;
dac_data_in_resetn_rclk : out STD_LOGIC;
dac_data_in_resetn_rclk2x : out STD_LOGIC;
dac_reset_pulse_dclk : in STD_LOGIC;
data_clk : out STD_LOGIC;
data_clk_2x : out STD_LOGIC;
data_clock_locked : out STD_LOGIC;
enable_gated_clocks_clk40 : in STD_LOGIC;
enable_sysref_rclk : in STD_LOGIC;
fir_resetn_rclk2x : out STD_LOGIC;
gated_base_clks_valid_clk40 : out STD_LOGIC;
invert_adc_iq_rclk2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
invert_dac_iq_rclk2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
irq0_lpd_rpu_n : in STD_LOGIC;
irq1_lpd_rpu_n : in STD_LOGIC;
jtag0_tck : inout STD_LOGIC;
jtag0_tdi : inout STD_LOGIC;
jtag0_tdo : in STD_LOGIC;
jtag0_tms : inout STD_LOGIC;
nco_reset_done_dclk : out STD_LOGIC;
pl_clk40 : out STD_LOGIC;
pl_clk100 : out STD_LOGIC;
pl_clk166 : out STD_LOGIC;
pl_clk200 : out STD_LOGIC;
pl_ps_irq0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
pl_ps_irq1 : in STD_LOGIC_VECTOR ( 5 downto 0 );
pl_resetn0 : out STD_LOGIC;
pl_resetn1 : out STD_LOGIC;
pl_resetn2 : out STD_LOGIC;
pl_resetn3 : out STD_LOGIC;
pll_ref_clk_in : in STD_LOGIC;
pll_ref_clk_out : out STD_LOGIC;
rf_axi_status_clk40 : in STD_LOGIC_VECTOR ( 31 downto 0 );
rf_dsp_info_clk40 : in STD_LOGIC_VECTOR ( 31 downto 0 );
rfdc_clk : out STD_LOGIC_VECTOR ( 0 to 0 );
rfdc_clk_2x : out STD_LOGIC_VECTOR ( 0 to 0 );
rfdc_irq : out STD_LOGIC;
s_axi_hp0_aclk : in STD_LOGIC;
s_axi_hp1_aclk : in STD_LOGIC;
s_axi_hpc0_aclk : in STD_LOGIC;
start_nco_reset_dclk : in STD_LOGIC;
sysref_out_pclk : out STD_LOGIC;
sysref_out_rclk : out STD_LOGIC;
sysref_pl_in : in STD_LOGIC;
s_axi_hp0_aruser : in STD_LOGIC;
s_axi_hp0_awuser : in STD_LOGIC;
s_axi_hp0_awid : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hp0_awaddr : in STD_LOGIC_VECTOR ( 48 downto 0 );
s_axi_hp0_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_hp0_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hp0_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hp0_awlock : in STD_LOGIC;
s_axi_hp0_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_hp0_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hp0_awvalid : in STD_LOGIC;
s_axi_hp0_awready : out STD_LOGIC;
s_axi_hp0_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_hp0_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_hp0_wlast : in STD_LOGIC;
s_axi_hp0_wvalid : in STD_LOGIC;
s_axi_hp0_wready : out STD_LOGIC;
s_axi_hp0_bid : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hp0_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hp0_bvalid : out STD_LOGIC;
s_axi_hp0_bready : in STD_LOGIC;
s_axi_hp0_arid : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hp0_araddr : in STD_LOGIC_VECTOR ( 48 downto 0 );
s_axi_hp0_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_hp0_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hp0_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hp0_arlock : in STD_LOGIC;
s_axi_hp0_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_hp0_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hp0_arvalid : in STD_LOGIC;
s_axi_hp0_arready : out STD_LOGIC;
s_axi_hp0_rid : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hp0_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_hp0_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hp0_rlast : out STD_LOGIC;
s_axi_hp0_rvalid : out STD_LOGIC;
s_axi_hp0_rready : in STD_LOGIC;
s_axi_hp0_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_hp0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_eth_dma_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axis_eth_dma_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_eth_dma_tlast : in STD_LOGIC;
s_axis_eth_dma_tready : out STD_LOGIC;
s_axis_eth_dma_tvalid : in STD_LOGIC;
s_axi_hp1_aruser : in STD_LOGIC;
s_axi_hp1_awuser : in STD_LOGIC;
s_axi_hp1_awid : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hp1_awaddr : in STD_LOGIC_VECTOR ( 48 downto 0 );
s_axi_hp1_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_hp1_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hp1_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hp1_awlock : in STD_LOGIC;
s_axi_hp1_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_hp1_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hp1_awvalid : in STD_LOGIC;
s_axi_hp1_awready : out STD_LOGIC;
s_axi_hp1_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_hp1_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_hp1_wlast : in STD_LOGIC;
s_axi_hp1_wvalid : in STD_LOGIC;
s_axi_hp1_wready : out STD_LOGIC;
s_axi_hp1_bid : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hp1_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hp1_bvalid : out STD_LOGIC;
s_axi_hp1_bready : in STD_LOGIC;
s_axi_hp1_arid : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hp1_araddr : in STD_LOGIC_VECTOR ( 48 downto 0 );
s_axi_hp1_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_hp1_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hp1_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hp1_arlock : in STD_LOGIC;
s_axi_hp1_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_hp1_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hp1_arvalid : in STD_LOGIC;
s_axi_hp1_arready : out STD_LOGIC;
s_axi_hp1_rid : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hp1_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_hp1_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hp1_rlast : out STD_LOGIC;
s_axi_hp1_rvalid : out STD_LOGIC;
s_axi_hp1_rready : in STD_LOGIC;
s_axi_hp1_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_hp1_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_hpc0_aruser : in STD_LOGIC;
s_axi_hpc0_awuser : in STD_LOGIC;
s_axi_hpc0_awid : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hpc0_awaddr : in STD_LOGIC_VECTOR ( 48 downto 0 );
s_axi_hpc0_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_hpc0_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hpc0_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hpc0_awlock : in STD_LOGIC;
s_axi_hpc0_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_hpc0_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hpc0_awvalid : in STD_LOGIC;
s_axi_hpc0_awready : out STD_LOGIC;
s_axi_hpc0_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_hpc0_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_hpc0_wlast : in STD_LOGIC;
s_axi_hpc0_wvalid : in STD_LOGIC;
s_axi_hpc0_wready : out STD_LOGIC;
s_axi_hpc0_bid : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hpc0_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hpc0_bvalid : out STD_LOGIC;
s_axi_hpc0_bready : in STD_LOGIC;
s_axi_hpc0_arid : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hpc0_araddr : in STD_LOGIC_VECTOR ( 48 downto 0 );
s_axi_hpc0_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_hpc0_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hpc0_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hpc0_arlock : in STD_LOGIC;
s_axi_hpc0_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_hpc0_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hpc0_arvalid : in STD_LOGIC;
s_axi_hpc0_arready : out STD_LOGIC;
s_axi_hpc0_rid : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hpc0_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_hpc0_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hpc0_rlast : out STD_LOGIC;
s_axi_hpc0_rvalid : out STD_LOGIC;
s_axi_hpc0_rready : in STD_LOGIC;
s_axi_hpc0_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_hpc0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
adc0_clk_clk_n : in STD_LOGIC;
adc0_clk_clk_p : in STD_LOGIC;
adc2_clk_clk_n : in STD_LOGIC;
adc2_clk_clk_p : in STD_LOGIC;
m_axi_app_awaddr : out STD_LOGIC_VECTOR ( 39 downto 0 );
m_axi_app_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_app_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_app_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_app_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_app_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_app_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_app_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_app_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_app_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_app_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_app_araddr : out STD_LOGIC_VECTOR ( 39 downto 0 );
m_axi_app_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_app_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_app_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_app_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_app_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_app_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_app_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
dac0_clk_clk_n : in STD_LOGIC;
dac0_clk_clk_p : in STD_LOGIC;
dac1_clk_clk_n : in STD_LOGIC;
dac1_clk_clk_p : in STD_LOGIC;
gpio_0_tri_i : in STD_LOGIC_VECTOR ( 63 downto 0 );
gpio_0_tri_o : out STD_LOGIC_VECTOR ( 63 downto 0 );
gpio_0_tri_t : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_eth_internal_awaddr : out STD_LOGIC_VECTOR ( 39 downto 0 );
m_axi_eth_internal_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_eth_internal_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_eth_internal_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_eth_internal_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_eth_internal_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_eth_internal_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_eth_internal_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_eth_internal_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_eth_internal_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_eth_internal_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_eth_internal_araddr : out STD_LOGIC_VECTOR ( 39 downto 0 );
m_axi_eth_internal_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_eth_internal_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_eth_internal_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_eth_internal_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_eth_internal_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_eth_internal_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_eth_internal_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_eth_dma_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axis_eth_dma_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_eth_dma_tlast : out STD_LOGIC;
m_axis_eth_dma_tready : in STD_LOGIC;
m_axis_eth_dma_tvalid : out STD_LOGIC;
m_axi_rpu_awaddr : out STD_LOGIC_VECTOR ( 39 downto 0 );
m_axi_rpu_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rpu_awvalid : out STD_LOGIC;
m_axi_rpu_awready : in STD_LOGIC;
m_axi_rpu_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rpu_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rpu_wvalid : out STD_LOGIC;
m_axi_rpu_wready : in STD_LOGIC;
m_axi_rpu_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rpu_bvalid : in STD_LOGIC;
m_axi_rpu_bready : out STD_LOGIC;
m_axi_rpu_araddr : out STD_LOGIC_VECTOR ( 39 downto 0 );
m_axi_rpu_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rpu_arvalid : out STD_LOGIC;
m_axi_rpu_arready : in STD_LOGIC;
m_axi_rpu_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rpu_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rpu_rvalid : in STD_LOGIC;
m_axi_rpu_rready : out STD_LOGIC;
m_axi_core_awaddr : out STD_LOGIC_VECTOR ( 39 downto 0 );
m_axi_core_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_core_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_core_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_core_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_core_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_core_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_core_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_core_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_core_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_core_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_core_araddr : out STD_LOGIC_VECTOR ( 39 downto 0 );
m_axi_core_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_core_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_core_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_core_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_core_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_core_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_core_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_mpm_ep_awaddr : out STD_LOGIC_VECTOR ( 39 downto 0 );
m_axi_mpm_ep_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mpm_ep_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_mpm_ep_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_mpm_ep_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mpm_ep_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_mpm_ep_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_mpm_ep_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_mpm_ep_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mpm_ep_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_mpm_ep_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_mpm_ep_araddr : out STD_LOGIC_VECTOR ( 39 downto 0 );
m_axi_mpm_ep_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mpm_ep_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_mpm_ep_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_mpm_ep_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mpm_ep_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mpm_ep_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_mpm_ep_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
adc_tile224_ch0_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile224_ch0_dout_i_tready : in STD_LOGIC;
adc_tile224_ch0_dout_i_tvalid : out STD_LOGIC;
adc_tile224_ch0_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile224_ch0_dout_q_tready : in STD_LOGIC;
adc_tile224_ch0_dout_q_tvalid : out STD_LOGIC;
adc_tile224_ch1_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile224_ch1_dout_i_tready : in STD_LOGIC;
adc_tile224_ch1_dout_i_tvalid : out STD_LOGIC;
adc_tile224_ch1_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile224_ch1_dout_q_tready : in STD_LOGIC;
adc_tile224_ch1_dout_q_tvalid : out STD_LOGIC;
adc_tile226_ch0_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile226_ch0_dout_i_tready : in STD_LOGIC;
adc_tile226_ch0_dout_i_tvalid : out STD_LOGIC;
adc_tile226_ch0_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile226_ch0_dout_q_tready : in STD_LOGIC;
adc_tile226_ch0_dout_q_tvalid : out STD_LOGIC;
adc_tile226_ch1_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile226_ch1_dout_i_tready : in STD_LOGIC;
adc_tile226_ch1_dout_i_tvalid : out STD_LOGIC;
adc_tile226_ch1_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile226_ch1_dout_q_tready : in STD_LOGIC;
adc_tile226_ch1_dout_q_tvalid : out STD_LOGIC;
dac_tile228_ch0_vout_v_n : out STD_LOGIC;
dac_tile228_ch0_vout_v_p : out STD_LOGIC;
dac_tile228_ch1_vout_v_n : out STD_LOGIC;
dac_tile228_ch1_vout_v_p : out STD_LOGIC;
dac_tile229_ch0_vout_v_n : out STD_LOGIC;
dac_tile229_ch0_vout_v_p : out STD_LOGIC;
dac_tile229_ch1_vout_v_n : out STD_LOGIC;
dac_tile229_ch1_vout_v_p : out STD_LOGIC;
dac_tile228_ch0_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
dac_tile228_ch0_din_tvalid : in STD_LOGIC;
dac_tile228_ch0_din_tready : out STD_LOGIC;
dac_tile228_ch1_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
dac_tile228_ch1_din_tvalid : in STD_LOGIC;
dac_tile228_ch1_din_tready : out STD_LOGIC;
dac_tile229_ch0_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
dac_tile229_ch0_din_tvalid : in STD_LOGIC;
dac_tile229_ch0_din_tready : out STD_LOGIC;
dac_tile229_ch1_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
dac_tile229_ch1_din_tvalid : in STD_LOGIC;
dac_tile229_ch1_din_tready : out STD_LOGIC;
s_axi_hpc1_awid : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hpc1_awaddr : in STD_LOGIC_VECTOR ( 48 downto 0 );
s_axi_hpc1_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_hpc1_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hpc1_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hpc1_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_hpc1_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_hpc1_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hpc1_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_hpc1_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_hpc1_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_hpc1_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_hpc1_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_hpc1_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_hpc1_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_hpc1_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_hpc1_bid : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hpc1_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hpc1_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_hpc1_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_hpc1_arid : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hpc1_araddr : in STD_LOGIC_VECTOR ( 48 downto 0 );
s_axi_hpc1_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_hpc1_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hpc1_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hpc1_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_hpc1_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_hpc1_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hpc1_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_hpc1_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_hpc1_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_hpc1_rid : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hpc1_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_hpc1_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hpc1_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_hpc1_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_hpc1_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
sysref_rf_in_diff_n : in STD_LOGIC;
sysref_rf_in_diff_p : in STD_LOGIC;
adc_tile224_ch0_vin_v_n : in STD_LOGIC;
adc_tile224_ch0_vin_v_p : in STD_LOGIC;
adc_tile224_ch1_vin_v_n : in STD_LOGIC;
adc_tile224_ch1_vin_v_p : in STD_LOGIC;
adc_tile226_ch0_vin_v_n : in STD_LOGIC;
adc_tile226_ch0_vin_v_p : in STD_LOGIC;
adc_tile226_ch1_vin_v_n : in STD_LOGIC;
adc_tile226_ch1_vin_v_p : in STD_LOGIC;
s_axi_hpc1_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_hpc1_awuser : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end entity x410_ps_rfdc_bd;
architecture stub of x410_ps_rfdc_bd is
begin
end architecture stub;
top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/x410_ps_rfdc_bd.tcl
+3825
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File diff suppressed because it is too large Load Diff
top/x400/ip/xge_pcs_pma/Makefile.inc
+1 -1
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@@ -38,4 +38,4 @@ $(IP_XGE_PCS_PMA_SRCS) $(IP_XGE_PCS_PMA_OUTS): IP_XGE_PCS_PMA_TRGT
@:
IP_XGE_PCS_PMA_TRGT: $(IP_DIR)/xge_pcs_pma/xge_pcs_pma.xci
$(call BUILD_VIVADO_IP,xge_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1)
$(call BUILD_VIVADO_IP_WITH_SUBCORES,xge_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1)