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fpga: Multiple X300 FPGA bugfixes and enhancements

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- Fixed 10GigE firmware communication issues and sequence errors for TX
- Multiple changes to help ease timing closure
- Cleaned up build scripts
- Switched to Xilinx ISE 14.7 as the default build tool for X300


Original-commit: 64d71dcbc5fa6790385b288de25224d386b047b0
This commit is contained in:
Ashish Chaudhari committed 2014-09-24 18:45:31 -07:00
1 parent 6b7004c311
commit adf2da6ac7
275 files changed
+13788 -293124
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lib/packet_proc/Makefile.srcs
+2
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@@ -18,4 +18,6 @@ cvita_insert_tlast.v \
cvita_dest_lookup.v \
cvita_chunker.v \
cvita_dechunker.v \
axis_packet_debug.v \
cvita_packet_debug.v \
))
lib/packet_proc/axis_packet_debug.v
+71
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@@ -0,0 +1,71 @@
//
// Copyright 2014 Ettus Research LLC
//
module axis_packet_debug (
input clk,
input reset,
input clear,
//Packet In
input [63:0] tdata,
input tlast,
input tvalid,
input tready,
//Per packet info
output reg pkt_strobe,
output reg [15:0] length,
output reg [63:0] checksum,
//Statistics
output reg [31:0] pkt_count
);
localparam ST_HEADER = 1'b0;
localparam ST_DATA = 1'b1;
//Packet state logic
reg pkt_state;
always @(posedge clk) begin
if (reset) begin
pkt_state <= ST_HEADER;
end else if (tvalid & tready) begin
pkt_state <= tlast ? ST_HEADER : ST_DATA;
end
end
//Trigger logic
always @(posedge clk)
if (reset)
pkt_strobe <= 1'b0;
else
pkt_strobe <= tvalid & tready & tlast;
//Length capture
always @(posedge clk)
if (reset || pkt_state == ST_HEADER)
length <= tlast ? 16'd8 : 16'd0;
else
if (tvalid & tready)
length <= length + 16'd8;
//Checksum capture
always @(posedge clk)
if (reset || pkt_state == ST_HEADER)
checksum <= 64'd0;
else
if (tvalid & tready)
checksum <= checksum ^ tdata;
//Counts
always @(posedge clk)
if (reset | clear) begin
pkt_count <= 32'd0;
end else begin
if (tvalid & tready & tlast) begin
pkt_count <= pkt_count + 32'd1;
end
end
endmodule // cvita_packet_debug
lib/packet_proc/cvita_packet_debug.v
+108
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@@ -0,0 +1,108 @@
//
// Copyright 2014 Ettus Research LLC
//
module cvita_packet_debug (
input clk,
input reset,
input clear,
//Packet In
input [63:0] tdata,
input tlast,
input tvalid,
input tready,
//Per packet info
output reg pkt_strobe,
output reg [63:0] header,
output reg [63:0] timestamp,
output reg [15:0] actual_length,
output reg [63:0] checksum,
//Statistics
output reg [31:0] pkt_count,
output reg [31:0] ctrl_pkt_count
);
localparam ST_HEADER = 2'd0;
localparam ST_TIME = 2'd1;
localparam ST_DATA = 2'd2;
//Packet state logic
reg [1:0] pkt_state;
always @(posedge clk) begin
if (reset) begin
pkt_state <= ST_HEADER;
end else if (tvalid & tready) begin
case(pkt_state)
ST_HEADER: begin
if (!tlast)
pkt_state <= (tdata[61]) ? ST_TIME : ST_DATA;
end
ST_TIME: begin
pkt_state <= (tlast) ? ST_HEADER : ST_DATA;
end
ST_DATA: begin
pkt_state <= (tlast) ? ST_HEADER : ST_DATA;
end
default: pkt_state <= ST_HEADER;
endcase
end
end
//Trigger logic
always @(posedge clk)
if (reset)
pkt_strobe <= 1'b0;
else
pkt_strobe <= tvalid & tready & tlast;
//Header capture
always @(posedge clk)
if (reset)
header <= 64'd0;
else if (pkt_state == ST_HEADER)
if (tvalid & tready)
header <= tdata;
//Timestamp capture
always @(posedge clk)
if (reset)
timestamp <= 64'd0;
else if (pkt_state == ST_TIME)
if (tvalid & tready)
timestamp <= tdata;
//Length capture
always @(posedge clk)
if (reset || pkt_state == ST_HEADER)
actual_length <= (tvalid & tready & tlast) ? 16'd8 : 16'd0;
else
if (tvalid & tready)
actual_length <= actual_length + 16'd8;
//Checksum capture
always @(posedge clk)
if (reset || pkt_state == ST_HEADER)
checksum <= 64'd0;
else if (pkt_state == ST_DATA)
if (tvalid & tready)
checksum <= checksum ^ tdata;
//Counts
always @(posedge clk)
if (reset | clear) begin
pkt_count <= 32'd0;
ctrl_pkt_count <= 32'd0;
end else begin
if (tvalid & tready & tlast) begin
pkt_count <= pkt_count + 32'd1;
if (pkt_state == ST_HEADER && tdata[63])
ctrl_pkt_count <= ctrl_pkt_count + 32'd1;
else if (header[63])
ctrl_pkt_count <= ctrl_pkt_count + 32'd1;
end
end
endmodule // cvita_packet_debug
lib/packet_proc/eth_dispatch.v
+54 -114
View File
@@ -76,9 +76,9 @@ module eth_dispatch
output [31:0] debug
);
//
//---------------------------------------------------------
// State machine declarations
//
//---------------------------------------------------------
reg [2:0] state;
localparam WAIT_PACKET = 0;
@@ -90,31 +90,23 @@ module eth_dispatch
localparam DROP_PACKET = 6;
localparam CLASSIFY_PACKET = 7;
//
// Small RAM stores packet header during parsing.
//
// IJB consider changing HEADER_RAM_SIZE to 7
localparam HEADER_RAM_SIZE = 9;
(*ram_style="distributed"*)
reg [68:0] header_ram [HEADER_RAM_SIZE-1:0];
reg [3:0] header_ram_addr;
reg drop_this_packet;
(*ram_style="distributed"*) reg [68:0] header_ram [HEADER_RAM_SIZE-1:0];
reg [3:0] header_ram_addr;
wire header_done = (header_ram_addr == HEADER_RAM_SIZE-1);
reg fwd_input;
//
reg [63:0] in_tdata_reg;
//
wire out_tvalid;
wire out_tready;
wire out_tlast;
wire [3:0] out_tuser;
wire [63:0] out_tdata;
//
// Output AXI-Stream interface to VITA Radio Core
wire [63:0] vita_pre_tdata;
wire [3:0] vita_pre_tuser;
@@ -134,9 +126,7 @@ module eth_dispatch
wire xo_pre_tvalid;
wire xo_pre_tready;
//
// Packet Parse Flags
//
reg is_eth_dst_addr;
reg is_eth_broadcast;
reg is_eth_type_ipv4;
@@ -147,67 +137,69 @@ module eth_dispatch
reg is_icmp_no_fwd;
reg is_chdr;
//
//---------------------------------------------------------
// Settings regs
//
//---------------------------------------------------------
// MAC address for the dispatcher module.
// This value is used to determine if the packet is meant
// for this device should be consumed
wire [47:0] my_mac;
setting_reg #(.my_addr(BASE), .awidth(16), .width(32)) sr_my_mac_lsb
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(my_mac[31:0]),.changed());
setting_reg #(.my_addr(BASE+1), .awidth(16), .width(16)) sr_my_mac_msb
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(my_mac[47:32]),.changed());
// IP address for the dispatcher module.
// This value is used to determine if the packet is addressed
// to this device
wire [31:0] my_ip;
setting_reg #(.my_addr(BASE+2), .awidth(16), .width(32)) sr_my_ip
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(my_ip[31:0]),.changed());
// This module supports two destination ports
wire [15:0] my_port0, my_port1;
setting_reg #(.my_addr(BASE+3), .awidth(16), .width(32)) sr_udp_port
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out({my_port1[15:0],my_port0[15:0]}),.changed());
// forward_ndest: Forward to crossover path if MAC Addr in packet
// does not match "my_mac"
// forward_bcast: Forward broadcasts to crossover path
wire forward_ndest, forward_bcast;
setting_reg #(.my_addr(BASE+4), .awidth(16), .width(2)) sr_forward_ctrl
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out({forward_ndest, forward_bcast}),.changed());
//ICMP Type and Code to forward packet to ZPU
wire [7:0] my_icmp_type, my_icmp_code;
setting_reg #(.my_addr(BASE+5), .awidth(16), .width(16)) sr_icmp_ctrl
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out({my_icmp_type, my_icmp_code}),.changed());
assign debug =
{
1'b0, state, //4
1'b0, in_tvalid, in_tready, in_tlast, //4
1'b0, is_eth_dst_addr, is_eth_broadcast, is_eth_type_ipv4,
is_ipv4_dst_addr, is_ipv4_proto_udp, is_udp_dst_ports, //8
header_ram_addr[3:0], //4
4'b0, 8'b0
};
//
//---------------------------------------------------------
// Packet Forwarding State machine.
//
//---------------------------------------------------------
// Read input packet and store the header into a RAM for
// classification. A header is defined as HEADER_RAM_SIZE
// number of 64-bit words.
// Based on clasification results, output the packet to the
// VITA port, crossover(XO) port or the ZPU. Note that the
// XO and ZPU ports require fully framed Eth packets so data
// from the RAM has to be replayed on the output. The state
// machine will hold off input packets until the header is
// replayed. The state machine also supports dropping pkts.
always @(posedge clk)
if (reset || clear) begin
state <= WAIT_PACKET;
header_ram_addr <= 0;
drop_this_packet <= 0;
fwd_input <= 0;
end else begin
// Defaults.
drop_this_packet <= 0;
case(state)
//
// Wait for start of a packet
@@ -250,15 +242,15 @@ module eth_dispatch
end else if (is_eth_broadcast) begin
header_ram_addr <= 0;
state <= forward_bcast? FORWARD_ZPU_AND_XO : FORWARD_ZPU;
end else if (!is_eth_dst_addr) begin
end else if (!is_eth_dst_addr && forward_ndest) begin
header_ram_addr <= 0;
state <= forward_ndest? FORWARD_XO : DROP_PACKET;
state <= FORWARD_XO;
end else if (!is_eth_dst_addr && !forward_ndest) begin
header_ram_addr <= HEADER_RAM_SIZE - 1;
state <= DROP_PACKET;
end else if ((is_udp_dst_ports != 0) && is_chdr) begin
header_ram_addr <= 6; // Jump to CHDR
state <= FORWARD_RADIO_CORE;
end else if (drop_this_packet) begin
header_ram_addr <= HEADER_RAM_SIZE-1;
state <= DROP_PACKET;
end else begin
header_ram_addr <= 0;
state <= FORWARD_ZPU;
@@ -328,10 +320,14 @@ module eth_dispatch
endcase // case (state)
end // else: !if(reset || clear)
//
//---------------------------------------------------------
// Classifier State machine.
// Deep packet inspection during header ingress.
//
//---------------------------------------------------------
// As the packet header is pushed into the RAM, set classification
// bits so that by the time the input state machine reaches the
// CLASSIFY_PACKET state, the packet has been fully identified.
always @(posedge clk)
if (reset || clear) begin
is_eth_dst_addr <= 1'b0;
@@ -343,10 +339,6 @@ module eth_dispatch
is_udp_dst_ports <= 0;
is_icmp_no_fwd <= 0;
is_chdr <= 1'b0;
//space_in_fifo <= 0;
//is_there_fifo_space <= 1;
//packet_length <= 0;
end else if (in_tvalid && in_tready) begin // if (reset || clear)
in_tdata_reg <= in_tdata;
@@ -426,9 +418,9 @@ module eth_dispatch
end // if (in_tvalid && in_tready)
//
//---------------------------------------------------------
// Output (Egress) Interface muxing
//
//---------------------------------------------------------
assign out_tready =
(state == DROP_PACKET) ||
((state == FORWARD_RADIO_CORE) && vita_pre_tready) ||
@@ -448,7 +440,6 @@ module eth_dispatch
(state == READ_HEADER) ||
(out_tready && fwd_input);
//
// Because we can forward to both the ZPU and XO FIFO's concurrently
// we have to make sure both can accept data in the same cycle.
@@ -461,25 +452,22 @@ module eth_dispatch
assign zpu_pre_tvalid = out_tvalid &&
((state == FORWARD_ZPU) ||
((state == FORWARD_ZPU_AND_XO) && xo_pre_tready));
assign vita_pre_tvalid = out_tvalid && (state == FORWARD_RADIO_CORE);
assign vita_pre_tvalid = out_tvalid &&
(state == FORWARD_RADIO_CORE);
assign {zpu_pre_tuser,zpu_pre_tdata} = ((state == FORWARD_ZPU_AND_XO) || (state == FORWARD_ZPU)) ?
{out_tuser,out_tdata} : 0;
assign {zpu_pre_tlast, zpu_pre_tuser, zpu_pre_tdata} = {out_tlast, out_tuser, out_tdata};
assign {xo_pre_tlast, xo_pre_tuser, xo_pre_tdata} = {out_tlast, out_tuser, out_tdata};
assign {vita_pre_tlast, vita_pre_tuser, vita_pre_tdata} = {out_tlast, out_tuser, out_tdata};
assign {xo_pre_tuser,xo_pre_tdata} = ((state == FORWARD_ZPU_AND_XO) || (state == FORWARD_XO)) ?
{out_tuser,out_tdata} : 0;
//---------------------------------------------------------
// Egress FIFO's
//---------------------------------------------------------
// These FIFO's have to be fairly large to prevent any egress
// port from backpressuring the input state machine.
// The ZPU and XO ports are inherently slow consumers so they
// get a large buffer. The VITA port is fast but high throughput
// so even that needs a large FIFO.
assign {vita_pre_tuser,vita_pre_tdata} = (state == FORWARD_RADIO_CORE) ? {out_tuser,out_tdata} : 0;
assign zpu_pre_tlast = out_tlast && ((state == FORWARD_ZPU) || (state == FORWARD_ZPU_AND_XO));
assign xo_pre_tlast = out_tlast && ((state == FORWARD_XO) || (state == FORWARD_ZPU_AND_XO));
assign vita_pre_tlast = out_tlast && (state == FORWARD_RADIO_CORE);
//
// Egress FIFO's (Large)
//
axi_fifo #(.WIDTH(69),.SIZE(10))
axi_fifo_zpu (
.clk(clk),
@@ -525,52 +513,4 @@ module eth_dispatch
.occupied()
);
assign debug_flags = {vita_pre_tready,xo_pre_tready,zpu_pre_tready};
/* -----\/----- EXCLUDED -----\/-----
wire vready, zready, oready;
wire vvalid, zvalid, ovalid;
reg [2:0] ed_state;
localparam ED_IDLE = 3'd0;
localparam ED_IN_HDR = 3'd1;
localparam ED_VITA = 3'd2;
localparam ED_ZPU = 3'd3;
localparam ED_OUT = 3'd4;
localparam ED_DROP = 3'd5;
-----/\----- EXCLUDED -----/\----- */
// for now, send everything to zpu
/*
always @(posedge clk)
if(reset | clear)
ed_state <= ED_IDLE;
else
case(ed_state)
ED_IDLE:
if(vready & zready & oready & in_tvalid)
;
endcase // case (ed_state)
*/
/* -----\/----- EXCLUDED -----\/-----
axi_packet_gate #(.WIDTH(64), .SIZE(10)) vita_gate
(.clk(clk), .reset(reset), .clear(clear),
.i_tdata(in_tdata), .i_tlast(), .i_terror(), .i_tvalid(1'b0), .i_tready(vready),
.o_tdata(vita_tdata), .o_tlast(vita_tlast), .o_tvalid(vita_tvalid), .o_tready(vita_tready));
axi_packet_gate #(.WIDTH(68), .SIZE(10)) zpu_gate
(.clk(clk), .reset(reset), .clear(clear),
.i_tdata({in_tuser,in_tdata}), .i_tlast(in_tlast), .i_terror(in_tuser[3]), .i_tvalid(in_tvalid), .i_tready(in_tready),
.o_tdata({zpu_tuser,zpu_tdata}), .o_tlast(zpu_tlast), .o_tvalid(zpu_tvalid), .o_tready(zpu_tready));
axi_packet_gate #(.WIDTH(68), .SIZE(10)) out_gate
(.clk(clk), .reset(reset), .clear(clear),
.i_tdata({in_tuser,in_tdata}), .i_tlast(), .i_terror(), .i_tvalid(1'b0), .i_tready(oready),
.o_tdata({out_tuser,out_tdata}), .o_tlast(out_tlast), .o_tvalid(out_tvalid), .o_tready(out_tready));
-----/\----- EXCLUDED -----/\----- */
endmodule // eth_dispatch
lib/packet_proc/eth_interface.v
+15 -35
View File
@@ -43,7 +43,10 @@ module eth_interface
// efficiently internally without holding resources allocted for longer than optimal. This also means that an upstream
// error discovered in the packet can allow the packet to be destroyed here, before it gets deeper into the USRP.
//
axi_packet_gate #(.WIDTH(68), .SIZE(10)) packet_gater //holds 8K pkts
// This gate must be able to hold at least 9900 bytes which is the maximum length between the SOF and EOF
// as asserted by the 1G and 10G MACs. This is required in case one of the max size packets has an error
// and needs to be dropped. With SIZE=11, this gate will hold 2 8k packets.
axi_packet_gate #(.WIDTH(68), .SIZE(11)) packet_gater
(.clk(clk), .reset(reset), .clear(clear),
.i_tdata({eth_rx_tuser, eth_rx_tdata}), .i_tlast(eth_rx_tlast),
@@ -56,6 +59,9 @@ module eth_interface
//
// Based on programmed rules, parse network headers and decide which internal destination(s) this packet will be forwarded to.
//
wire [63:0] e2v_tdata_int;
wire e2v_tlast_int, e2v_tvalid_int, e2v_tready_int;
wire [63:0] e2z_tdata_int;
wire [3:0] e2z_tuser_int;
wire e2z_tlast_int, e2z_tvalid_int, e2z_tready_int;
@@ -65,11 +71,18 @@ module eth_interface
(.clk(clk), .reset(reset), .clear(clear),
.set_stb(set_stb), .set_addr(set_addr) , .set_data(set_data),
.in_tdata(epg_tdata_int), .in_tuser(epg_tuser_int), .in_tlast(epg_tlast_int), .in_tvalid(epg_tvalid_int), .in_tready(epg_tready_int),
.vita_tdata(e2v_tdata), .vita_tlast(e2v_tlast), .vita_tvalid(e2v_tvalid), .vita_tready(e2v_tready),
.vita_tdata(e2v_tdata_int), .vita_tlast(e2v_tlast_int), .vita_tvalid(e2v_tvalid_int), .vita_tready(e2v_tready_int),
.zpu_tdata(e2z_tdata_int), .zpu_tuser(e2z_tuser_int), .zpu_tlast(e2z_tlast_int), .zpu_tvalid(e2z_tvalid_int), .zpu_tready(e2z_tready_int),
.xo_tdata(xo_tdata), .xo_tuser(xo_tuser), .xo_tlast(xo_tlast), .xo_tvalid(xo_tvalid), .xo_tready(xo_tready), // to other eth port
.debug_flags(dispatch_debug_flags),.debug(debug));
axi_fifo_short #(.WIDTH(65)) e2v_pipeline_srl
(.clk(clk), .reset(reset), .clear(clear),
.i_tdata({e2v_tlast_int,e2v_tdata_int}), .i_tvalid(e2v_tvalid_int), .i_tready(e2v_tready_int),
.o_tdata({e2v_tlast,e2v_tdata}), .o_tvalid(e2v_tvalid), .o_tready(e2v_tready),
.space(), .occupied()
);
//
// ZPU can be slow to respond (relative to packet wirespeed) so extra buffer for packets destined there so it doesn't back up.
//
@@ -124,37 +137,4 @@ module eth_interface
.o_tdata({eth_tx_tlast,eth_tx_tuser,eth_tx_tdata}), .o_tvalid(eth_tx_tvalid), .o_tready(eth_tx_tready));
//
// Provide instrumentation so that abnormal FIFO conditions can be identifed.
//
/* -----\/----- EXCLUDED -----\/-----
setting_reg #(.my_addr(BASE+15), .awidth(16), .width(1)) sr_reset_fifo_debug
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(),.changed(clear_debug_flags));
always @(posedge clk)
if (reset)
debug_flags <= 0;
else if (clear_debug_flags)
debug_flags <= 0;
else
debug_flags <= debug_flags | {eth_rx_tuser[3],
~eth_tx_tready_int,
~xi_tready,
~v2e_tready,
~e2z_tready_int,
~eth_rx_tready,
~dispatch_debug_flags[2:0]};
-----/\----- EXCLUDED -----/\----- */
assign debug_flags = {eth_rx_tuser[3],
~eth_tx_tready_int,
~xi_tready,
~v2e_tready,
~e2z_tready_int,
~eth_rx_tready,
~dispatch_debug_flags[2:0]};
endmodule // eth_interface
lib/xge_interface/xge_mac_wrapper.v
+3 -3
View File
@@ -151,7 +151,7 @@ module xge_mac_wrapper
///////////////////////////////////////////////////////////////////////////////////////
wire [63:0] rx_tdata_int;
wire [3:0] rx_tuser_int;
wire rx_talst_int;
wire rx_tlast_int;
wire rx_tvalid_int;
wire rx_tready_int;
@@ -194,7 +194,7 @@ module xge_mac_wrapper
// Large FIFO must be able to run input side at 64b@156MHz to sustain 10Gb Rx.
//
axi64_8k_2clk_fifo rxfifo_2clk
axi64_4k_2clk_fifo rxfifo_2clk
(
.s_aresetn(~xgmii_reset),
.s_aclk(xgmii_clk),
@@ -235,7 +235,7 @@ module xge_mac_wrapper
wire tx_sof_int3;
axi64_8k_2clk_fifo txfifo_2clk_1x
axi64_4k_2clk_fifo txfifo_2clk_1x
(
.s_aresetn(~xgmii_reset),
.s_aclk(sys_clk),
top/x300/.gitignore
-1
View File
@@ -1,7 +1,6 @@
build*
isim*
fuse*
gen_ddrlvds_tb
tmp*
*.log
*impact*
top/x300/Makefile
+21 -14
View File
@@ -28,15 +28,22 @@ clean:
print_report = \
echo "========================================================================"; \
cat $(1) | grep "Design Summary:" -A 124; \
cat $(1)/x300.syr | grep "Device utilization summary:" -A 30; \
echo "========================================================================"; \
echo "Timing Summary:\n"; \
cat $(1) | grep constraint | grep met | grep -v "*"; \
cat $(1)/x300.twr | grep constraint | grep met | grep -v "*"; \
echo "========================================================================";
# ise_build($1=Device, $2=Definitions)
ifndef EXPORT_ONLY
ise_build = make -f Makefile.x300.inc bin NAME=$@ DEVICE=$1 $2 EXTRA_DEFS="$2"
else
ise_build = @echo "Skipping ISE build and exporting pre-built files.";
endif
# post_build($1=Device, $2=Flavor)
post_build = \
@$(call print_report,build-$(1)_$(2)/build.log) \
@$(call print_report,build-$(1)_$(2)) \
mkdir -p build; \
echo "Exporting bitstream files..."; \
cp build-$(1)_$(2)/x300.bin build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bin; \
@@ -45,54 +52,54 @@ post_build = \
$(CREATE_LVBITX) --input-bin=build-$(1)_$(2)/x300.bin --output-lvbitx=build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).lvbitx --device="USRP $(1)" x3x0_base.lvbitx; \
cp -f x3x0_base.lvbitx build/`echo $(1) | tr A-Z a-z`.lvbitx_base; \
echo "Exporting logs..."; \
cp build-$(1)_$(2)/build.log build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).log; \
cp build-$(1)_$(2)/x300.syr build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).syr; \
cp build-$(1)_$(2)/x300.twr build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).twr; \
echo "\nDONE ... $(1)_$(2)\n";
#1Gig on both ports
X310_1G:
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(GIGE_DEFS) EXTRA_DEFS="$(GIGE_DEFS)"
$(call ise_build,XC7K410T,$(GIGE_DEFS))
$(call post_build,X310,1G)
X300_1G:
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(GIGE_DEFS) EXTRA_DEFS="$(GIGE_DEFS)"
$(call ise_build,XC7K325T,$(GIGE_DEFS))
$(call post_build,X300,1G)
#1Gig on port0, 10Gig on port1
X310_HG:
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(HYBRID_DEFS) EXTRA_DEFS="$(HYBRID_DEFS)"
$(call ise_build,XC7K410T,$(HYBRID_DEFS))
$(call post_build,X310,HG)
X300_HG:
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(HYBRID_DEFS) EXTRA_DEFS="$(HYBRID_DEFS)"
$(call ise_build,XC7K325T,$(HYBRID_DEFS))
$(call post_build,X300,HG)
#10Gig on both ports
X310_XG:
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(XGIGE_DEFS) EXTRA_DEFS="$(XGIGE_DEFS)"
$(call ise_build,XC7K410T,$(XGIGE_DEFS))
$(call post_build,X310,XG)
X300_XG:
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(XGIGE_DEFS) EXTRA_DEFS="$(XGIGE_DEFS)"
$(call ise_build,XC7K325T,$(XGIGE_DEFS))
$(call post_build,X300,XG)
# 1Gig on port0, 10Gig on port1, SRAM Tx FIFO's
X310_HGS:
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(HYBRID_SRAM_DEFS) EXTRA_DEFS="$(HYBRID_SRAM_DEFS)"
$(call ise_build,XC7K410T,$(HYBRID_SRAM_DEFS))
$(call post_build,X310,HGS)
X300_HGS:
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T FLOORPLAN=1 $(HYBRID_SRAM_DEFS) EXTRA_DEFS="$(HYBRID_SRAM_DEFS)"
$(call ise_build,XC7K325T,$(HYBRID_SRAM_DEFS))
$(call post_build,X300,HGS)
# 10Gig on both ports, SRAM Tx FIFO's
X310_XGS:
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(XGIGE_SRAM_DEFS) EXTRA_DEFS="$(XGIGE_SRAM_DEFS)"
$(call ise_build,XC7K410T,$(XGIGE_SRAM_DEFS))
$(call post_build,X310,XGS)
X300_XGS:
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(XGIGE_SRAM_DEFS) EXTRA_DEFS="$(XGIGE_SRAM_DEFS)"
$(call ise_build,XC7K325T,$(XGIGE_SRAM_DEFS))
$(call post_build,X300,XGS)
top/x300/Makefile.x300.inc
+31 -14
View File
@@ -65,12 +65,32 @@ capture_ddrlvds.v \
gen_ddrlvds.v \
radio.v \
bus_int.v \
gige_phy.v \
gige_phy_mdio.v \
x300.ucf \
stc3.ucf \
timing.ucf
ONE_GIG_SRCS = $(COREGEN_ONE_GIG_SRCS) \
gige_phy/gige_phy_mdio.v \
gige_phy/gige_sfp_mdio_block.v \
gige_phy/gige_sfp_mdio_reset_sync.v \
gige_phy/gige_sfp_mdio_sync_block.v \
gige_phy/transceiver/gige_sfp_mdio_transceiver.v \
gige_phy/transceiver/gige_sfp_mdio_gtwizard.v \
gige_phy/transceiver/gige_sfp_mdio_gtwizard_gt.v \
gige_phy/transceiver/gige_sfp_mdio_gtwizard_init.v \
gige_phy/transceiver/gige_sfp_mdio_tx_startup_fsm.v \
gige_phy/transceiver/gige_sfp_mdio_rx_startup_fsm.v \
gige_phy/transceiver/gige_sfp_mdio_recclk_monitor.v \
TEN_GIG_SRCS = $(COREGEN_TEN_GIG_SRCS) \
ten_gige_phy/ten_gig_eth_pcs_pma_x300_top.v \
ten_gige_phy/ten_gig_eth_pcs_pma_x300_top.ucf \
ten_gige_phy/ten_gig_eth_pcs_pma_block.v \
ten_gige_phy/ten_gig_eth_pcs_pma_mod.v \
ten_gige_phy/gtx/ten_gig_eth_pcs_pma_gt_usrclk_source.v \
ten_gige_phy/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser_gt.v \
ten_gige_phy/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser.v \
ifeq ($(FLOORPLAN), 1)
ifeq ($(DEVICE), XC7K325T)
TOP_SRCS+=floorplan_X300.ucf
@@ -82,11 +102,11 @@ ifeq ($(FLOORPLAN), 1)
endif
ifdef BUILD_10G
ETH_SRCS+=$(TEN_GIG_SRCS) $(XGE_SRCS) $(XGE_INTERFACE_SRCS) $(abspath x300_10ge.ucf)
ETH_SRCS+=$(abspath $(TEN_GIG_SRCS)) $(XGE_SRCS) $(XGE_INTERFACE_SRCS) $(abspath x300_10ge.ucf)
endif
ifdef BUILD_1G
ETH_SRCS+=$(ONE_GIG_SRCS) $(abspath x300_1ge.ucf)
ETH_SRCS+=$(abspath $(ONE_GIG_SRCS)) $(abspath x300_1ge.ucf)
endif
ifdef ETH10G_PORT0
@@ -130,26 +150,23 @@ SYNTHESIZE_PROPERTIES = \
"Verilog Macros" "$(EXTRA_DEFS) $(CUSTOM_DEFS)"
TRANSLATE_PROPERTIES = \
"Macro Search Path" "$(shell pwd)/../../coregen/"
"Macro Search Path" "$(shell pwd)/coregen"
MAP_PROPERTIES = \
"Generate Detailed MAP Report" TRUE \
"Allow Logic Optimization Across Hierarchy" TRUE \
"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
"Combinatorial Logic Optimization" TRUE \
"Register Duplication" TRUE \
"Optimization Strategy (Cover Mode)" Speed \
"Map Effort Level" High \
"Extra Effort" Normal \
"Perform Timing-Driven Packing and Placement" TRUE \
"Enable Multi-Threading 2" \
"Starting Placer Cost Table (1-100)" $$(( $$RANDOM % 100 + 1 ))
#"Map to Input Functions" 4 \
"Register Duplication" On \
"Placer Effort Level" High \
"Placer Extra Effort" Normal \
"Enable Multi-Threading" 2 \
"Starting Placer Cost Table (1-100)" $(shell awk 'BEGIN{srand();printf("%d", (100*rand()%100)+1)}')
PLACE_ROUTE_PROPERTIES = \
"Place & Route Effort Level (Overall)" High \
"Extra Effort (Highest PAR level only)" Normal \
"Enable Multi-Threading 4"
"Enable Multi-Threading" 4
STATIC_TIMING_PROPERTIES = \
"Number of Paths in Error/Verbose Report" 10 \
top/x300/coregen/.gitignore
+1
View File
@@ -1,4 +1,5 @@
_xmsgs
*.log
*.ncf
/bootram.ncf
/bootram.xise
top/x300/coregen/Makefile.srcs
+5 -33
View File
@@ -12,8 +12,11 @@ CG_BUILD_DIR = $(BUILD_DIR)/coregen
COREGEN_SRCS = $(abspath $(addprefix $(CG_BUILD_DIR)/, \
input_sample_fifo.v \
input_sample_fifo.xco \
axi64_4k_2clk_fifo.v \
axi64_8k_2clk_fifo.v \
fifo_4k_2clk.v \
fifo_short_2clk.v \
fifo_short_2clk.xco \
radio_clk_gen.v \
radio_clk_gen.xco \
bus_clk_gen.v \
@@ -39,45 +42,14 @@ chipscope_icon.v \
chipscope_icon.xco \
chipscope_icon_2port.v \
chipscope_icon_2port.xco \
fifo_xlnx_16x40_2clk.v \
fifo_xlnx_16x40_2clk.xco \
fifo_short_2clk.v \
fifo_short_2clk.xco \
))
ONE_GIG_SRCS = $(abspath $(addprefix $(CG_SOURCE_DIR)/, \
COREGEN_ONE_GIG_SRCS = $(abspath $(addprefix $(CG_SOURCE_DIR)/, \
gige_sfp_mdio.v \
gige_sfp_mdio/example_design/gige_sfp_mdio_block.v \
gige_sfp_mdio/example_design/gige_sfp_mdio_reset_sync.v \
gige_sfp_mdio/example_design/gige_sfp_mdio_sync_block.v \
gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_transceiver.v \
gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_gtwizard.v \
gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_gtwizard_gt.v \
gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_gtwizard_init.v \
gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_tx_startup_fsm.v \
gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_rx_startup_fsm.v \
gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_recclk_monitor.v \
gige_sfp.v \
gige_sfp/example_design/gige_sfp_block.v \
gige_sfp/example_design/gige_sfp_reset_sync.v \
gige_sfp/example_design/gige_sfp_sync_block.v \
gige_sfp/example_design/transceiver/gige_sfp_transceiver.v \
gige_sfp/example_design/transceiver/gige_sfp_gtwizard.v \
gige_sfp/example_design/transceiver/gige_sfp_gtwizard_gt.v \
gige_sfp/example_design/transceiver/gige_sfp_gtwizard_init.v \
gige_sfp/example_design/transceiver/gige_sfp_tx_startup_fsm.v \
gige_sfp/example_design/transceiver/gige_sfp_rx_startup_fsm.v \
))
TEN_GIG_SRCS = $(abspath $(addprefix $(CG_SOURCE_DIR)/, \
COREGEN_TEN_GIG_SRCS = $(abspath $(addprefix $(CG_SOURCE_DIR)/, \
ten_gig_eth_pcs_pma.v \
ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_x300_top.v \
ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_x300_top.ucf \
ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_block.v \
ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_mod.v \
ten_gig_eth_pcs_pma/example_design/gtx/ten_gig_eth_pcs_pma_gt_usrclk_source.v \
ten_gig_eth_pcs_pma/example_design/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser_gt.v \
ten_gig_eth_pcs_pma/example_design/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser.v \
))
#make rule to regenerate bootram when the coe file is changed
top/x300/coregen/axi64_4k_2clk_fifo.gise
+1 -1
View File
@@ -15,7 +15,7 @@
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
top/x300/coregen/axi64_4k_2clk_fifo.ngc
+1 -1
View File
@@ -1,3 +1,3 @@
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
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e truncated
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truncated
top/x300/coregen/axi64_4k_2clk_fifo.v
+1 -1
View File
@@ -22,7 +22,7 @@
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2013 Xilinx, Inc. *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file axi64_4k_2clk_fifo.v when simulating
top/x300/coregen/axi64_4k_2clk_fifo.veo
+1 -1
View File
@@ -22,7 +22,7 @@
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2013 Xilinx, Inc. *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
top/x300/coregen/axi64_4k_2clk_fifo.xco
+2 -2
View File
@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Fri Jan 25 04:53:45 2013
# Xilinx Core Generator version 14.7
# Date: Wed Sep 3 23:46:32 2014
#
##############################################################
#
top/x300/coregen/axi64_4k_2clk_fifo.xise
+5 -5
View File
@@ -9,10 +9,10 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="axi64_4k_2clk_fifo.ngc" xil_pn:type="FILE_NGC">
@@ -55,7 +55,7 @@
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -339,8 +339,8 @@
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-01-24T20:55:04" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="A947A7A05CBD210362B053B220D1A581" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-09-03T16:47:54" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="B549470EEC291A61A895D80D7556E7AD" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
top/x300/coregen/axi_intercon_2x64_128.ncf
-4
View File
@@ -1,4 +0,0 @@
NET "*_resync*" TNM = FFS "axi_intercon_2x64_128_reset_resync";
NET "*INTERCONNECT_ARESETN" TNM = FFS "axi_intercon_2x64_128_reset_resync";
TIMESPEC "TS_axi_intercon_2x64_128_reset_resync" = TO "axi_intercon_2x64_128_reset_resync" TIG;
top/x300/coregen/axi_intercon_2x64_128.xise
+1 -1
View File
@@ -12,7 +12,7 @@
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="axi_intercon_2x64_128/hdl/verilog/ict106_a_axi3_conv.v" xil_pn:type="FILE_VERILOG">
top/x300/coregen/axi_vfifo_64.gise
-31
View File
@@ -1,31 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="axi_vfifo_64.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_VEO" xil_pn:name="axi_vfifo_64.veo" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="axi_vfifo_ctrl_v1_1_readme.txt" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
top/x300/coregen/axi_vfifo_64.ngc
-3
View File
@@ -1,3 +0,0 @@
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
$3`b6~753-Xnzd}foo8#5+421).97 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truncated
top/x300/coregen/axi_vfifo_64.v
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top/x300/coregen/axi_vfifo_64.veo
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/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2012 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
/*******************************************************************************
* Generated from core with identifier: xilinx.com:ip:axi_vfifo_ctrl:1.1 *
* *
* The AXI Virtual FIFO Controller is a parameterizable number of multi *
* channel FIFO. *
*******************************************************************************/
// Interfaces:
// AXI4Stream_MASTER_M_AXIS
// AXI4Stream_SLAVE_S_AXIS
// AXI4_MASTER_M_AXI
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
axi_vfifo_64 your_instance_name (
.aclk(aclk), // input aclk
.aresetn(aresetn), // input aresetn
.m_axi_awid(m_axi_awid), // output [0 : 0] m_axi_awid
.m_axi_awaddr(m_axi_awaddr), // output [31 : 0] m_axi_awaddr
.m_axi_awlen(m_axi_awlen), // output [7 : 0] m_axi_awlen
.m_axi_awsize(m_axi_awsize), // output [2 : 0] m_axi_awsize
.m_axi_awburst(m_axi_awburst), // output [1 : 0] m_axi_awburst
.m_axi_awlock(m_axi_awlock), // output [0 : 0] m_axi_awlock
.m_axi_awcache(m_axi_awcache), // output [3 : 0] m_axi_awcache
.m_axi_awprot(m_axi_awprot), // output [2 : 0] m_axi_awprot
.m_axi_awqos(m_axi_awqos), // output [3 : 0] m_axi_awqos
.m_axi_awregion(m_axi_awregion), // output [3 : 0] m_axi_awregion
.m_axi_awuser(m_axi_awuser), // output [0 : 0] m_axi_awuser
.m_axi_awvalid(m_axi_awvalid), // output m_axi_awvalid
.m_axi_awready(m_axi_awready), // input m_axi_awready
.m_axi_wdata(m_axi_wdata), // output [63 : 0] m_axi_wdata
.m_axi_wstrb(m_axi_wstrb), // output [7 : 0] m_axi_wstrb
.m_axi_wlast(m_axi_wlast), // output m_axi_wlast
.m_axi_wuser(m_axi_wuser), // output [0 : 0] m_axi_wuser
.m_axi_wvalid(m_axi_wvalid), // output m_axi_wvalid
.m_axi_wready(m_axi_wready), // input m_axi_wready
.m_axi_bid(m_axi_bid), // input [0 : 0] m_axi_bid
.m_axi_bresp(m_axi_bresp), // input [1 : 0] m_axi_bresp
.m_axi_buser(m_axi_buser), // input [0 : 0] m_axi_buser
.m_axi_bvalid(m_axi_bvalid), // input m_axi_bvalid
.m_axi_bready(m_axi_bready), // output m_axi_bready
.m_axi_arid(m_axi_arid), // output [0 : 0] m_axi_arid
.m_axi_araddr(m_axi_araddr), // output [31 : 0] m_axi_araddr
.m_axi_arlen(m_axi_arlen), // output [7 : 0] m_axi_arlen
.m_axi_arsize(m_axi_arsize), // output [2 : 0] m_axi_arsize
.m_axi_arburst(m_axi_arburst), // output [1 : 0] m_axi_arburst
.m_axi_arlock(m_axi_arlock), // output [0 : 0] m_axi_arlock
.m_axi_arcache(m_axi_arcache), // output [3 : 0] m_axi_arcache
.m_axi_arprot(m_axi_arprot), // output [2 : 0] m_axi_arprot
.m_axi_arqos(m_axi_arqos), // output [3 : 0] m_axi_arqos
.m_axi_arregion(m_axi_arregion), // output [3 : 0] m_axi_arregion
.m_axi_aruser(m_axi_aruser), // output [0 : 0] m_axi_aruser
.m_axi_arvalid(m_axi_arvalid), // output m_axi_arvalid
.m_axi_arready(m_axi_arready), // input m_axi_arready
.m_axi_rid(m_axi_rid), // input [0 : 0] m_axi_rid
.m_axi_rdata(m_axi_rdata), // input [63 : 0] m_axi_rdata
.m_axi_rresp(m_axi_rresp), // input [1 : 0] m_axi_rresp
.m_axi_rlast(m_axi_rlast), // input m_axi_rlast
.m_axi_ruser(m_axi_ruser), // input [0 : 0] m_axi_ruser
.m_axi_rvalid(m_axi_rvalid), // input m_axi_rvalid
.m_axi_rready(m_axi_rready), // output m_axi_rready
.s_axis_tvalid(s_axis_tvalid), // input s_axis_tvalid
.s_axis_tready(s_axis_tready), // output s_axis_tready
.s_axis_tdata(s_axis_tdata), // input [63 : 0] s_axis_tdata
.s_axis_tstrb(s_axis_tstrb), // input [7 : 0] s_axis_tstrb
.s_axis_tkeep(s_axis_tkeep), // input [7 : 0] s_axis_tkeep
.s_axis_tlast(s_axis_tlast), // input s_axis_tlast
.s_axis_tid(s_axis_tid), // input [0 : 0] s_axis_tid
.s_axis_tdest(s_axis_tdest), // input [0 : 0] s_axis_tdest
.m_axis_tvalid(m_axis_tvalid), // output m_axis_tvalid
.m_axis_tready(m_axis_tready), // input m_axis_tready
.m_axis_tdata(m_axis_tdata), // output [63 : 0] m_axis_tdata
.m_axis_tstrb(m_axis_tstrb), // output [7 : 0] m_axis_tstrb
.m_axis_tkeep(m_axis_tkeep), // output [7 : 0] m_axis_tkeep
.m_axis_tlast(m_axis_tlast), // output m_axis_tlast
.m_axis_tid(m_axis_tid), // output [0 : 0] m_axis_tid
.m_axis_tdest(m_axis_tdest), // output [0 : 0] m_axis_tdest
.vfifo_mm2s_channel_full(vfifo_mm2s_channel_full), // input [1 : 0] vfifo_mm2s_channel_full
.vfifo_s2mm_channel_full(vfifo_s2mm_channel_full), // output [1 : 0] vfifo_s2mm_channel_full
.vfifo_mm2s_channel_empty(vfifo_mm2s_channel_empty), // output [1 : 0] vfifo_mm2s_channel_empty
.vfifo_mm2s_rresp_err_intr(vfifo_mm2s_rresp_err_intr), // output vfifo_mm2s_rresp_err_intr
.vfifo_s2mm_bresp_err_intr(vfifo_s2mm_bresp_err_intr), // output vfifo_s2mm_bresp_err_intr
.vfifo_s2mm_overrun_err_intr(vfifo_s2mm_overrun_err_intr), // output vfifo_s2mm_overrun_err_intr
.vfifo_idle(vfifo_idle) // output [1 : 0] vfifo_idle
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file axi_vfifo_64.v when simulating
// the core, axi_vfifo_64. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
top/x300/coregen/axi_vfifo_64.xco
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##############################################################
#
# Xilinx Core Generator version 14.3
# Date: Thu Nov 22 06:37:07 2012
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:axi_vfifo_ctrl:1.1
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc7k410t
SET devicefamily = kintex7
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg900
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT AXI_Virtual_FIFO_Controller xilinx.com:ip:axi_vfifo_ctrl:1.1
# END Select
# BEGIN Parameters
CSET ar_weight_ch0=8
CSET ar_weight_ch1=8
CSET ar_weight_ch2=8
CSET ar_weight_ch3=8
CSET ar_weight_ch4=8
CSET ar_weight_ch5=8
CSET ar_weight_ch6=8
CSET ar_weight_ch7=8
CSET axi_burst_size=512
CSET axis_tdata_width=64
CSET axis_tuser_width=1
CSET component_name=axi_vfifo_64
CSET deassert_tready=false
CSET dram_base_addr=80000000
CSET enable_axis_tid=true
CSET enable_axis_tuser=false
CSET enable_interrupt=true
CSET implementation_type=Burst_Mode
CSET number_of_channel=2
CSET number_of_page_ch0=4096
CSET number_of_page_ch1=4096
CSET number_of_page_ch2=8
CSET number_of_page_ch3=8
CSET number_of_page_ch4=8
CSET number_of_page_ch5=8
CSET number_of_page_ch6=8
CSET number_of_page_ch7=8
CSET s2mm_txn_timeout_value=8
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-06-21T19:48:53Z
# END Extra information
GENERATE
# CRC: 70c312ac
top/x300/coregen/axi_vfifo_64.xise
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.3" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="axi_vfifo_64.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="axi_vfifo_64.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="axi_vfifo_64_synth.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
</file>
</files>
<properties>
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
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<property xil_pn:name="Device" xil_pn:value="xc7k410t" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="axi_vfifo_64" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="kintex7" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-11-21T22:41:11" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="3942A9152040FE847FC0E42F7693A8B2" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
top/x300/coregen/axi_vfifo_64/doc/axi_vfifo_ctrl_v1_1_readme.txt
-189
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CHANGE LOG for LogiCORE AXI Virtual FIFO Controller V1.1
Core name: Xilinx LogiCORE AXI Virtual FIFO Controller
Version: 1.1
Release: ISE 14.2 / Vivado 2012.2
Release Date: July 25, 2012
--------------------------------------------------------------------------------
Table of Contents
1. INTRODUCTION
2. DEVICE SUPPORT
3. NEW FEATURES HISTORY
4. RESOLVED ISSUES
5. KNOWN ISSUES & LIMITATIONS
6. TECHNICAL SUPPORT & FEEDBACK
7. CORE RELEASE HISTORY
8. LEGAL DISCLAIMER
--------------------------------------------------------------------------------
1. INTRODUCTION
For installation instructions for this release, please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
This file contains release notes for the Xilinx LogiCORE IP AXI Virtual FIFO Controller v1.1
solution. For the latest core updates, see the product page at:
http://www.xilinx.com/products/intellectual-property/axi_virtual_fifo_controller.htm
................................................................................
2. DEVICE SUPPORT
2.1 ISE
The following device families are supported by the core for this release.
All 7 Series devices
Zynq-7000 devices
All Virtex-6 devices
All Spartan-6 devices
2.2 Vivado
All 7 Series devices
Zynq-7000 devices
................................................................................
3. NEW FEATURES HISTORY
3.1 ISE
- First release
- ISE 14.2 software support
3.2 Vivado
- First release
- 2012.2 software support
................................................................................
4. RESOLVED ISSUES
4.1 ISE
- N/A
4.2 Vivado
- N/A
................................................................................
5. KNOWN ISSUES & LIMITATIONS
5.1 ISE
- N/A
5.2 Vivado
- N/A
The most recent information, including known issues, workarounds, and
resolutions for this version is provided in the IP Release Notes User Guide
located at
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
................................................................................
6. TECHNICAL SUPPORT & FEEDBACK
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
................................................................................
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
07/25/2012 Xilinx, Inc. 1.1 First release; ISE 14.2 and Vivado 2012.2 support.
04/24/2012 Xilinx, Inc. 1.1 First release; ISE 14.1 and Vivado 2012.1 support.
================================================================================
................................................................................
8. LEGAL DISCLAIMER
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
top/x300/coregen/axi_vfifo_64/doc/axi_vfifo_ctrl_v1_1_vinfo.html
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<HTML>
<HEAD>
<TITLE>axi_vfifo_ctrl_v1_1_vinfo</TITLE>
<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
</HEAD>
<BODY>
<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
CHANGE LOG for LogiCORE AXI Virtual FIFO Controller V1.1
Core name: Xilinx LogiCORE AXI Virtual FIFO Controller
Version: 1.1
Release: ISE 14.2 / Vivado 2012.2
Release Date: July 25, 2012
--------------------------------------------------------------------------------
Table of Contents
1. INTRODUCTION
2. DEVICE SUPPORT
3. NEW FEATURES HISTORY
4. RESOLVED ISSUES
5. KNOWN ISSUES & LIMITATIONS
6. TECHNICAL SUPPORT & FEEDBACK
7. CORE RELEASE HISTORY
8. LEGAL DISCLAIMER
--------------------------------------------------------------------------------
1. INTRODUCTION
For installation instructions for this release, please go to:
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
For system requirements:
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
This file contains release notes for the Xilinx LogiCORE IP AXI Virtual FIFO Controller v1.1
solution. For the latest core updates, see the product page at:
<A HREF="http://www.xilinx.com/products/intellectual-property/axi_virtual_fifo_controller.htm">www.xilinx.com/products/intellectual-property/axi_virtual_fifo_controller.htm</A>
................................................................................
2. DEVICE SUPPORT
2.1 ISE
The following device families are supported by the core for this release.
All 7 Series devices
Zynq-7000 devices
All Virtex-6 devices
All Spartan-6 devices
2.2 Vivado
All 7 Series devices
Zynq-7000 devices
................................................................................
3. NEW FEATURES HISTORY
3.1 ISE
- First release
- ISE 14.2 software support
3.2 Vivado
- First release
- 2012.2 software support
................................................................................
4. RESOLVED ISSUES
4.1 ISE
- N/A
4.2 Vivado
- N/A
................................................................................
5. KNOWN ISSUES & LIMITATIONS
5.1 ISE
- N/A
5.2 Vivado
- N/A
The most recent information, including known issues, workarounds, and
resolutions for this version is provided in the IP Release Notes User Guide
located at
<A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
................................................................................
6. TECHNICAL SUPPORT & FEEDBACK
To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
................................................................................
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
07/25/2012 Xilinx, Inc. 1.1 First release; ISE 14.2 and Vivado 2012.2 support.
04/24/2012 Xilinx, Inc. 1.1 First release; ISE 14.1 and Vivado 2012.1 support.
================================================================================
................................................................................
8. LEGAL DISCLAIMER
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
</FONT>
</PRE>
</BODY>
</HTML>
top/x300/coregen/axi_vfifo_64/doc/pg038_axi_vfifo_ctrl.pdf
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top/x300/coregen/axi_vfifo_64/example_design/axi_vfifo_64_exdes.ucf
-56
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################################################################################
# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
################################################################################
# Core Period Constraint. This constraint can be modified, and is
# valid as long as it is met after place and route.
NET "ACLK" TNM_NET = "ACLK";
TIMESPEC "TS_ACLK" = PERIOD "ACLK" 50 MHZ;
################################################################################
top/x300/coregen/axi_vfifo_64/example_design/axi_vfifo_64_exdes.vhd
-370
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@@ -1,370 +0,0 @@
--------------------------------------------------------------------------------
--
-- AXI Virtual FIFO Controller Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: axi_vfifo_64_exdes.vhd
--
-- Description:
-- This is the VFIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity axi_vfifo_64_exdes is
PORT (
-- AXI Stream Input Signals From Switch to AXI Virtual FIFO Controller (AVFC)
S_AXIS_TVALID : IN STD_LOGIC := '0';
S_AXIS_TREADY : OUT STD_LOGIC := '0';
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TSTRB : IN STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TKEEP : IN STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TLAST : IN STD_LOGIC := '0';
S_AXIS_TID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TDEST : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
-- AXI Virtual FIFO Controller (AVFC) Output Signals To AXI Stream Switch
M_AXIS_TVALID : OUT STD_LOGIC := '0';
M_AXIS_TREADY : IN STD_LOGIC := '0';
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TSTRB : OUT STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS => '1');
M_AXIS_TKEEP : OUT STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TLAST : OUT STD_LOGIC := '0';
M_AXIS_TID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TDEST : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
-- Write Address Channel Signals
M_AXI_AWID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLOCK : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWQOS : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWREGION : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWVALID : OUT STD_LOGIC := '0';
M_AXI_AWREADY : IN STD_LOGIC := '0';
-- Write Data Channel Signals
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(64 / 8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WLAST : OUT STD_LOGIC := '0';
M_AXI_WUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WVALID : OUT STD_LOGIC := '0';
M_AXI_WREADY : IN STD_LOGIC := '0';
-- Write Response Channel Signals
M_AXI_BID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_BRESP : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_BUSER : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_BVALID : IN STD_LOGIC := '0';
M_AXI_BREADY : OUT STD_LOGIC := '1';
-- Read Address Channel Signals
M_AXI_ARID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLOCK : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARQOS : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARREGION : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARVALID : OUT STD_LOGIC := '0';
M_AXI_ARREADY : IN STD_LOGIC := '0';
-- Read Data Channel Signals
M_AXI_RID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RDATA : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RRESP : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RLAST : IN STD_LOGIC := '0';
M_AXI_RUSER : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RVALID : IN STD_LOGIC := '0';
M_AXI_RREADY : OUT STD_LOGIC := '0';
-- External Interface Signals
VFIFO_MM2S_CHANNEL_FULL : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
VFIFO_S2MM_CHANNEL_FULL : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
VFIFO_MM2S_CHANNEL_EMPTY : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'1');
-- Status Signal
VFIFO_IDLE : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'1');
-- Interrupt Signals
VFIFO_MM2S_RRESP_ERR_INTR : OUT STD_LOGIC := '0';
VFIFO_S2MM_BRESP_ERR_INTR : OUT STD_LOGIC := '0';
VFIFO_S2MM_OVERRUN_ERR_INTR : OUT STD_LOGIC := '0';
-- Global Signals
ACLK : IN STD_LOGIC := '0';
ARESETN : IN STD_LOGIC := '0'
);
end axi_vfifo_64_exdes;
architecture xilinx of axi_vfifo_64_exdes is
signal s_aclk_i : std_logic;
component axi_vfifo_64 is
PORT (
-- AXI Stream Input Signals From Switch to AXI Virtual FIFO Controller (AVFC)
S_AXIS_TVALID : IN STD_LOGIC := '0';
S_AXIS_TREADY : OUT STD_LOGIC := '0';
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TSTRB : IN STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TKEEP : IN STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TLAST : IN STD_LOGIC := '0';
S_AXIS_TID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TDEST : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
-- AXI Virtual FIFO Controller (AVFC) Output Signals To AXI Stream Switch
M_AXIS_TVALID : OUT STD_LOGIC := '0';
M_AXIS_TREADY : IN STD_LOGIC := '0';
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TSTRB : OUT STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS => '1');
M_AXIS_TKEEP : OUT STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TLAST : OUT STD_LOGIC := '0';
M_AXIS_TID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TDEST : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
-- Write Address Channel Signals
M_AXI_AWID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLOCK : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWQOS : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWREGION : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWVALID : OUT STD_LOGIC := '0';
M_AXI_AWREADY : IN STD_LOGIC := '0';
-- Write Data Channel Signals
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(64 / 8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WLAST : OUT STD_LOGIC := '0';
M_AXI_WUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WVALID : OUT STD_LOGIC := '0';
M_AXI_WREADY : IN STD_LOGIC := '0';
-- Write Response Channel Signals
M_AXI_BID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_BRESP : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_BUSER : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_BVALID : IN STD_LOGIC := '0';
M_AXI_BREADY : OUT STD_LOGIC := '1';
-- Read Address Channel Signals
M_AXI_ARID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLOCK : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARQOS : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARREGION : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARVALID : OUT STD_LOGIC := '0';
M_AXI_ARREADY : IN STD_LOGIC := '0';
-- Read Data Channel Signals
M_AXI_RID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RDATA : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RRESP : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RLAST : IN STD_LOGIC := '0';
M_AXI_RUSER : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RVALID : IN STD_LOGIC := '0';
M_AXI_RREADY : OUT STD_LOGIC := '0';
-- External Interface Signals
VFIFO_MM2S_CHANNEL_FULL : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
VFIFO_S2MM_CHANNEL_FULL : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
VFIFO_MM2S_CHANNEL_EMPTY : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'1');
-- Status Signal
VFIFO_IDLE : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'1');
-- Interrupt Signals
VFIFO_MM2S_RRESP_ERR_INTR : OUT STD_LOGIC := '0';
VFIFO_S2MM_BRESP_ERR_INTR : OUT STD_LOGIC := '0';
VFIFO_S2MM_OVERRUN_ERR_INTR : OUT STD_LOGIC := '0';
-- Global Signals
ACLK : IN STD_LOGIC := '0';
ARESETN : IN STD_LOGIC := '0'
);
end component;
begin
s_aclk_buf: bufg
PORT map(
i => ACLK,
o => s_aclk_i
);
exdes_inst : axi_vfifo_64
PORT MAP (
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TSTRB => S_AXIS_TSTRB,
S_AXIS_TKEEP => S_AXIS_TKEEP,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TID => S_AXIS_TID,
S_AXIS_TDEST => S_AXIS_TDEST,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TREADY => M_AXIS_TREADY,
M_AXIS_TDATA => M_AXIS_TDATA,
M_AXIS_TSTRB => M_AXIS_TSTRB,
M_AXIS_TKEEP => M_AXIS_TKEEP,
M_AXIS_TLAST => M_AXIS_TLAST,
M_AXIS_TID => M_AXIS_TID,
M_AXIS_TDEST => M_AXIS_TDEST,
M_AXI_AWID => M_AXI_AWID,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWLEN => M_AXI_AWLEN,
M_AXI_AWSIZE => M_AXI_AWSIZE,
M_AXI_AWBURST => M_AXI_AWBURST,
M_AXI_AWLOCK => M_AXI_AWLOCK,
M_AXI_AWCACHE => M_AXI_AWCACHE,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWQOS => M_AXI_AWQOS,
M_AXI_AWREGION => M_AXI_AWREGION,
M_AXI_AWUSER => M_AXI_AWUSER,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WLAST => M_AXI_WLAST,
M_AXI_WUSER => M_AXI_WUSER,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_BID => M_AXI_BID,
M_AXI_BRESP => M_AXI_BRESP,
M_AXI_BUSER => M_AXI_BUSER,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_ARID => M_AXI_ARID,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARLEN => M_AXI_ARLEN,
M_AXI_ARSIZE => M_AXI_ARSIZE,
M_AXI_ARBURST => M_AXI_ARBURST,
M_AXI_ARLOCK => M_AXI_ARLOCK,
M_AXI_ARCACHE => M_AXI_ARCACHE,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARQOS => M_AXI_ARQOS,
M_AXI_ARREGION => M_AXI_ARREGION,
M_AXI_ARUSER => M_AXI_ARUSER,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_RID => M_AXI_RID,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RLAST => M_AXI_RLAST,
M_AXI_RUSER => M_AXI_RUSER,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RREADY => M_AXI_RREADY,
-- External Interface Signals
VFIFO_MM2S_CHANNEL_FULL => VFIFO_MM2S_CHANNEL_FULL,
VFIFO_MM2S_CHANNEL_EMPTY => VFIFO_MM2S_CHANNEL_EMPTY,
VFIFO_S2MM_CHANNEL_FULL => VFIFO_S2MM_CHANNEL_FULL,
-- Status Signal
VFIFO_IDLE => VFIFO_IDLE,
-- Interrupt Signals
VFIFO_MM2S_RRESP_ERR_INTR => VFIFO_MM2S_RRESP_ERR_INTR,
VFIFO_S2MM_BRESP_ERR_INTR => VFIFO_S2MM_BRESP_ERR_INTR,
VFIFO_S2MM_OVERRUN_ERR_INTR => VFIFO_S2MM_OVERRUN_ERR_INTR,
ACLK => s_aclk_i,
ARESETN => ARESETN
);
end xilinx;
top/x300/coregen/axi_vfifo_64/example_design/axi_vfifo_64_exdes.xdc
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@@ -1,55 +0,0 @@
################################################################################
# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
################################################################################
# Core Period Constraint. This constraint can be modified, and is
# valid as long as it is met after place and route.
create_clock -name "TS_ACLK" -period 20.0 [ get_ports ACLK ]
################################################################################
top/x300/coregen/axi_vfifo_64/implement/implement.bat
-88
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@@ -1,88 +0,0 @@
rem (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
rem
rem This file contains confidential and proprietary information
rem of Xilinx, Inc. and is protected under U.S. and
rem international copyright and other intellectual property
rem laws.
rem
rem DISCLAIMER
rem This disclaimer is not a license and does not grant any
rem rights to the materials distributed herewith. Except as
rem otherwise provided in a valid license issued to you by
rem Xilinx, and to the maximum extent permitted by applicable
rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
rem (2) Xilinx shall not be liable (whether in contract or tort,
rem including negligence, or under any other theory of
rem liability) for any loss or damage of any kind or nature
rem related to, arising under or in connection with these
rem materials, including for any direct, or any indirect,
rem special, incidental, or consequential loss or damage
rem (including loss of data, profits, goodwill, or any type of
rem loss or damage suffered as a result of any action brought
rem by a third party) even if such damage or loss was
rem reasonably foreseeable or Xilinx had been advised of the
rem possibility of the same.
rem
rem CRITICAL APPLICATIONS
rem Xilinx products are not designed or intended to be fail-
rem safe, or for use in any application requiring fail-safe
rem performance, such as life-support or safety devices or
rem systems, Class III medical devices, nuclear facilities,
rem applications related to the deployment of airbags, or any
rem other applications that could lead to death, personal
rem injury, or severe property or environmental damage
rem (individually and collectively, "Critical
rem Applications"). Customer assumes the sole risk and
rem liability of any use of Xilinx products in Critical
rem Applications, subject only to applicable laws and
rem regulations governing limitations on product liability.
rem
rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
rem PART OF THIS FILE AT ALL TIMES.
rem Clean up the results directory
rmdir /S /Q results
mkdir results
rem Synthesize the VHDL Wrapper Files
#Synthesize the Wrapper Files
echo 'Synthesizing example design with XST';
xst -ifn xst.scr
copy axi_vfifo_64_exdes.ngc .\results\
rem Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
copy ..\..\axi_vfifo_64.ngc results\
rem Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
copy ..\example_design\axi_vfifo_64_exdes.ucf results\
cd results
echo 'Running ngdbuild'
ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi_vfifo_64_exdes
echo 'Running map'
map axi_vfifo_64_exdes -o mapped.ncd
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed -g UnconstrainedPins:Allow
echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -sim -tm axi_vfifo_64_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
top/x300/coregen/axi_vfifo_64/implement/implement.sh
-87
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@@ -1,87 +0,0 @@
#!/bin/sh
# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
# Clean up the results directory
rm -rf results
mkdir results
#Synthesize the Wrapper Files
echo 'Synthesizing example design with XST';
xst -ifn xst.scr
cp axi_vfifo_64_exdes.ngc ./results/
# Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
cp ../../axi_vfifo_64.ngc results/
# Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
cp ../example_design/axi_vfifo_64_exdes.ucf results/
cd results
echo 'Running ngdbuild'
ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi_vfifo_64_exdes
echo 'Running map'
map axi_vfifo_64_exdes -o mapped.ncd
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed -g UnconstrainedPins:Allow
echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -sim -tm axi_vfifo_64_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
top/x300/coregen/axi_vfifo_64/implement/implement_synplify.bat
-87
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@@ -1,87 +0,0 @@
rem (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
rem
rem This file contains confidential and proprietary information
rem of Xilinx, Inc. and is protected under U.S. and
rem international copyright and other intellectual property
rem laws.
rem
rem DISCLAIMER
rem This disclaimer is not a license and does not grant any
rem rights to the materials distributed herewith. Except as
rem otherwise provided in a valid license issued to you by
rem Xilinx, and to the maximum extent permitted by applicable
rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
rem (2) Xilinx shall not be liable (whether in contract or tort,
rem including negligence, or under any other theory of
rem liability) for any loss or damage of any kind or nature
rem related to, arising under or in connection with these
rem materials, including for any direct, or any indirect,
rem special, incidental, or consequential loss or damage
rem (including loss of data, profits, goodwill, or any type of
rem loss or damage suffered as a result of any action brought
rem by a third party) even if such damage or loss was
rem reasonably foreseeable or Xilinx had been advised of the
rem possibility of the same.
rem
rem CRITICAL APPLICATIONS
rem Xilinx products are not designed or intended to be fail-
rem safe, or for use in any application requiring fail-safe
rem performance, such as life-support or safety devices or
rem systems, Class III medical devices, nuclear facilities,
rem applications related to the deployment of airbags, or any
rem other applications that could lead to death, personal
rem injury, or severe property or environmental damage
rem (individually and collectively, "Critical
rem Applications"). Customer assumes the sole risk and
rem liability of any use of Xilinx products in Critical
rem Applications, subject only to applicable laws and
rem regulations governing limitations on product liability.
rem
rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
rem PART OF THIS FILE AT ALL TIMES.
rem Clean up the results directory
rmdir /S /Q results
mkdir results
rem Synthesize the VHDL Wrapper Files
#Synthesize the Wrapper Files
echo 'Synthesizing example design with Synplify'
synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx
rem Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
copy ..\..\axi_vfifo_64.ngc results\
rem Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
copy ..\example_design\axi_vfifo_64_exdes.ucf results\
cd results
echo 'Running ngdbuild'
ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi_vfifo_64_exdes
echo 'Running map'
map axi_vfifo_64_exdes -o mapped.ncd
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed -g UnconstrainedPins:Allow
echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -sim -tm axi_vfifo_64_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
top/x300/coregen/axi_vfifo_64/implement/implement_synplify.sh
-86
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@@ -1,86 +0,0 @@
#!/bin/sh
# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
# Clean up the results directory
rm -rf results
mkdir results
#Synthesize the Wrapper Files
echo 'Synthesizing example design with Synplify'
synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx
# Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
cp ../../axi_vfifo_64.ngc results/
# Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
cp ../example_design/axi_vfifo_64_exdes.ucf results/
cd results
echo 'Running ngdbuild'
ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi_vfifo_64_exdes
echo 'Running map'
map axi_vfifo_64_exdes -o mapped.ncd
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed -g UnconstrainedPins:Allow
echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -sim -tm axi_vfifo_64_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
top/x300/coregen/axi_vfifo_64/implement/planAhead_ise.bat
-54
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@@ -1,54 +0,0 @@
rem (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
rem
rem This file contains confidential and proprietary information
rem of Xilinx, Inc. and is protected under U.S. and
rem international copyright and other intellectual property
rem laws.
rem
rem DISCLAIMER
rem This disclaimer is not a license and does not grant any
rem rights to the materials distributed herewith. Except as
rem otherwise provided in a valid license issued to you by
rem Xilinx, and to the maximum extent permitted by applicable
rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
rem (2) Xilinx shall not be liable (whether in contract or tort,
rem including negligence, or under any other theory of
rem liability) for any loss or damage of any kind or nature
rem related to, arising under or in connection with these
rem materials, including for any direct, or any indirect,
rem special, incidental, or consequential loss or damage
rem (including loss of data, profits, goodwill, or any type of
rem loss or damage suffered as a result of any action brought
rem by a third party) even if such damage or loss was
rem reasonably foreseeable or Xilinx had been advised of the
rem possibility of the same.
rem
rem CRITICAL APPLICATIONS
rem Xilinx products are not designed or intended to be fail-
rem safe, or for use in any application requiring fail-safe
rem performance, such as life-support or safety devices or
rem systems, Class III medical devices, nuclear facilities,
rem applications related to the deployment of airbags, or any
rem other applications that could lead to death, personal
rem injury, or severe property or environmental damage
rem (individually and collectively, "Critical
rem Applications"). Customer assumes the sole risk and
rem liability of any use of Xilinx products in Critical
rem Applications, subject only to applicable laws and
rem regulations governing limitations on product liability.
rem
rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
rem PART OF THIS FILE AT ALL TIMES.
rem -----------------------------------------------------------------------------
rem Script to synthesize and implement the Coregen FIFO Generator
rem -----------------------------------------------------------------------------
rmdir /S /Q results
mkdir results
cd results
copy ..\..\..\axi_vfifo_64.ngc .
planAhead -mode batch -source ..\planAhead_ise.tcl
top/x300/coregen/axi_vfifo_64/implement/planAhead_ise.sh
-55
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@@ -1,55 +0,0 @@
#!/bin/sh
# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#-----------------------------------------------------------------------------
# Script to synthesize and implement the Coregen FIFO Generator
#-----------------------------------------------------------------------------
rm -rf results
mkdir results
cd results
cp ../../../axi_vfifo_64.ngc .
planAhead -mode batch -source ../planAhead_ise.tcl
top/x300/coregen/axi_vfifo_64/implement/planAhead_ise.tcl
-67
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@@ -1,67 +0,0 @@
# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
set device xc7k410tffg900-2
set projName axi_vfifo_64
set design axi_vfifo_64
set projDir [file dirname [info script]]
create_project $projName $projDir/results/$projName -part $device -force
set_property design_mode RTL [current_fileset -srcset]
set top_module axi_vfifo_64_exdes
add_files -norecurse {../../example_design/axi_vfifo_64_exdes.vhd}
add_files -norecurse {./axi_vfifo_64.ngc}
import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/axi_vfifo_64_exdes.xdc}
set_property top axi_vfifo_64_exdes [get_property srcset [current_run]]
synth_design
opt_design
place_design
route_design
write_sdf -rename_top_module axi_vfifo_64_exdes -file routed.sdf
write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module axi_vfifo_64_exdes routed.v
report_timing -nworst 30 -path_type full -file routed.twr
report_drc -file report.drc
write_bitstream -bitgen_options {-g UnconstrainedPins:Allow}
top/x300/coregen/axi_vfifo_64/implement/xst.prj
-1
View File
@@ -1 +0,0 @@
work ../example_design/axi_vfifo_64_exdes.vhd
top/x300/coregen/axi_vfifo_64/implement/xst.scr
-13
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@@ -1,13 +0,0 @@
run
-ifmt VHDL
-ent axi_vfifo_64_exdes
-p xc7k410t-ffg900-2
-ifn xst.prj
-write_timing_constraints No
-iobuf YES
-max_fanout 100
-ofn axi_vfifo_64_exdes
-ofmt NGC
-bus_delimiter ()
-hierarchy_separator /
-case Maintain
top/x300/coregen/axi_vfifo_64_0x0.gise
-31
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@@ -1,31 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="axi_vfifo_64_0x0.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_VEO" xil_pn:name="axi_vfifo_64_0x0.veo" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="axi_vfifo_ctrl_v1_1_readme.txt" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
top/x300/coregen/axi_vfifo_64_0x0.ncf
View File
Whitespace-only changes.
top/x300/coregen/axi_vfifo_64_0x0.ngc
-3
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@@ -1,3 +0,0 @@
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
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top/x300/coregen/axi_vfifo_64_0x0.v
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top/x300/coregen/axi_vfifo_64_0x0.veo
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/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2013 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
/*******************************************************************************
* Generated from core with identifier: xilinx.com:ip:axi_vfifo_ctrl:1.1 *
* *
* Rev 1. The AXI Virtual FIFO Controller is a parameterizable number of *
* multi channel FIFO. *
*******************************************************************************/
// Interfaces:
// AXI4Stream_MASTER_M_AXIS
// AXI4Stream_SLAVE_S_AXIS
// AXI4_MASTER_M_AXI
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
axi_vfifo_64_0x0 your_instance_name (
.aclk(aclk), // input aclk
.aresetn(aresetn), // input aresetn
.m_axi_awid(m_axi_awid), // output [0 : 0] m_axi_awid
.m_axi_awaddr(m_axi_awaddr), // output [31 : 0] m_axi_awaddr
.m_axi_awlen(m_axi_awlen), // output [7 : 0] m_axi_awlen
.m_axi_awsize(m_axi_awsize), // output [2 : 0] m_axi_awsize
.m_axi_awburst(m_axi_awburst), // output [1 : 0] m_axi_awburst
.m_axi_awlock(m_axi_awlock), // output [0 : 0] m_axi_awlock
.m_axi_awcache(m_axi_awcache), // output [3 : 0] m_axi_awcache
.m_axi_awprot(m_axi_awprot), // output [2 : 0] m_axi_awprot
.m_axi_awqos(m_axi_awqos), // output [3 : 0] m_axi_awqos
.m_axi_awregion(m_axi_awregion), // output [3 : 0] m_axi_awregion
.m_axi_awuser(m_axi_awuser), // output [0 : 0] m_axi_awuser
.m_axi_awvalid(m_axi_awvalid), // output m_axi_awvalid
.m_axi_awready(m_axi_awready), // input m_axi_awready
.m_axi_wdata(m_axi_wdata), // output [63 : 0] m_axi_wdata
.m_axi_wstrb(m_axi_wstrb), // output [7 : 0] m_axi_wstrb
.m_axi_wlast(m_axi_wlast), // output m_axi_wlast
.m_axi_wuser(m_axi_wuser), // output [0 : 0] m_axi_wuser
.m_axi_wvalid(m_axi_wvalid), // output m_axi_wvalid
.m_axi_wready(m_axi_wready), // input m_axi_wready
.m_axi_bid(m_axi_bid), // input [0 : 0] m_axi_bid
.m_axi_bresp(m_axi_bresp), // input [1 : 0] m_axi_bresp
.m_axi_buser(m_axi_buser), // input [0 : 0] m_axi_buser
.m_axi_bvalid(m_axi_bvalid), // input m_axi_bvalid
.m_axi_bready(m_axi_bready), // output m_axi_bready
.m_axi_arid(m_axi_arid), // output [0 : 0] m_axi_arid
.m_axi_araddr(m_axi_araddr), // output [31 : 0] m_axi_araddr
.m_axi_arlen(m_axi_arlen), // output [7 : 0] m_axi_arlen
.m_axi_arsize(m_axi_arsize), // output [2 : 0] m_axi_arsize
.m_axi_arburst(m_axi_arburst), // output [1 : 0] m_axi_arburst
.m_axi_arlock(m_axi_arlock), // output [0 : 0] m_axi_arlock
.m_axi_arcache(m_axi_arcache), // output [3 : 0] m_axi_arcache
.m_axi_arprot(m_axi_arprot), // output [2 : 0] m_axi_arprot
.m_axi_arqos(m_axi_arqos), // output [3 : 0] m_axi_arqos
.m_axi_arregion(m_axi_arregion), // output [3 : 0] m_axi_arregion
.m_axi_aruser(m_axi_aruser), // output [0 : 0] m_axi_aruser
.m_axi_arvalid(m_axi_arvalid), // output m_axi_arvalid
.m_axi_arready(m_axi_arready), // input m_axi_arready
.m_axi_rid(m_axi_rid), // input [0 : 0] m_axi_rid
.m_axi_rdata(m_axi_rdata), // input [63 : 0] m_axi_rdata
.m_axi_rresp(m_axi_rresp), // input [1 : 0] m_axi_rresp
.m_axi_rlast(m_axi_rlast), // input m_axi_rlast
.m_axi_ruser(m_axi_ruser), // input [0 : 0] m_axi_ruser
.m_axi_rvalid(m_axi_rvalid), // input m_axi_rvalid
.m_axi_rready(m_axi_rready), // output m_axi_rready
.s_axis_tvalid(s_axis_tvalid), // input s_axis_tvalid
.s_axis_tready(s_axis_tready), // output s_axis_tready
.s_axis_tdata(s_axis_tdata), // input [63 : 0] s_axis_tdata
.s_axis_tstrb(s_axis_tstrb), // input [7 : 0] s_axis_tstrb
.s_axis_tkeep(s_axis_tkeep), // input [7 : 0] s_axis_tkeep
.s_axis_tlast(s_axis_tlast), // input s_axis_tlast
.s_axis_tid(s_axis_tid), // input [0 : 0] s_axis_tid
.s_axis_tdest(s_axis_tdest), // input [0 : 0] s_axis_tdest
.m_axis_tvalid(m_axis_tvalid), // output m_axis_tvalid
.m_axis_tready(m_axis_tready), // input m_axis_tready
.m_axis_tdata(m_axis_tdata), // output [63 : 0] m_axis_tdata
.m_axis_tstrb(m_axis_tstrb), // output [7 : 0] m_axis_tstrb
.m_axis_tkeep(m_axis_tkeep), // output [7 : 0] m_axis_tkeep
.m_axis_tlast(m_axis_tlast), // output m_axis_tlast
.m_axis_tid(m_axis_tid), // output [0 : 0] m_axis_tid
.m_axis_tdest(m_axis_tdest), // output [0 : 0] m_axis_tdest
.vfifo_mm2s_channel_full(vfifo_mm2s_channel_full), // input [1 : 0] vfifo_mm2s_channel_full
.vfifo_s2mm_channel_full(vfifo_s2mm_channel_full), // output [1 : 0] vfifo_s2mm_channel_full
.vfifo_mm2s_channel_empty(vfifo_mm2s_channel_empty), // output [1 : 0] vfifo_mm2s_channel_empty
.vfifo_mm2s_rresp_err_intr(vfifo_mm2s_rresp_err_intr), // output vfifo_mm2s_rresp_err_intr
.vfifo_s2mm_bresp_err_intr(vfifo_s2mm_bresp_err_intr), // output vfifo_s2mm_bresp_err_intr
.vfifo_s2mm_overrun_err_intr(vfifo_s2mm_overrun_err_intr), // output vfifo_s2mm_overrun_err_intr
.vfifo_idle(vfifo_idle) // output [1 : 0] vfifo_idle
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file axi_vfifo_64_0x0.v when simulating
// the core, axi_vfifo_64_0x0. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
top/x300/coregen/axi_vfifo_64_0x0.xco
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##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Fri Jan 18 18:05:21 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:axi_vfifo_ctrl:1.1
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc7k410t
SET devicefamily = kintex7
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg900
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT AXI_Virtual_FIFO_Controller xilinx.com:ip:axi_vfifo_ctrl:1.1
# END Select
# BEGIN Parameters
CSET ar_weight_ch0=8
CSET ar_weight_ch1=8
CSET ar_weight_ch2=8
CSET ar_weight_ch3=8
CSET ar_weight_ch4=8
CSET ar_weight_ch5=8
CSET ar_weight_ch6=8
CSET ar_weight_ch7=8
CSET axi_burst_size=512
CSET axis_tdata_width=64
CSET axis_tuser_width=1
CSET component_name=axi_vfifo_64_0x0
CSET deassert_tready=false
CSET dram_base_addr=00000000
CSET enable_axis_tid=true
CSET enable_axis_tuser=false
CSET enable_interrupt=true
CSET implementation_type=Burst_Mode
CSET number_of_channel=2
CSET number_of_page_ch0=4096
CSET number_of_page_ch1=4096
CSET number_of_page_ch2=8
CSET number_of_page_ch3=8
CSET number_of_page_ch4=8
CSET number_of_page_ch5=8
CSET number_of_page_ch6=8
CSET number_of_page_ch7=8
CSET s2mm_txn_timeout_value=8
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-19T22:37:34Z
# END Extra information
GENERATE
# CRC: 175980fe
top/x300/coregen/axi_vfifo_64_0x0.xise
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="axi_vfifo_64_0x0.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="axi_vfifo_64_0x0.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc7k410t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Kintex7" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|axi_vfifo_64_0x0" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="axi_vfifo_64_0x0.ngc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/axi_vfifo_64_0x0" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="ffg900" xil_pn:valueState="non-default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="axi_vfifo_64_0x0" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="kintex7" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-01-18T10:15:23" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="3C4425823DE80F101A5DE6759EC8B2B3" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
top/x300/coregen/axi_vfifo_64_0x0/doc/axi_vfifo_ctrl_v1_1_readme.txt
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CHANGE LOG for LogiCORE AXI Virtual FIFO Controller V1.1
Core name: Xilinx LogiCORE AXI Virtual FIFO Controller
Version: 1.1
Release: ISE 14.2 / Vivado 2012.2
Release Date: July 25, 2012
--------------------------------------------------------------------------------
Table of Contents
1. INTRODUCTION
2. DEVICE SUPPORT
3. NEW FEATURES HISTORY
4. RESOLVED ISSUES
5. KNOWN ISSUES & LIMITATIONS
6. TECHNICAL SUPPORT & FEEDBACK
7. CORE RELEASE HISTORY
8. LEGAL DISCLAIMER
--------------------------------------------------------------------------------
1. INTRODUCTION
For installation instructions for this release, please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
This file contains release notes for the Xilinx LogiCORE IP AXI Virtual FIFO Controller v1.1
solution. For the latest core updates, see the product page at:
http://www.xilinx.com/products/intellectual-property/axi_virtual_fifo_controller.htm
................................................................................
2. DEVICE SUPPORT
2.1 ISE
The following device families are supported by the core for this release.
All 7 Series devices
Zynq-7000 devices
All Virtex-6 devices
All Spartan-6 devices
2.2 Vivado
All 7 Series devices
Zynq-7000 devices
................................................................................
3. NEW FEATURES HISTORY
3.1 ISE
- First release
- ISE 14.2 software support
3.2 Vivado
- First release
- 2012.2 software support
................................................................................
4. RESOLVED ISSUES
4.1 ISE
- N/A
4.2 Vivado
- N/A
................................................................................
5. KNOWN ISSUES & LIMITATIONS
5.1 ISE
- N/A
5.2 Vivado
- N/A
The most recent information, including known issues, workarounds, and
resolutions for this version is provided in the IP Release Notes User Guide
located at
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
................................................................................
6. TECHNICAL SUPPORT & FEEDBACK
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
................................................................................
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
07/25/2012 Xilinx, Inc. 1.1 First release; ISE 14.2 and Vivado 2012.2 support.
04/24/2012 Xilinx, Inc. 1.1 First release; ISE 14.1 and Vivado 2012.1 support.
================================================================================
................................................................................
8. LEGAL DISCLAIMER
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
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<HTML>
<HEAD>
<TITLE>axi_vfifo_ctrl_v1_1_vinfo</TITLE>
<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
</HEAD>
<BODY>
<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
CHANGE LOG for LogiCORE AXI Virtual FIFO Controller V1.1
Core name: Xilinx LogiCORE AXI Virtual FIFO Controller
Version: 1.1
Release: ISE 14.2 / Vivado 2012.2
Release Date: July 25, 2012
--------------------------------------------------------------------------------
Table of Contents
1. INTRODUCTION
2. DEVICE SUPPORT
3. NEW FEATURES HISTORY
4. RESOLVED ISSUES
5. KNOWN ISSUES & LIMITATIONS
6. TECHNICAL SUPPORT & FEEDBACK
7. CORE RELEASE HISTORY
8. LEGAL DISCLAIMER
--------------------------------------------------------------------------------
1. INTRODUCTION
For installation instructions for this release, please go to:
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
For system requirements:
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
This file contains release notes for the Xilinx LogiCORE IP AXI Virtual FIFO Controller v1.1
solution. For the latest core updates, see the product page at:
<A HREF="http://www.xilinx.com/products/intellectual-property/axi_virtual_fifo_controller.htm">www.xilinx.com/products/intellectual-property/axi_virtual_fifo_controller.htm</A>
................................................................................
2. DEVICE SUPPORT
2.1 ISE
The following device families are supported by the core for this release.
All 7 Series devices
Zynq-7000 devices
All Virtex-6 devices
All Spartan-6 devices
2.2 Vivado
All 7 Series devices
Zynq-7000 devices
................................................................................
3. NEW FEATURES HISTORY
3.1 ISE
- First release
- ISE 14.2 software support
3.2 Vivado
- First release
- 2012.2 software support
................................................................................
4. RESOLVED ISSUES
4.1 ISE
- N/A
4.2 Vivado
- N/A
................................................................................
5. KNOWN ISSUES & LIMITATIONS
5.1 ISE
- N/A
5.2 Vivado
- N/A
The most recent information, including known issues, workarounds, and
resolutions for this version is provided in the IP Release Notes User Guide
located at
<A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
................................................................................
6. TECHNICAL SUPPORT & FEEDBACK
To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
................................................................................
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
07/25/2012 Xilinx, Inc. 1.1 First release; ISE 14.2 and Vivado 2012.2 support.
04/24/2012 Xilinx, Inc. 1.1 First release; ISE 14.1 and Vivado 2012.1 support.
================================================================================
................................................................................
8. LEGAL DISCLAIMER
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
</FONT>
</PRE>
</BODY>
</HTML>
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################################################################################
# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
################################################################################
# Core Period Constraint. This constraint can be modified, and is
# valid as long as it is met after place and route.
NET "ACLK" TNM_NET = "ACLK";
TIMESPEC "TS_ACLK" = PERIOD "ACLK" 50 MHZ;
################################################################################
top/x300/coregen/axi_vfifo_64_0x0/example_design/axi_vfifo_64_0x0_exdes.vhd
-370
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--------------------------------------------------------------------------------
--
-- AXI Virtual FIFO Controller Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: axi_vfifo_64_0x0_exdes.vhd
--
-- Description:
-- This is the VFIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity axi_vfifo_64_0x0_exdes is
PORT (
-- AXI Stream Input Signals From Switch to AXI Virtual FIFO Controller (AVFC)
S_AXIS_TVALID : IN STD_LOGIC := '0';
S_AXIS_TREADY : OUT STD_LOGIC := '0';
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TSTRB : IN STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TKEEP : IN STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TLAST : IN STD_LOGIC := '0';
S_AXIS_TID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TDEST : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
-- AXI Virtual FIFO Controller (AVFC) Output Signals To AXI Stream Switch
M_AXIS_TVALID : OUT STD_LOGIC := '0';
M_AXIS_TREADY : IN STD_LOGIC := '0';
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TSTRB : OUT STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS => '1');
M_AXIS_TKEEP : OUT STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TLAST : OUT STD_LOGIC := '0';
M_AXIS_TID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TDEST : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
-- Write Address Channel Signals
M_AXI_AWID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLOCK : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWQOS : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWREGION : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWVALID : OUT STD_LOGIC := '0';
M_AXI_AWREADY : IN STD_LOGIC := '0';
-- Write Data Channel Signals
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(64 / 8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WLAST : OUT STD_LOGIC := '0';
M_AXI_WUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WVALID : OUT STD_LOGIC := '0';
M_AXI_WREADY : IN STD_LOGIC := '0';
-- Write Response Channel Signals
M_AXI_BID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_BRESP : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_BUSER : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_BVALID : IN STD_LOGIC := '0';
M_AXI_BREADY : OUT STD_LOGIC := '1';
-- Read Address Channel Signals
M_AXI_ARID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLOCK : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARQOS : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARREGION : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARVALID : OUT STD_LOGIC := '0';
M_AXI_ARREADY : IN STD_LOGIC := '0';
-- Read Data Channel Signals
M_AXI_RID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RDATA : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RRESP : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RLAST : IN STD_LOGIC := '0';
M_AXI_RUSER : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RVALID : IN STD_LOGIC := '0';
M_AXI_RREADY : OUT STD_LOGIC := '0';
-- External Interface Signals
VFIFO_MM2S_CHANNEL_FULL : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
VFIFO_S2MM_CHANNEL_FULL : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
VFIFO_MM2S_CHANNEL_EMPTY : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'1');
-- Status Signal
VFIFO_IDLE : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'1');
-- Interrupt Signals
VFIFO_MM2S_RRESP_ERR_INTR : OUT STD_LOGIC := '0';
VFIFO_S2MM_BRESP_ERR_INTR : OUT STD_LOGIC := '0';
VFIFO_S2MM_OVERRUN_ERR_INTR : OUT STD_LOGIC := '0';
-- Global Signals
ACLK : IN STD_LOGIC := '0';
ARESETN : IN STD_LOGIC := '0'
);
end axi_vfifo_64_0x0_exdes;
architecture xilinx of axi_vfifo_64_0x0_exdes is
signal s_aclk_i : std_logic;
component axi_vfifo_64_0x0 is
PORT (
-- AXI Stream Input Signals From Switch to AXI Virtual FIFO Controller (AVFC)
S_AXIS_TVALID : IN STD_LOGIC := '0';
S_AXIS_TREADY : OUT STD_LOGIC := '0';
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TSTRB : IN STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TKEEP : IN STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TLAST : IN STD_LOGIC := '0';
S_AXIS_TID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TDEST : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
-- AXI Virtual FIFO Controller (AVFC) Output Signals To AXI Stream Switch
M_AXIS_TVALID : OUT STD_LOGIC := '0';
M_AXIS_TREADY : IN STD_LOGIC := '0';
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TSTRB : OUT STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS => '1');
M_AXIS_TKEEP : OUT STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TLAST : OUT STD_LOGIC := '0';
M_AXIS_TID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TDEST : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
-- Write Address Channel Signals
M_AXI_AWID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLOCK : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWQOS : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWREGION : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWVALID : OUT STD_LOGIC := '0';
M_AXI_AWREADY : IN STD_LOGIC := '0';
-- Write Data Channel Signals
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(64 / 8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WLAST : OUT STD_LOGIC := '0';
M_AXI_WUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WVALID : OUT STD_LOGIC := '0';
M_AXI_WREADY : IN STD_LOGIC := '0';
-- Write Response Channel Signals
M_AXI_BID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_BRESP : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_BUSER : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_BVALID : IN STD_LOGIC := '0';
M_AXI_BREADY : OUT STD_LOGIC := '1';
-- Read Address Channel Signals
M_AXI_ARID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLOCK : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARQOS : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARREGION : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARVALID : OUT STD_LOGIC := '0';
M_AXI_ARREADY : IN STD_LOGIC := '0';
-- Read Data Channel Signals
M_AXI_RID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RDATA : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RRESP : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RLAST : IN STD_LOGIC := '0';
M_AXI_RUSER : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RVALID : IN STD_LOGIC := '0';
M_AXI_RREADY : OUT STD_LOGIC := '0';
-- External Interface Signals
VFIFO_MM2S_CHANNEL_FULL : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
VFIFO_S2MM_CHANNEL_FULL : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
VFIFO_MM2S_CHANNEL_EMPTY : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'1');
-- Status Signal
VFIFO_IDLE : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'1');
-- Interrupt Signals
VFIFO_MM2S_RRESP_ERR_INTR : OUT STD_LOGIC := '0';
VFIFO_S2MM_BRESP_ERR_INTR : OUT STD_LOGIC := '0';
VFIFO_S2MM_OVERRUN_ERR_INTR : OUT STD_LOGIC := '0';
-- Global Signals
ACLK : IN STD_LOGIC := '0';
ARESETN : IN STD_LOGIC := '0'
);
end component;
begin
s_aclk_buf: bufg
PORT map(
i => ACLK,
o => s_aclk_i
);
exdes_inst : axi_vfifo_64_0x0
PORT MAP (
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TSTRB => S_AXIS_TSTRB,
S_AXIS_TKEEP => S_AXIS_TKEEP,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TID => S_AXIS_TID,
S_AXIS_TDEST => S_AXIS_TDEST,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TREADY => M_AXIS_TREADY,
M_AXIS_TDATA => M_AXIS_TDATA,
M_AXIS_TSTRB => M_AXIS_TSTRB,
M_AXIS_TKEEP => M_AXIS_TKEEP,
M_AXIS_TLAST => M_AXIS_TLAST,
M_AXIS_TID => M_AXIS_TID,
M_AXIS_TDEST => M_AXIS_TDEST,
M_AXI_AWID => M_AXI_AWID,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWLEN => M_AXI_AWLEN,
M_AXI_AWSIZE => M_AXI_AWSIZE,
M_AXI_AWBURST => M_AXI_AWBURST,
M_AXI_AWLOCK => M_AXI_AWLOCK,
M_AXI_AWCACHE => M_AXI_AWCACHE,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWQOS => M_AXI_AWQOS,
M_AXI_AWREGION => M_AXI_AWREGION,
M_AXI_AWUSER => M_AXI_AWUSER,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WLAST => M_AXI_WLAST,
M_AXI_WUSER => M_AXI_WUSER,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_BID => M_AXI_BID,
M_AXI_BRESP => M_AXI_BRESP,
M_AXI_BUSER => M_AXI_BUSER,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_ARID => M_AXI_ARID,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARLEN => M_AXI_ARLEN,
M_AXI_ARSIZE => M_AXI_ARSIZE,
M_AXI_ARBURST => M_AXI_ARBURST,
M_AXI_ARLOCK => M_AXI_ARLOCK,
M_AXI_ARCACHE => M_AXI_ARCACHE,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARQOS => M_AXI_ARQOS,
M_AXI_ARREGION => M_AXI_ARREGION,
M_AXI_ARUSER => M_AXI_ARUSER,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_RID => M_AXI_RID,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RLAST => M_AXI_RLAST,
M_AXI_RUSER => M_AXI_RUSER,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RREADY => M_AXI_RREADY,
-- External Interface Signals
VFIFO_MM2S_CHANNEL_FULL => VFIFO_MM2S_CHANNEL_FULL,
VFIFO_MM2S_CHANNEL_EMPTY => VFIFO_MM2S_CHANNEL_EMPTY,
VFIFO_S2MM_CHANNEL_FULL => VFIFO_S2MM_CHANNEL_FULL,
-- Status Signal
VFIFO_IDLE => VFIFO_IDLE,
-- Interrupt Signals
VFIFO_MM2S_RRESP_ERR_INTR => VFIFO_MM2S_RRESP_ERR_INTR,
VFIFO_S2MM_BRESP_ERR_INTR => VFIFO_S2MM_BRESP_ERR_INTR,
VFIFO_S2MM_OVERRUN_ERR_INTR => VFIFO_S2MM_OVERRUN_ERR_INTR,
ACLK => s_aclk_i,
ARESETN => ARESETN
);
end xilinx;
top/x300/coregen/axi_vfifo_64_0x0/example_design/axi_vfifo_64_0x0_exdes.xdc
-55
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@@ -1,55 +0,0 @@
################################################################################
# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
################################################################################
# Core Period Constraint. This constraint can be modified, and is
# valid as long as it is met after place and route.
create_clock -name "TS_ACLK" -period 20.0 [ get_ports ACLK ]
################################################################################
top/x300/coregen/axi_vfifo_64_0x0/implement/implement.bat
-88
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@@ -1,88 +0,0 @@
rem (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
rem
rem This file contains confidential and proprietary information
rem of Xilinx, Inc. and is protected under U.S. and
rem international copyright and other intellectual property
rem laws.
rem
rem DISCLAIMER
rem This disclaimer is not a license and does not grant any
rem rights to the materials distributed herewith. Except as
rem otherwise provided in a valid license issued to you by
rem Xilinx, and to the maximum extent permitted by applicable
rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
rem (2) Xilinx shall not be liable (whether in contract or tort,
rem including negligence, or under any other theory of
rem liability) for any loss or damage of any kind or nature
rem related to, arising under or in connection with these
rem materials, including for any direct, or any indirect,
rem special, incidental, or consequential loss or damage
rem (including loss of data, profits, goodwill, or any type of
rem loss or damage suffered as a result of any action brought
rem by a third party) even if such damage or loss was
rem reasonably foreseeable or Xilinx had been advised of the
rem possibility of the same.
rem
rem CRITICAL APPLICATIONS
rem Xilinx products are not designed or intended to be fail-
rem safe, or for use in any application requiring fail-safe
rem performance, such as life-support or safety devices or
rem systems, Class III medical devices, nuclear facilities,
rem applications related to the deployment of airbags, or any
rem other applications that could lead to death, personal
rem injury, or severe property or environmental damage
rem (individually and collectively, "Critical
rem Applications"). Customer assumes the sole risk and
rem liability of any use of Xilinx products in Critical
rem Applications, subject only to applicable laws and
rem regulations governing limitations on product liability.
rem
rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
rem PART OF THIS FILE AT ALL TIMES.
rem Clean up the results directory
rmdir /S /Q results
mkdir results
rem Synthesize the VHDL Wrapper Files
#Synthesize the Wrapper Files
echo 'Synthesizing example design with XST';
xst -ifn xst.scr
copy axi_vfifo_64_0x0_exdes.ngc .\results\
rem Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
copy ..\..\axi_vfifo_64_0x0.ngc results\
rem Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
copy ..\example_design\axi_vfifo_64_0x0_exdes.ucf results\
cd results
echo 'Running ngdbuild'
ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi_vfifo_64_0x0_exdes
echo 'Running map'
map axi_vfifo_64_0x0_exdes -o mapped.ncd
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed -g UnconstrainedPins:Allow
echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -sim -tm axi_vfifo_64_0x0_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
top/x300/coregen/axi_vfifo_64_0x0/implement/implement.sh
-87
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@@ -1,87 +0,0 @@
#!/bin/sh
# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
# Clean up the results directory
rm -rf results
mkdir results
#Synthesize the Wrapper Files
echo 'Synthesizing example design with XST';
xst -ifn xst.scr
cp axi_vfifo_64_0x0_exdes.ngc ./results/
# Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
cp ../../axi_vfifo_64_0x0.ngc results/
# Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
cp ../example_design/axi_vfifo_64_0x0_exdes.ucf results/
cd results
echo 'Running ngdbuild'
ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi_vfifo_64_0x0_exdes
echo 'Running map'
map axi_vfifo_64_0x0_exdes -o mapped.ncd
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed -g UnconstrainedPins:Allow
echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -sim -tm axi_vfifo_64_0x0_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
top/x300/coregen/axi_vfifo_64_0x0/implement/implement_synplify.bat
-87
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@@ -1,87 +0,0 @@
rem (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
rem
rem This file contains confidential and proprietary information
rem of Xilinx, Inc. and is protected under U.S. and
rem international copyright and other intellectual property
rem laws.
rem
rem DISCLAIMER
rem This disclaimer is not a license and does not grant any
rem rights to the materials distributed herewith. Except as
rem otherwise provided in a valid license issued to you by
rem Xilinx, and to the maximum extent permitted by applicable
rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
rem (2) Xilinx shall not be liable (whether in contract or tort,
rem including negligence, or under any other theory of
rem liability) for any loss or damage of any kind or nature
rem related to, arising under or in connection with these
rem materials, including for any direct, or any indirect,
rem special, incidental, or consequential loss or damage
rem (including loss of data, profits, goodwill, or any type of
rem loss or damage suffered as a result of any action brought
rem by a third party) even if such damage or loss was
rem reasonably foreseeable or Xilinx had been advised of the
rem possibility of the same.
rem
rem CRITICAL APPLICATIONS
rem Xilinx products are not designed or intended to be fail-
rem safe, or for use in any application requiring fail-safe
rem performance, such as life-support or safety devices or
rem systems, Class III medical devices, nuclear facilities,
rem applications related to the deployment of airbags, or any
rem other applications that could lead to death, personal
rem injury, or severe property or environmental damage
rem (individually and collectively, "Critical
rem Applications"). Customer assumes the sole risk and
rem liability of any use of Xilinx products in Critical
rem Applications, subject only to applicable laws and
rem regulations governing limitations on product liability.
rem
rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
rem PART OF THIS FILE AT ALL TIMES.
rem Clean up the results directory
rmdir /S /Q results
mkdir results
rem Synthesize the VHDL Wrapper Files
#Synthesize the Wrapper Files
echo 'Synthesizing example design with Synplify'
synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx
rem Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
copy ..\..\axi_vfifo_64_0x0.ngc results\
rem Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
copy ..\example_design\axi_vfifo_64_0x0_exdes.ucf results\
cd results
echo 'Running ngdbuild'
ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi_vfifo_64_0x0_exdes
echo 'Running map'
map axi_vfifo_64_0x0_exdes -o mapped.ncd
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed -g UnconstrainedPins:Allow
echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -sim -tm axi_vfifo_64_0x0_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
top/x300/coregen/axi_vfifo_64_0x0/implement/implement_synplify.sh
-86
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@@ -1,86 +0,0 @@
#!/bin/sh
# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
# Clean up the results directory
rm -rf results
mkdir results
#Synthesize the Wrapper Files
echo 'Synthesizing example design with Synplify'
synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx
# Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
cp ../../axi_vfifo_64_0x0.ngc results/
# Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
cp ../example_design/axi_vfifo_64_0x0_exdes.ucf results/
cd results
echo 'Running ngdbuild'
ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi_vfifo_64_0x0_exdes
echo 'Running map'
map axi_vfifo_64_0x0_exdes -o mapped.ncd
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed -g UnconstrainedPins:Allow
echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -sim -tm axi_vfifo_64_0x0_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
top/x300/coregen/axi_vfifo_64_0x0/implement/planAhead_ise.bat
-54
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@@ -1,54 +0,0 @@
rem (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
rem
rem This file contains confidential and proprietary information
rem of Xilinx, Inc. and is protected under U.S. and
rem international copyright and other intellectual property
rem laws.
rem
rem DISCLAIMER
rem This disclaimer is not a license and does not grant any
rem rights to the materials distributed herewith. Except as
rem otherwise provided in a valid license issued to you by
rem Xilinx, and to the maximum extent permitted by applicable
rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
rem (2) Xilinx shall not be liable (whether in contract or tort,
rem including negligence, or under any other theory of
rem liability) for any loss or damage of any kind or nature
rem related to, arising under or in connection with these
rem materials, including for any direct, or any indirect,
rem special, incidental, or consequential loss or damage
rem (including loss of data, profits, goodwill, or any type of
rem loss or damage suffered as a result of any action brought
rem by a third party) even if such damage or loss was
rem reasonably foreseeable or Xilinx had been advised of the
rem possibility of the same.
rem
rem CRITICAL APPLICATIONS
rem Xilinx products are not designed or intended to be fail-
rem safe, or for use in any application requiring fail-safe
rem performance, such as life-support or safety devices or
rem systems, Class III medical devices, nuclear facilities,
rem applications related to the deployment of airbags, or any
rem other applications that could lead to death, personal
rem injury, or severe property or environmental damage
rem (individually and collectively, "Critical
rem Applications"). Customer assumes the sole risk and
rem liability of any use of Xilinx products in Critical
rem Applications, subject only to applicable laws and
rem regulations governing limitations on product liability.
rem
rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
rem PART OF THIS FILE AT ALL TIMES.
rem -----------------------------------------------------------------------------
rem Script to synthesize and implement the Coregen FIFO Generator
rem -----------------------------------------------------------------------------
rmdir /S /Q results
mkdir results
cd results
copy ..\..\..\axi_vfifo_64_0x0.ngc .
planAhead -mode batch -source ..\planAhead_ise.tcl
top/x300/coregen/axi_vfifo_64_0x0/implement/planAhead_ise.sh
-55
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@@ -1,55 +0,0 @@
#!/bin/sh
# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#-----------------------------------------------------------------------------
# Script to synthesize and implement the Coregen FIFO Generator
#-----------------------------------------------------------------------------
rm -rf results
mkdir results
cd results
cp ../../../axi_vfifo_64_0x0.ngc .
planAhead -mode batch -source ../planAhead_ise.tcl
top/x300/coregen/axi_vfifo_64_0x0/implement/planAhead_ise.tcl
-67
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@@ -1,67 +0,0 @@
# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
set device xc7k410tffg900-2
set projName axi_vfifo_64_0x0
set design axi_vfifo_64_0x0
set projDir [file dirname [info script]]
create_project $projName $projDir/results/$projName -part $device -force
set_property design_mode RTL [current_fileset -srcset]
set top_module axi_vfifo_64_0x0_exdes
add_files -norecurse {../../example_design/axi_vfifo_64_0x0_exdes.vhd}
add_files -norecurse {./axi_vfifo_64_0x0.ngc}
import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/axi_vfifo_64_0x0_exdes.xdc}
set_property top axi_vfifo_64_0x0_exdes [get_property srcset [current_run]]
synth_design
opt_design
place_design
route_design
write_sdf -rename_top_module axi_vfifo_64_0x0_exdes -file routed.sdf
write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module axi_vfifo_64_0x0_exdes routed.v
report_timing -nworst 30 -path_type full -file routed.twr
report_drc -file report.drc
write_bitstream -bitgen_options {-g UnconstrainedPins:Allow}
top/x300/coregen/axi_vfifo_64_0x0/implement/xst.prj
-1
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@@ -1 +0,0 @@
work ../example_design/axi_vfifo_64_0x0_exdes.vhd
top/x300/coregen/axi_vfifo_64_0x0/implement/xst.scr
-13
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@@ -1,13 +0,0 @@
run
-ifmt VHDL
-ent axi_vfifo_64_0x0_exdes
-p xc7k410t-ffg900-2
-ifn xst.prj
-write_timing_constraints No
-iobuf YES
-max_fanout 100
-ofn axi_vfifo_64_0x0_exdes
-ofmt NGC
-bus_delimiter ()
-hierarchy_separator /
-case Maintain
top/x300/coregen/axi_vfifo_64_0x0_flist.txt
-25
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@@ -1,25 +0,0 @@
# Output products list for <axi_vfifo_64_0x0>
axi_vfifo_64_0x0/doc/axi_vfifo_ctrl_v1_1_readme.txt
axi_vfifo_64_0x0/doc/axi_vfifo_ctrl_v1_1_vinfo.html
axi_vfifo_64_0x0/doc/pg038_axi_vfifo_ctrl.pdf
axi_vfifo_64_0x0/example_design/axi_vfifo_64_0x0_exdes.ucf
axi_vfifo_64_0x0/example_design/axi_vfifo_64_0x0_exdes.vhd
axi_vfifo_64_0x0/example_design/axi_vfifo_64_0x0_exdes.xdc
axi_vfifo_64_0x0/implement/implement.bat
axi_vfifo_64_0x0/implement/implement.sh
axi_vfifo_64_0x0/implement/implement_synplify.bat
axi_vfifo_64_0x0/implement/implement_synplify.sh
axi_vfifo_64_0x0/implement/planAhead_ise.bat
axi_vfifo_64_0x0/implement/planAhead_ise.sh
axi_vfifo_64_0x0/implement/planAhead_ise.tcl
axi_vfifo_64_0x0/implement/xst.prj
axi_vfifo_64_0x0/implement/xst.scr
axi_vfifo_64_0x0.gise
axi_vfifo_64_0x0.ngc
axi_vfifo_64_0x0.v
axi_vfifo_64_0x0.veo
axi_vfifo_64_0x0.xco
axi_vfifo_64_0x0.xise
axi_vfifo_64_0x0_flist.txt
axi_vfifo_64_0x0_xmdf.tcl
axi_vfifo_ctrl_v1_1_readme.txt
top/x300/coregen/axi_vfifo_64_0x0_xmdf.tcl
-127
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@@ -1,127 +0,0 @@
# The package naming convention is <core_name>_xmdf
package provide axi_vfifo_64_0x0_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::axi_vfifo_64_0x0_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::axi_vfifo_64_0x0_xmdf::xmdfInit { instance } {
# Variable containing name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name axi_vfifo_64_0x0
}
# ::axi_vfifo_64_0x0_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::axi_vfifo_64_0x0_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0/doc/axi_vfifo_ctrl_v1_1_readme.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0/doc/axi_vfifo_ctrl_v1_1_vinfo.html
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0/doc/pg038_axi_vfifo_ctrl.pdf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0/example_design/axi_vfifo_64_0x0_exdes.ucf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0/example_design/axi_vfifo_64_0x0_exdes.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0/example_design/axi_vfifo_64_0x0_exdes.xdc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0/implement/implement.bat
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0/implement/implement.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0/implement/implement_synplify.bat
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0/implement/implement_synplify.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0/implement/planAhead_ise.bat
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0/implement/planAhead_ise.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0/implement/planAhead_ise.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0/implement/xst.prj
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0/implement/xst.scr
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0.veo
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x0_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_ctrl_v1_1_readme.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module axi_vfifo_64_0x0
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
top/x300/coregen/axi_vfifo_64_0x2000000.gise
-31
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@@ -1,31 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="axi_vfifo_64_0x2000000.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_VEO" xil_pn:name="axi_vfifo_64_0x2000000.veo" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="axi_vfifo_ctrl_v1_1_readme.txt" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
top/x300/coregen/axi_vfifo_64_0x2000000.ncf
View File
Whitespace-only changes.
top/x300/coregen/axi_vfifo_64_0x2000000.ngc
-3
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@@ -1,3 +0,0 @@
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
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top/x300/coregen/axi_vfifo_64_0x2000000.v
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top/x300/coregen/axi_vfifo_64_0x2000000.veo
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/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2013 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
/*******************************************************************************
* Generated from core with identifier: xilinx.com:ip:axi_vfifo_ctrl:1.1 *
* *
* Rev 1. The AXI Virtual FIFO Controller is a parameterizable number of *
* multi channel FIFO. *
*******************************************************************************/
// Interfaces:
// AXI4Stream_MASTER_M_AXIS
// AXI4Stream_SLAVE_S_AXIS
// AXI4_MASTER_M_AXI
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
axi_vfifo_64_0x2000000 your_instance_name (
.aclk(aclk), // input aclk
.aresetn(aresetn), // input aresetn
.m_axi_awid(m_axi_awid), // output [0 : 0] m_axi_awid
.m_axi_awaddr(m_axi_awaddr), // output [31 : 0] m_axi_awaddr
.m_axi_awlen(m_axi_awlen), // output [7 : 0] m_axi_awlen
.m_axi_awsize(m_axi_awsize), // output [2 : 0] m_axi_awsize
.m_axi_awburst(m_axi_awburst), // output [1 : 0] m_axi_awburst
.m_axi_awlock(m_axi_awlock), // output [0 : 0] m_axi_awlock
.m_axi_awcache(m_axi_awcache), // output [3 : 0] m_axi_awcache
.m_axi_awprot(m_axi_awprot), // output [2 : 0] m_axi_awprot
.m_axi_awqos(m_axi_awqos), // output [3 : 0] m_axi_awqos
.m_axi_awregion(m_axi_awregion), // output [3 : 0] m_axi_awregion
.m_axi_awuser(m_axi_awuser), // output [0 : 0] m_axi_awuser
.m_axi_awvalid(m_axi_awvalid), // output m_axi_awvalid
.m_axi_awready(m_axi_awready), // input m_axi_awready
.m_axi_wdata(m_axi_wdata), // output [63 : 0] m_axi_wdata
.m_axi_wstrb(m_axi_wstrb), // output [7 : 0] m_axi_wstrb
.m_axi_wlast(m_axi_wlast), // output m_axi_wlast
.m_axi_wuser(m_axi_wuser), // output [0 : 0] m_axi_wuser
.m_axi_wvalid(m_axi_wvalid), // output m_axi_wvalid
.m_axi_wready(m_axi_wready), // input m_axi_wready
.m_axi_bid(m_axi_bid), // input [0 : 0] m_axi_bid
.m_axi_bresp(m_axi_bresp), // input [1 : 0] m_axi_bresp
.m_axi_buser(m_axi_buser), // input [0 : 0] m_axi_buser
.m_axi_bvalid(m_axi_bvalid), // input m_axi_bvalid
.m_axi_bready(m_axi_bready), // output m_axi_bready
.m_axi_arid(m_axi_arid), // output [0 : 0] m_axi_arid
.m_axi_araddr(m_axi_araddr), // output [31 : 0] m_axi_araddr
.m_axi_arlen(m_axi_arlen), // output [7 : 0] m_axi_arlen
.m_axi_arsize(m_axi_arsize), // output [2 : 0] m_axi_arsize
.m_axi_arburst(m_axi_arburst), // output [1 : 0] m_axi_arburst
.m_axi_arlock(m_axi_arlock), // output [0 : 0] m_axi_arlock
.m_axi_arcache(m_axi_arcache), // output [3 : 0] m_axi_arcache
.m_axi_arprot(m_axi_arprot), // output [2 : 0] m_axi_arprot
.m_axi_arqos(m_axi_arqos), // output [3 : 0] m_axi_arqos
.m_axi_arregion(m_axi_arregion), // output [3 : 0] m_axi_arregion
.m_axi_aruser(m_axi_aruser), // output [0 : 0] m_axi_aruser
.m_axi_arvalid(m_axi_arvalid), // output m_axi_arvalid
.m_axi_arready(m_axi_arready), // input m_axi_arready
.m_axi_rid(m_axi_rid), // input [0 : 0] m_axi_rid
.m_axi_rdata(m_axi_rdata), // input [63 : 0] m_axi_rdata
.m_axi_rresp(m_axi_rresp), // input [1 : 0] m_axi_rresp
.m_axi_rlast(m_axi_rlast), // input m_axi_rlast
.m_axi_ruser(m_axi_ruser), // input [0 : 0] m_axi_ruser
.m_axi_rvalid(m_axi_rvalid), // input m_axi_rvalid
.m_axi_rready(m_axi_rready), // output m_axi_rready
.s_axis_tvalid(s_axis_tvalid), // input s_axis_tvalid
.s_axis_tready(s_axis_tready), // output s_axis_tready
.s_axis_tdata(s_axis_tdata), // input [63 : 0] s_axis_tdata
.s_axis_tstrb(s_axis_tstrb), // input [7 : 0] s_axis_tstrb
.s_axis_tkeep(s_axis_tkeep), // input [7 : 0] s_axis_tkeep
.s_axis_tlast(s_axis_tlast), // input s_axis_tlast
.s_axis_tid(s_axis_tid), // input [0 : 0] s_axis_tid
.s_axis_tdest(s_axis_tdest), // input [0 : 0] s_axis_tdest
.m_axis_tvalid(m_axis_tvalid), // output m_axis_tvalid
.m_axis_tready(m_axis_tready), // input m_axis_tready
.m_axis_tdata(m_axis_tdata), // output [63 : 0] m_axis_tdata
.m_axis_tstrb(m_axis_tstrb), // output [7 : 0] m_axis_tstrb
.m_axis_tkeep(m_axis_tkeep), // output [7 : 0] m_axis_tkeep
.m_axis_tlast(m_axis_tlast), // output m_axis_tlast
.m_axis_tid(m_axis_tid), // output [0 : 0] m_axis_tid
.m_axis_tdest(m_axis_tdest), // output [0 : 0] m_axis_tdest
.vfifo_mm2s_channel_full(vfifo_mm2s_channel_full), // input [1 : 0] vfifo_mm2s_channel_full
.vfifo_s2mm_channel_full(vfifo_s2mm_channel_full), // output [1 : 0] vfifo_s2mm_channel_full
.vfifo_mm2s_channel_empty(vfifo_mm2s_channel_empty), // output [1 : 0] vfifo_mm2s_channel_empty
.vfifo_mm2s_rresp_err_intr(vfifo_mm2s_rresp_err_intr), // output vfifo_mm2s_rresp_err_intr
.vfifo_s2mm_bresp_err_intr(vfifo_s2mm_bresp_err_intr), // output vfifo_s2mm_bresp_err_intr
.vfifo_s2mm_overrun_err_intr(vfifo_s2mm_overrun_err_intr), // output vfifo_s2mm_overrun_err_intr
.vfifo_idle(vfifo_idle) // output [1 : 0] vfifo_idle
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file axi_vfifo_64_0x2000000.v when simulating
// the core, axi_vfifo_64_0x2000000. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
top/x300/coregen/axi_vfifo_64_0x2000000.xco
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##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Fri Jan 18 18:20:30 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:axi_vfifo_ctrl:1.1
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc7k410t
SET devicefamily = kintex7
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg900
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT AXI_Virtual_FIFO_Controller xilinx.com:ip:axi_vfifo_ctrl:1.1
# END Select
# BEGIN Parameters
CSET ar_weight_ch0=8
CSET ar_weight_ch1=8
CSET ar_weight_ch2=8
CSET ar_weight_ch3=8
CSET ar_weight_ch4=8
CSET ar_weight_ch5=8
CSET ar_weight_ch6=8
CSET ar_weight_ch7=8
CSET axi_burst_size=512
CSET axis_tdata_width=64
CSET axis_tuser_width=1
CSET component_name=axi_vfifo_64_0x2000000
CSET deassert_tready=false
CSET dram_base_addr=02000000
CSET enable_axis_tid=true
CSET enable_axis_tuser=false
CSET enable_interrupt=true
CSET implementation_type=Burst_Mode
CSET number_of_channel=2
CSET number_of_page_ch0=4096
CSET number_of_page_ch1=4096
CSET number_of_page_ch2=8
CSET number_of_page_ch3=8
CSET number_of_page_ch4=8
CSET number_of_page_ch5=8
CSET number_of_page_ch6=8
CSET number_of_page_ch7=8
CSET s2mm_txn_timeout_value=8
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-19T22:37:34Z
# END Extra information
GENERATE
# CRC: cae4af68
top/x300/coregen/axi_vfifo_64_0x2000000.xise
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="axi_vfifo_64_0x2000000.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="axi_vfifo_64_0x2000000.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc7k410t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Kintex7" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|axi_vfifo_64_0x2000000" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="axi_vfifo_64_0x2000000.ngc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/axi_vfifo_64_0x2000000" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="ffg900" xil_pn:valueState="non-default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="axi_vfifo_64_0x2000000" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="kintex7" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-01-18T10:30:19" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="A346775F24C07C594060EA114E9E4BA0" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
top/x300/coregen/axi_vfifo_64_0x2000000/doc/axi_vfifo_ctrl_v1_1_readme.txt
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CHANGE LOG for LogiCORE AXI Virtual FIFO Controller V1.1
Core name: Xilinx LogiCORE AXI Virtual FIFO Controller
Version: 1.1
Release: ISE 14.2 / Vivado 2012.2
Release Date: July 25, 2012
--------------------------------------------------------------------------------
Table of Contents
1. INTRODUCTION
2. DEVICE SUPPORT
3. NEW FEATURES HISTORY
4. RESOLVED ISSUES
5. KNOWN ISSUES & LIMITATIONS
6. TECHNICAL SUPPORT & FEEDBACK
7. CORE RELEASE HISTORY
8. LEGAL DISCLAIMER
--------------------------------------------------------------------------------
1. INTRODUCTION
For installation instructions for this release, please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
This file contains release notes for the Xilinx LogiCORE IP AXI Virtual FIFO Controller v1.1
solution. For the latest core updates, see the product page at:
http://www.xilinx.com/products/intellectual-property/axi_virtual_fifo_controller.htm
................................................................................
2. DEVICE SUPPORT
2.1 ISE
The following device families are supported by the core for this release.
All 7 Series devices
Zynq-7000 devices
All Virtex-6 devices
All Spartan-6 devices
2.2 Vivado
All 7 Series devices
Zynq-7000 devices
................................................................................
3. NEW FEATURES HISTORY
3.1 ISE
- First release
- ISE 14.2 software support
3.2 Vivado
- First release
- 2012.2 software support
................................................................................
4. RESOLVED ISSUES
4.1 ISE
- N/A
4.2 Vivado
- N/A
................................................................................
5. KNOWN ISSUES & LIMITATIONS
5.1 ISE
- N/A
5.2 Vivado
- N/A
The most recent information, including known issues, workarounds, and
resolutions for this version is provided in the IP Release Notes User Guide
located at
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
................................................................................
6. TECHNICAL SUPPORT & FEEDBACK
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
................................................................................
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
07/25/2012 Xilinx, Inc. 1.1 First release; ISE 14.2 and Vivado 2012.2 support.
04/24/2012 Xilinx, Inc. 1.1 First release; ISE 14.1 and Vivado 2012.1 support.
================================================================================
................................................................................
8. LEGAL DISCLAIMER
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
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<HTML>
<HEAD>
<TITLE>axi_vfifo_ctrl_v1_1_vinfo</TITLE>
<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
</HEAD>
<BODY>
<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
CHANGE LOG for LogiCORE AXI Virtual FIFO Controller V1.1
Core name: Xilinx LogiCORE AXI Virtual FIFO Controller
Version: 1.1
Release: ISE 14.2 / Vivado 2012.2
Release Date: July 25, 2012
--------------------------------------------------------------------------------
Table of Contents
1. INTRODUCTION
2. DEVICE SUPPORT
3. NEW FEATURES HISTORY
4. RESOLVED ISSUES
5. KNOWN ISSUES & LIMITATIONS
6. TECHNICAL SUPPORT & FEEDBACK
7. CORE RELEASE HISTORY
8. LEGAL DISCLAIMER
--------------------------------------------------------------------------------
1. INTRODUCTION
For installation instructions for this release, please go to:
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
For system requirements:
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
This file contains release notes for the Xilinx LogiCORE IP AXI Virtual FIFO Controller v1.1
solution. For the latest core updates, see the product page at:
<A HREF="http://www.xilinx.com/products/intellectual-property/axi_virtual_fifo_controller.htm">www.xilinx.com/products/intellectual-property/axi_virtual_fifo_controller.htm</A>
................................................................................
2. DEVICE SUPPORT
2.1 ISE
The following device families are supported by the core for this release.
All 7 Series devices
Zynq-7000 devices
All Virtex-6 devices
All Spartan-6 devices
2.2 Vivado
All 7 Series devices
Zynq-7000 devices
................................................................................
3. NEW FEATURES HISTORY
3.1 ISE
- First release
- ISE 14.2 software support
3.2 Vivado
- First release
- 2012.2 software support
................................................................................
4. RESOLVED ISSUES
4.1 ISE
- N/A
4.2 Vivado
- N/A
................................................................................
5. KNOWN ISSUES & LIMITATIONS
5.1 ISE
- N/A
5.2 Vivado
- N/A
The most recent information, including known issues, workarounds, and
resolutions for this version is provided in the IP Release Notes User Guide
located at
<A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
................................................................................
6. TECHNICAL SUPPORT & FEEDBACK
To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
................................................................................
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
07/25/2012 Xilinx, Inc. 1.1 First release; ISE 14.2 and Vivado 2012.2 support.
04/24/2012 Xilinx, Inc. 1.1 First release; ISE 14.1 and Vivado 2012.1 support.
================================================================================
................................................................................
8. LEGAL DISCLAIMER
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
</FONT>
</PRE>
</BODY>
</HTML>
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################################################################################
# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
################################################################################
# Core Period Constraint. This constraint can be modified, and is
# valid as long as it is met after place and route.
NET "ACLK" TNM_NET = "ACLK";
TIMESPEC "TS_ACLK" = PERIOD "ACLK" 50 MHZ;
################################################################################
top/x300/coregen/axi_vfifo_64_0x2000000/example_design/axi_vfifo_64_0x2000000_exdes.vhd
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--------------------------------------------------------------------------------
--
-- AXI Virtual FIFO Controller Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: axi_vfifo_64_0x2000000_exdes.vhd
--
-- Description:
-- This is the VFIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity axi_vfifo_64_0x2000000_exdes is
PORT (
-- AXI Stream Input Signals From Switch to AXI Virtual FIFO Controller (AVFC)
S_AXIS_TVALID : IN STD_LOGIC := '0';
S_AXIS_TREADY : OUT STD_LOGIC := '0';
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TSTRB : IN STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TKEEP : IN STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TLAST : IN STD_LOGIC := '0';
S_AXIS_TID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TDEST : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
-- AXI Virtual FIFO Controller (AVFC) Output Signals To AXI Stream Switch
M_AXIS_TVALID : OUT STD_LOGIC := '0';
M_AXIS_TREADY : IN STD_LOGIC := '0';
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TSTRB : OUT STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS => '1');
M_AXIS_TKEEP : OUT STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TLAST : OUT STD_LOGIC := '0';
M_AXIS_TID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TDEST : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
-- Write Address Channel Signals
M_AXI_AWID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLOCK : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWQOS : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWREGION : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWVALID : OUT STD_LOGIC := '0';
M_AXI_AWREADY : IN STD_LOGIC := '0';
-- Write Data Channel Signals
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(64 / 8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WLAST : OUT STD_LOGIC := '0';
M_AXI_WUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WVALID : OUT STD_LOGIC := '0';
M_AXI_WREADY : IN STD_LOGIC := '0';
-- Write Response Channel Signals
M_AXI_BID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_BRESP : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_BUSER : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_BVALID : IN STD_LOGIC := '0';
M_AXI_BREADY : OUT STD_LOGIC := '1';
-- Read Address Channel Signals
M_AXI_ARID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLOCK : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARQOS : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARREGION : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARVALID : OUT STD_LOGIC := '0';
M_AXI_ARREADY : IN STD_LOGIC := '0';
-- Read Data Channel Signals
M_AXI_RID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RDATA : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RRESP : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RLAST : IN STD_LOGIC := '0';
M_AXI_RUSER : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RVALID : IN STD_LOGIC := '0';
M_AXI_RREADY : OUT STD_LOGIC := '0';
-- External Interface Signals
VFIFO_MM2S_CHANNEL_FULL : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
VFIFO_S2MM_CHANNEL_FULL : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
VFIFO_MM2S_CHANNEL_EMPTY : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'1');
-- Status Signal
VFIFO_IDLE : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'1');
-- Interrupt Signals
VFIFO_MM2S_RRESP_ERR_INTR : OUT STD_LOGIC := '0';
VFIFO_S2MM_BRESP_ERR_INTR : OUT STD_LOGIC := '0';
VFIFO_S2MM_OVERRUN_ERR_INTR : OUT STD_LOGIC := '0';
-- Global Signals
ACLK : IN STD_LOGIC := '0';
ARESETN : IN STD_LOGIC := '0'
);
end axi_vfifo_64_0x2000000_exdes;
architecture xilinx of axi_vfifo_64_0x2000000_exdes is
signal s_aclk_i : std_logic;
component axi_vfifo_64_0x2000000 is
PORT (
-- AXI Stream Input Signals From Switch to AXI Virtual FIFO Controller (AVFC)
S_AXIS_TVALID : IN STD_LOGIC := '0';
S_AXIS_TREADY : OUT STD_LOGIC := '0';
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TSTRB : IN STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TKEEP : IN STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TLAST : IN STD_LOGIC := '0';
S_AXIS_TID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
S_AXIS_TDEST : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
-- AXI Virtual FIFO Controller (AVFC) Output Signals To AXI Stream Switch
M_AXIS_TVALID : OUT STD_LOGIC := '0';
M_AXIS_TREADY : IN STD_LOGIC := '0';
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TSTRB : OUT STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS => '1');
M_AXIS_TKEEP : OUT STD_LOGIC_VECTOR(64/8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TLAST : OUT STD_LOGIC := '0';
M_AXIS_TID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TDEST : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
-- Write Address Channel Signals
M_AXI_AWID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLOCK : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWQOS : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWREGION : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWVALID : OUT STD_LOGIC := '0';
M_AXI_AWREADY : IN STD_LOGIC := '0';
-- Write Data Channel Signals
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(64 / 8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WLAST : OUT STD_LOGIC := '0';
M_AXI_WUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WVALID : OUT STD_LOGIC := '0';
M_AXI_WREADY : IN STD_LOGIC := '0';
-- Write Response Channel Signals
M_AXI_BID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_BRESP : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_BUSER : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_BVALID : IN STD_LOGIC := '0';
M_AXI_BREADY : OUT STD_LOGIC := '1';
-- Read Address Channel Signals
M_AXI_ARID : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLOCK : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARQOS : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARREGION : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARUSER : OUT STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARVALID : OUT STD_LOGIC := '0';
M_AXI_ARREADY : IN STD_LOGIC := '0';
-- Read Data Channel Signals
M_AXI_RID : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RDATA : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RRESP : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RLAST : IN STD_LOGIC := '0';
M_AXI_RUSER : IN STD_LOGIC_VECTOR(1 - 1 DOWNTO 0) := (OTHERS =>'0');
M_AXI_RVALID : IN STD_LOGIC := '0';
M_AXI_RREADY : OUT STD_LOGIC := '0';
-- External Interface Signals
VFIFO_MM2S_CHANNEL_FULL : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
VFIFO_S2MM_CHANNEL_FULL : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'0');
VFIFO_MM2S_CHANNEL_EMPTY : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'1');
-- Status Signal
VFIFO_IDLE : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS =>'1');
-- Interrupt Signals
VFIFO_MM2S_RRESP_ERR_INTR : OUT STD_LOGIC := '0';
VFIFO_S2MM_BRESP_ERR_INTR : OUT STD_LOGIC := '0';
VFIFO_S2MM_OVERRUN_ERR_INTR : OUT STD_LOGIC := '0';
-- Global Signals
ACLK : IN STD_LOGIC := '0';
ARESETN : IN STD_LOGIC := '0'
);
end component;
begin
s_aclk_buf: bufg
PORT map(
i => ACLK,
o => s_aclk_i
);
exdes_inst : axi_vfifo_64_0x2000000
PORT MAP (
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TSTRB => S_AXIS_TSTRB,
S_AXIS_TKEEP => S_AXIS_TKEEP,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TID => S_AXIS_TID,
S_AXIS_TDEST => S_AXIS_TDEST,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TREADY => M_AXIS_TREADY,
M_AXIS_TDATA => M_AXIS_TDATA,
M_AXIS_TSTRB => M_AXIS_TSTRB,
M_AXIS_TKEEP => M_AXIS_TKEEP,
M_AXIS_TLAST => M_AXIS_TLAST,
M_AXIS_TID => M_AXIS_TID,
M_AXIS_TDEST => M_AXIS_TDEST,
M_AXI_AWID => M_AXI_AWID,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWLEN => M_AXI_AWLEN,
M_AXI_AWSIZE => M_AXI_AWSIZE,
M_AXI_AWBURST => M_AXI_AWBURST,
M_AXI_AWLOCK => M_AXI_AWLOCK,
M_AXI_AWCACHE => M_AXI_AWCACHE,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWQOS => M_AXI_AWQOS,
M_AXI_AWREGION => M_AXI_AWREGION,
M_AXI_AWUSER => M_AXI_AWUSER,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WLAST => M_AXI_WLAST,
M_AXI_WUSER => M_AXI_WUSER,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_BID => M_AXI_BID,
M_AXI_BRESP => M_AXI_BRESP,
M_AXI_BUSER => M_AXI_BUSER,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_ARID => M_AXI_ARID,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARLEN => M_AXI_ARLEN,
M_AXI_ARSIZE => M_AXI_ARSIZE,
M_AXI_ARBURST => M_AXI_ARBURST,
M_AXI_ARLOCK => M_AXI_ARLOCK,
M_AXI_ARCACHE => M_AXI_ARCACHE,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARQOS => M_AXI_ARQOS,
M_AXI_ARREGION => M_AXI_ARREGION,
M_AXI_ARUSER => M_AXI_ARUSER,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_RID => M_AXI_RID,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RLAST => M_AXI_RLAST,
M_AXI_RUSER => M_AXI_RUSER,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RREADY => M_AXI_RREADY,
-- External Interface Signals
VFIFO_MM2S_CHANNEL_FULL => VFIFO_MM2S_CHANNEL_FULL,
VFIFO_MM2S_CHANNEL_EMPTY => VFIFO_MM2S_CHANNEL_EMPTY,
VFIFO_S2MM_CHANNEL_FULL => VFIFO_S2MM_CHANNEL_FULL,
-- Status Signal
VFIFO_IDLE => VFIFO_IDLE,
-- Interrupt Signals
VFIFO_MM2S_RRESP_ERR_INTR => VFIFO_MM2S_RRESP_ERR_INTR,
VFIFO_S2MM_BRESP_ERR_INTR => VFIFO_S2MM_BRESP_ERR_INTR,
VFIFO_S2MM_OVERRUN_ERR_INTR => VFIFO_S2MM_OVERRUN_ERR_INTR,
ACLK => s_aclk_i,
ARESETN => ARESETN
);
end xilinx;
top/x300/coregen/axi_vfifo_64_0x2000000/example_design/axi_vfifo_64_0x2000000_exdes.xdc
-55
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@@ -1,55 +0,0 @@
################################################################################
# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
################################################################################
# Core Period Constraint. This constraint can be modified, and is
# valid as long as it is met after place and route.
create_clock -name "TS_ACLK" -period 20.0 [ get_ports ACLK ]
################################################################################
top/x300/coregen/axi_vfifo_64_0x2000000/implement/implement.bat
-88
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@@ -1,88 +0,0 @@
rem (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
rem
rem This file contains confidential and proprietary information
rem of Xilinx, Inc. and is protected under U.S. and
rem international copyright and other intellectual property
rem laws.
rem
rem DISCLAIMER
rem This disclaimer is not a license and does not grant any
rem rights to the materials distributed herewith. Except as
rem otherwise provided in a valid license issued to you by
rem Xilinx, and to the maximum extent permitted by applicable
rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
rem (2) Xilinx shall not be liable (whether in contract or tort,
rem including negligence, or under any other theory of
rem liability) for any loss or damage of any kind or nature
rem related to, arising under or in connection with these
rem materials, including for any direct, or any indirect,
rem special, incidental, or consequential loss or damage
rem (including loss of data, profits, goodwill, or any type of
rem loss or damage suffered as a result of any action brought
rem by a third party) even if such damage or loss was
rem reasonably foreseeable or Xilinx had been advised of the
rem possibility of the same.
rem
rem CRITICAL APPLICATIONS
rem Xilinx products are not designed or intended to be fail-
rem safe, or for use in any application requiring fail-safe
rem performance, such as life-support or safety devices or
rem systems, Class III medical devices, nuclear facilities,
rem applications related to the deployment of airbags, or any
rem other applications that could lead to death, personal
rem injury, or severe property or environmental damage
rem (individually and collectively, "Critical
rem Applications"). Customer assumes the sole risk and
rem liability of any use of Xilinx products in Critical
rem Applications, subject only to applicable laws and
rem regulations governing limitations on product liability.
rem
rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
rem PART OF THIS FILE AT ALL TIMES.
rem Clean up the results directory
rmdir /S /Q results
mkdir results
rem Synthesize the VHDL Wrapper Files
#Synthesize the Wrapper Files
echo 'Synthesizing example design with XST';
xst -ifn xst.scr
copy axi_vfifo_64_0x2000000_exdes.ngc .\results\
rem Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
copy ..\..\axi_vfifo_64_0x2000000.ngc results\
rem Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
copy ..\example_design\axi_vfifo_64_0x2000000_exdes.ucf results\
cd results
echo 'Running ngdbuild'
ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi_vfifo_64_0x2000000_exdes
echo 'Running map'
map axi_vfifo_64_0x2000000_exdes -o mapped.ncd
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed -g UnconstrainedPins:Allow
echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -sim -tm axi_vfifo_64_0x2000000_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
top/x300/coregen/axi_vfifo_64_0x2000000/implement/implement.sh
-87
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@@ -1,87 +0,0 @@
#!/bin/sh
# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
# Clean up the results directory
rm -rf results
mkdir results
#Synthesize the Wrapper Files
echo 'Synthesizing example design with XST';
xst -ifn xst.scr
cp axi_vfifo_64_0x2000000_exdes.ngc ./results/
# Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
cp ../../axi_vfifo_64_0x2000000.ngc results/
# Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
cp ../example_design/axi_vfifo_64_0x2000000_exdes.ucf results/
cd results
echo 'Running ngdbuild'
ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi_vfifo_64_0x2000000_exdes
echo 'Running map'
map axi_vfifo_64_0x2000000_exdes -o mapped.ncd
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed -g UnconstrainedPins:Allow
echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -sim -tm axi_vfifo_64_0x2000000_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
top/x300/coregen/axi_vfifo_64_0x2000000/implement/implement_synplify.bat
-87
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@@ -1,87 +0,0 @@
rem (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
rem
rem This file contains confidential and proprietary information
rem of Xilinx, Inc. and is protected under U.S. and
rem international copyright and other intellectual property
rem laws.
rem
rem DISCLAIMER
rem This disclaimer is not a license and does not grant any
rem rights to the materials distributed herewith. Except as
rem otherwise provided in a valid license issued to you by
rem Xilinx, and to the maximum extent permitted by applicable
rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
rem (2) Xilinx shall not be liable (whether in contract or tort,
rem including negligence, or under any other theory of
rem liability) for any loss or damage of any kind or nature
rem related to, arising under or in connection with these
rem materials, including for any direct, or any indirect,
rem special, incidental, or consequential loss or damage
rem (including loss of data, profits, goodwill, or any type of
rem loss or damage suffered as a result of any action brought
rem by a third party) even if such damage or loss was
rem reasonably foreseeable or Xilinx had been advised of the
rem possibility of the same.
rem
rem CRITICAL APPLICATIONS
rem Xilinx products are not designed or intended to be fail-
rem safe, or for use in any application requiring fail-safe
rem performance, such as life-support or safety devices or
rem systems, Class III medical devices, nuclear facilities,
rem applications related to the deployment of airbags, or any
rem other applications that could lead to death, personal
rem injury, or severe property or environmental damage
rem (individually and collectively, "Critical
rem Applications"). Customer assumes the sole risk and
rem liability of any use of Xilinx products in Critical
rem Applications, subject only to applicable laws and
rem regulations governing limitations on product liability.
rem
rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
rem PART OF THIS FILE AT ALL TIMES.
rem Clean up the results directory
rmdir /S /Q results
mkdir results
rem Synthesize the VHDL Wrapper Files
#Synthesize the Wrapper Files
echo 'Synthesizing example design with Synplify'
synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx
rem Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
copy ..\..\axi_vfifo_64_0x2000000.ngc results\
rem Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
copy ..\example_design\axi_vfifo_64_0x2000000_exdes.ucf results\
cd results
echo 'Running ngdbuild'
ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi_vfifo_64_0x2000000_exdes
echo 'Running map'
map axi_vfifo_64_0x2000000_exdes -o mapped.ncd
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed -g UnconstrainedPins:Allow
echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -sim -tm axi_vfifo_64_0x2000000_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
top/x300/coregen/axi_vfifo_64_0x2000000/implement/implement_synplify.sh
-86
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@@ -1,86 +0,0 @@
#!/bin/sh
# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
# Clean up the results directory
rm -rf results
mkdir results
#Synthesize the Wrapper Files
echo 'Synthesizing example design with Synplify'
synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx
# Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
cp ../../axi_vfifo_64_0x2000000.ngc results/
# Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
cp ../example_design/axi_vfifo_64_0x2000000_exdes.ucf results/
cd results
echo 'Running ngdbuild'
ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi_vfifo_64_0x2000000_exdes
echo 'Running map'
map axi_vfifo_64_0x2000000_exdes -o mapped.ncd
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed -g UnconstrainedPins:Allow
echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -sim -tm axi_vfifo_64_0x2000000_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
top/x300/coregen/axi_vfifo_64_0x2000000/implement/planAhead_ise.bat
-54
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@@ -1,54 +0,0 @@
rem (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
rem
rem This file contains confidential and proprietary information
rem of Xilinx, Inc. and is protected under U.S. and
rem international copyright and other intellectual property
rem laws.
rem
rem DISCLAIMER
rem This disclaimer is not a license and does not grant any
rem rights to the materials distributed herewith. Except as
rem otherwise provided in a valid license issued to you by
rem Xilinx, and to the maximum extent permitted by applicable
rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
rem (2) Xilinx shall not be liable (whether in contract or tort,
rem including negligence, or under any other theory of
rem liability) for any loss or damage of any kind or nature
rem related to, arising under or in connection with these
rem materials, including for any direct, or any indirect,
rem special, incidental, or consequential loss or damage
rem (including loss of data, profits, goodwill, or any type of
rem loss or damage suffered as a result of any action brought
rem by a third party) even if such damage or loss was
rem reasonably foreseeable or Xilinx had been advised of the
rem possibility of the same.
rem
rem CRITICAL APPLICATIONS
rem Xilinx products are not designed or intended to be fail-
rem safe, or for use in any application requiring fail-safe
rem performance, such as life-support or safety devices or
rem systems, Class III medical devices, nuclear facilities,
rem applications related to the deployment of airbags, or any
rem other applications that could lead to death, personal
rem injury, or severe property or environmental damage
rem (individually and collectively, "Critical
rem Applications"). Customer assumes the sole risk and
rem liability of any use of Xilinx products in Critical
rem Applications, subject only to applicable laws and
rem regulations governing limitations on product liability.
rem
rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
rem PART OF THIS FILE AT ALL TIMES.
rem -----------------------------------------------------------------------------
rem Script to synthesize and implement the Coregen FIFO Generator
rem -----------------------------------------------------------------------------
rmdir /S /Q results
mkdir results
cd results
copy ..\..\..\axi_vfifo_64_0x2000000.ngc .
planAhead -mode batch -source ..\planAhead_ise.tcl
top/x300/coregen/axi_vfifo_64_0x2000000/implement/planAhead_ise.sh
-55
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@@ -1,55 +0,0 @@
#!/bin/sh
# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#-----------------------------------------------------------------------------
# Script to synthesize and implement the Coregen FIFO Generator
#-----------------------------------------------------------------------------
rm -rf results
mkdir results
cd results
cp ../../../axi_vfifo_64_0x2000000.ngc .
planAhead -mode batch -source ../planAhead_ise.tcl
top/x300/coregen/axi_vfifo_64_0x2000000/implement/planAhead_ise.tcl
-67
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@@ -1,67 +0,0 @@
# (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
set device xc7k410tffg900-2
set projName axi_vfifo_64_0x2000000
set design axi_vfifo_64_0x2000000
set projDir [file dirname [info script]]
create_project $projName $projDir/results/$projName -part $device -force
set_property design_mode RTL [current_fileset -srcset]
set top_module axi_vfifo_64_0x2000000_exdes
add_files -norecurse {../../example_design/axi_vfifo_64_0x2000000_exdes.vhd}
add_files -norecurse {./axi_vfifo_64_0x2000000.ngc}
import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/axi_vfifo_64_0x2000000_exdes.xdc}
set_property top axi_vfifo_64_0x2000000_exdes [get_property srcset [current_run]]
synth_design
opt_design
place_design
route_design
write_sdf -rename_top_module axi_vfifo_64_0x2000000_exdes -file routed.sdf
write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module axi_vfifo_64_0x2000000_exdes routed.v
report_timing -nworst 30 -path_type full -file routed.twr
report_drc -file report.drc
write_bitstream -bitgen_options {-g UnconstrainedPins:Allow}
top/x300/coregen/axi_vfifo_64_0x2000000/implement/xst.prj
-1
View File
@@ -1 +0,0 @@
work ../example_design/axi_vfifo_64_0x2000000_exdes.vhd
top/x300/coregen/axi_vfifo_64_0x2000000/implement/xst.scr
-13
View File
@@ -1,13 +0,0 @@
run
-ifmt VHDL
-ent axi_vfifo_64_0x2000000_exdes
-p xc7k410t-ffg900-2
-ifn xst.prj
-write_timing_constraints No
-iobuf YES
-max_fanout 100
-ofn axi_vfifo_64_0x2000000_exdes
-ofmt NGC
-bus_delimiter ()
-hierarchy_separator /
-case Maintain
top/x300/coregen/axi_vfifo_64_0x2000000_flist.txt
-25
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@@ -1,25 +0,0 @@
# Output products list for <axi_vfifo_64_0x2000000>
axi_vfifo_64_0x2000000/doc/axi_vfifo_ctrl_v1_1_readme.txt
axi_vfifo_64_0x2000000/doc/axi_vfifo_ctrl_v1_1_vinfo.html
axi_vfifo_64_0x2000000/doc/pg038_axi_vfifo_ctrl.pdf
axi_vfifo_64_0x2000000/example_design/axi_vfifo_64_0x2000000_exdes.ucf
axi_vfifo_64_0x2000000/example_design/axi_vfifo_64_0x2000000_exdes.vhd
axi_vfifo_64_0x2000000/example_design/axi_vfifo_64_0x2000000_exdes.xdc
axi_vfifo_64_0x2000000/implement/implement.bat
axi_vfifo_64_0x2000000/implement/implement.sh
axi_vfifo_64_0x2000000/implement/implement_synplify.bat
axi_vfifo_64_0x2000000/implement/implement_synplify.sh
axi_vfifo_64_0x2000000/implement/planAhead_ise.bat
axi_vfifo_64_0x2000000/implement/planAhead_ise.sh
axi_vfifo_64_0x2000000/implement/planAhead_ise.tcl
axi_vfifo_64_0x2000000/implement/xst.prj
axi_vfifo_64_0x2000000/implement/xst.scr
axi_vfifo_64_0x2000000.gise
axi_vfifo_64_0x2000000.ngc
axi_vfifo_64_0x2000000.v
axi_vfifo_64_0x2000000.veo
axi_vfifo_64_0x2000000.xco
axi_vfifo_64_0x2000000.xise
axi_vfifo_64_0x2000000_flist.txt
axi_vfifo_64_0x2000000_xmdf.tcl
axi_vfifo_ctrl_v1_1_readme.txt
top/x300/coregen/axi_vfifo_64_0x2000000_xmdf.tcl
-127
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@@ -1,127 +0,0 @@
# The package naming convention is <core_name>_xmdf
package provide axi_vfifo_64_0x2000000_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::axi_vfifo_64_0x2000000_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::axi_vfifo_64_0x2000000_xmdf::xmdfInit { instance } {
# Variable containing name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name axi_vfifo_64_0x2000000
}
# ::axi_vfifo_64_0x2000000_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::axi_vfifo_64_0x2000000_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000/doc/axi_vfifo_ctrl_v1_1_readme.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000/doc/axi_vfifo_ctrl_v1_1_vinfo.html
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000/doc/pg038_axi_vfifo_ctrl.pdf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000/example_design/axi_vfifo_64_0x2000000_exdes.ucf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000/example_design/axi_vfifo_64_0x2000000_exdes.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000/example_design/axi_vfifo_64_0x2000000_exdes.xdc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000/implement/implement.bat
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000/implement/implement.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000/implement/implement_synplify.bat
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000/implement/implement_synplify.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000/implement/planAhead_ise.bat
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000/implement/planAhead_ise.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000/implement/planAhead_ise.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000/implement/xst.prj
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000/implement/xst.scr
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000.veo
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_0x2000000_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_ctrl_v1_1_readme.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module axi_vfifo_64_0x2000000
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
top/x300/coregen/axi_vfifo_64_flist.txt
-26
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@@ -1,26 +0,0 @@
# Output products list for <axi_vfifo_64>
axi_vfifo_64/doc/axi_vfifo_ctrl_v1_1_readme.txt
axi_vfifo_64/doc/axi_vfifo_ctrl_v1_1_vinfo.html
axi_vfifo_64/doc/pg038_axi_vfifo_ctrl.pdf
axi_vfifo_64/example_design/axi_vfifo_64_exdes.ucf
axi_vfifo_64/example_design/axi_vfifo_64_exdes.vhd
axi_vfifo_64/example_design/axi_vfifo_64_exdes.xdc
axi_vfifo_64/implement/implement.bat
axi_vfifo_64/implement/implement.sh
axi_vfifo_64/implement/implement_synplify.bat
axi_vfifo_64/implement/implement_synplify.sh
axi_vfifo_64/implement/planAhead_ise.bat
axi_vfifo_64/implement/planAhead_ise.sh
axi_vfifo_64/implement/planAhead_ise.tcl
axi_vfifo_64/implement/xst.prj
axi_vfifo_64/implement/xst.scr
axi_vfifo_64.gise
axi_vfifo_64.ngc
axi_vfifo_64.v
axi_vfifo_64.veo
axi_vfifo_64.xco
axi_vfifo_64.xise
axi_vfifo_64_flist.txt
axi_vfifo_64_synth.v
axi_vfifo_64_xmdf.tcl
axi_vfifo_ctrl_v1_1_readme.txt
top/x300/coregen/axi_vfifo_64_synth.v
-190
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@@ -1,190 +0,0 @@
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2012 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
/*******************************************************************************
* Generated from core with identifier: xilinx.com:ip:axi_vfifo_ctrl:1.1 *
* *
* The AXI Virtual FIFO Controller is a parameterizable number of multi *
* channel FIFO. *
*******************************************************************************/
// Synthesized Netlist Wrapper
// This file is provided to wrap around the synthesized netlist (if appropriate)
// Interfaces:
// AXI4Stream_MASTER_M_AXIS
// AXI4Stream_SLAVE_S_AXIS
// AXI4_MASTER_M_AXI
module axi_vfifo_64 (
aclk,
aresetn,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
vfifo_mm2s_channel_full,
vfifo_s2mm_channel_full,
vfifo_mm2s_channel_empty,
vfifo_mm2s_rresp_err_intr,
vfifo_s2mm_bresp_err_intr,
vfifo_s2mm_overrun_err_intr,
vfifo_idle
);
input aclk;
input aresetn;
output [0 : 0] m_axi_awid;
output [31 : 0] m_axi_awaddr;
output [7 : 0] m_axi_awlen;
output [2 : 0] m_axi_awsize;
output [1 : 0] m_axi_awburst;
output [0 : 0] m_axi_awlock;
output [3 : 0] m_axi_awcache;
output [2 : 0] m_axi_awprot;
output [3 : 0] m_axi_awqos;
output [3 : 0] m_axi_awregion;
output [0 : 0] m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [63 : 0] m_axi_wdata;
output [7 : 0] m_axi_wstrb;
output m_axi_wlast;
output [0 : 0] m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0 : 0] m_axi_bid;
input [1 : 0] m_axi_bresp;
input [0 : 0] m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
output [0 : 0] m_axi_arid;
output [31 : 0] m_axi_araddr;
output [7 : 0] m_axi_arlen;
output [2 : 0] m_axi_arsize;
output [1 : 0] m_axi_arburst;
output [0 : 0] m_axi_arlock;
output [3 : 0] m_axi_arcache;
output [2 : 0] m_axi_arprot;
output [3 : 0] m_axi_arqos;
output [3 : 0] m_axi_arregion;
output [0 : 0] m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0 : 0] m_axi_rid;
input [63 : 0] m_axi_rdata;
input [1 : 0] m_axi_rresp;
input m_axi_rlast;
input [0 : 0] m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [63 : 0] s_axis_tdata;
input [7 : 0] s_axis_tstrb;
input [7 : 0] s_axis_tkeep;
input s_axis_tlast;
input [0 : 0] s_axis_tid;
input [0 : 0] s_axis_tdest;
output m_axis_tvalid;
input m_axis_tready;
output [63 : 0] m_axis_tdata;
output [7 : 0] m_axis_tstrb;
output [7 : 0] m_axis_tkeep;
output m_axis_tlast;
output [0 : 0] m_axis_tid;
output [0 : 0] m_axis_tdest;
input [1 : 0] vfifo_mm2s_channel_full;
output [1 : 0] vfifo_s2mm_channel_full;
output [1 : 0] vfifo_mm2s_channel_empty;
output vfifo_mm2s_rresp_err_intr;
output vfifo_s2mm_bresp_err_intr;
output vfifo_s2mm_overrun_err_intr;
output [1 : 0] vfifo_idle;
// WARNING: This file provides a module declaration only, it does not support
// direct instantiation. Please use an instantiation template (VEO) to
// instantiate the IP within a design.
endmodule
top/x300/coregen/axi_vfifo_64_xmdf.tcl
-131
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@@ -1,131 +0,0 @@
# The package naming convention is <core_name>_xmdf
package provide axi_vfifo_64_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::axi_vfifo_64_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::axi_vfifo_64_xmdf::xmdfInit { instance } {
# Variable containing name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name axi_vfifo_64
}
# ::axi_vfifo_64_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::axi_vfifo_64_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64/doc/axi_vfifo_ctrl_v1_1_readme.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64/doc/axi_vfifo_ctrl_v1_1_vinfo.html
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64/doc/pg038_axi_vfifo_ctrl.pdf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64/example_design/axi_vfifo_64_exdes.ucf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64/example_design/axi_vfifo_64_exdes.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64/example_design/axi_vfifo_64_exdes.xdc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64/implement/implement.bat
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64/implement/implement.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64/implement/implement_synplify.bat
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64/implement/implement_synplify.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64/implement/planAhead_ise.bat
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64/implement/planAhead_ise.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64/implement/planAhead_ise.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64/implement/xst.prj
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64/implement/xst.scr
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64.veo
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_synth.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_64_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi_vfifo_ctrl_v1_1_readme.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module axi_vfifo_64
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
top/x300/coregen/axi_vfifo_ctrl_v1_1_readme.txt
-189
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@@ -1,189 +0,0 @@
CHANGE LOG for LogiCORE AXI Virtual FIFO Controller V1.1
Core name: Xilinx LogiCORE AXI Virtual FIFO Controller
Version: 1.1
Release: ISE 14.2 / Vivado 2012.2
Release Date: July 25, 2012
--------------------------------------------------------------------------------
Table of Contents
1. INTRODUCTION
2. DEVICE SUPPORT
3. NEW FEATURES HISTORY
4. RESOLVED ISSUES
5. KNOWN ISSUES & LIMITATIONS
6. TECHNICAL SUPPORT & FEEDBACK
7. CORE RELEASE HISTORY
8. LEGAL DISCLAIMER
--------------------------------------------------------------------------------
1. INTRODUCTION
For installation instructions for this release, please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
This file contains release notes for the Xilinx LogiCORE IP AXI Virtual FIFO Controller v1.1
solution. For the latest core updates, see the product page at:
http://www.xilinx.com/products/intellectual-property/axi_virtual_fifo_controller.htm
................................................................................
2. DEVICE SUPPORT
2.1 ISE
The following device families are supported by the core for this release.
All 7 Series devices
Zynq-7000 devices
All Virtex-6 devices
All Spartan-6 devices
2.2 Vivado
All 7 Series devices
Zynq-7000 devices
................................................................................
3. NEW FEATURES HISTORY
3.1 ISE
- First release
- ISE 14.2 software support
3.2 Vivado
- First release
- 2012.2 software support
................................................................................
4. RESOLVED ISSUES
4.1 ISE
- N/A
4.2 Vivado
- N/A
................................................................................
5. KNOWN ISSUES & LIMITATIONS
5.1 ISE
- N/A
5.2 Vivado
- N/A
The most recent information, including known issues, workarounds, and
resolutions for this version is provided in the IP Release Notes User Guide
located at
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
................................................................................
6. TECHNICAL SUPPORT & FEEDBACK
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
................................................................................
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
07/25/2012 Xilinx, Inc. 1.1 First release; ISE 14.2 and Vivado 2012.2 support.
04/24/2012 Xilinx, Inc. 1.1 First release; ISE 14.1 and Vivado 2012.1 support.
================================================================================
................................................................................
8. LEGAL DISCLAIMER
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
top/x300/coregen/chipscope_icon.xise
+1 -1
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@@ -12,7 +12,7 @@
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="chipscope_icon.ngc" xil_pn:type="FILE_NGC">
top/x300/coregen/chipscope_icon_2port.xise
+1 -1
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@@ -12,7 +12,7 @@
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="chipscope_icon_2port.ngc" xil_pn:type="FILE_NGC">
top/x300/coregen/chipscope_ila.xise
+1 -1
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@@ -12,7 +12,7 @@
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="chipscope_ila.ngc" xil_pn:type="FILE_NGC">
top/x300/coregen/chipscope_ila_64.xise
+1 -1
View File
@@ -12,7 +12,7 @@
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="chipscope_ila_64.ngc" xil_pn:type="FILE_NGC">
top/x300/coregen/coregen.cgp
+1 -1
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@@ -1,6 +1,6 @@
SET busformat = BusFormatAngleBracketNotRipped
SET designentry = Verilog
SET device = xc7k410t
SET device = xc7k325t
SET devicefamily = kintex7
SET flowvendor = Foundation_ISE
SET package = ffg900
top/x300/coregen/ddr3_32bit.xise
+1 -1
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@@ -12,7 +12,7 @@
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_addr_decode.v" xil_pn:type="FILE_VERILOG">
top/x300/coregen/fifo_xlnx_16x40_2clk.asy
-41
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@@ -1,41 +0,0 @@
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 fifo_xlnx_16x40_2clk
RECTANGLE Normal 32 32 800 4064
LINE Normal 0 112 32 112
PIN 0 112 LEFT 36
PINATTR PinName rst
PINATTR Polarity IN
LINE Normal 0 208 32 208
PIN 0 208 LEFT 36
PINATTR PinName wr_clk
PINATTR Polarity IN
LINE Wide 0 240 32 240
PIN 0 240 LEFT 36
PINATTR PinName din[39:0]
PINATTR Polarity IN
LINE Normal 0 272 32 272
PIN 0 272 LEFT 36
PINATTR PinName wr_en
PINATTR Polarity IN
LINE Normal 0 464 32 464
PIN 0 464 LEFT 36
PINATTR PinName full
PINATTR Polarity OUT
LINE Normal 832 240 800 240
PIN 832 240 RIGHT 36
PINATTR PinName rd_clk
PINATTR Polarity IN
LINE Wide 832 272 800 272
PIN 832 272 RIGHT 36
PINATTR PinName dout[39:0]
PINATTR Polarity OUT
LINE Normal 832 304 800 304
PIN 832 304 RIGHT 36
PINATTR PinName rd_en
PINATTR Polarity IN
LINE Normal 832 496 800 496
PIN 832 496 RIGHT 36
PINATTR PinName empty
PINATTR Polarity OUT
top/x300/coregen/fifo_xlnx_16x40_2clk.gise
-31
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@@ -1,31 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_xlnx_16x40_2clk.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="fifo_xlnx_16x40_2clk.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_xlnx_16x40_2clk.veo" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
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