Ashish Chaudhari
adf2da6ac7
- Fixed 10GigE firmware communication issues and sequence errors for TX - Multiple changes to help ease timing closure - Cleaned up build scripts - Switched to Xilinx ISE 14.7 as the default build tool for X300 Original-commit: 64d71dcbc5fa6790385b288de25224d386b047b0
184 lines
5.1 KiB
PHP
184 lines
5.1 KiB
PHP
#
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# Copyright 2008-2012 Ettus Research LLC
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#
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##################################################
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# Project Setup
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##################################################
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TOP_MODULE = x300
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BUILD_DIR = build-$(NAME)
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# set me in a custom makefile
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CUSTOM_SRCS =
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CUSTOM_DEFS =
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##################################################
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# Include other makefiles
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##################################################
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include ../Makefile.common
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include coregen/Makefile.srcs
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include coregen_dsp/Makefile.srcs
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include ../../lib/control/Makefile.srcs
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include ../../lib/fifo/Makefile.srcs
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include ../../lib/simple_gemac/Makefile.srcs
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include ../../lib/timing/Makefile.srcs
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include ../../lib/zpu/Makefile.srcs
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include ../../lib/wishbone/Makefile.srcs
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include ../../lib/packet_proc/Makefile.srcs
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include ../../lib/vita/Makefile.srcs
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include ../../lib/xge/Makefile.srcs
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include ../../lib/xge_interface/Makefile.srcs
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include ../../lib/dsp/Makefile.srcs
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include ../../lib/io_port2/Makefile.srcs
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include ../../lib/axi/Makefile.srcs
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promgen: $(BIT_FILE)
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promgen -w -p bin -o $(BIN_FILE) -u 0 $<
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##################################################
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# Project Properties
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##################################################
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export PROJECT_PROPERTIES := \
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family "Kintex7" \
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device $(DEVICE) \
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package ffg900 \
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speed -2 \
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top_level_module_type "HDL" \
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synthesis_tool "XST (VHDL/Verilog)" \
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simulator "ISim (VHDL/Verilog)" \
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"Preferred Language" "Verilog" \
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"Enable Message Filtering" FALSE \
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"Display Incremental Messages" FALSE
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##################################################
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# Sources
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##################################################
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TOP_SRCS = \
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x300.v \
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x300_pcie_int.v \
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x300_core.v \
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x300_zpu_config.vhd \
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soft_ctrl.v \
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dbuf_bootram.v \
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capture_ddrlvds.v \
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gen_ddrlvds.v \
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radio.v \
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bus_int.v \
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x300.ucf \
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stc3.ucf \
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timing.ucf
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ONE_GIG_SRCS = $(COREGEN_ONE_GIG_SRCS) \
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gige_phy/gige_phy_mdio.v \
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gige_phy/gige_sfp_mdio_block.v \
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gige_phy/gige_sfp_mdio_reset_sync.v \
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gige_phy/gige_sfp_mdio_sync_block.v \
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gige_phy/transceiver/gige_sfp_mdio_transceiver.v \
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gige_phy/transceiver/gige_sfp_mdio_gtwizard.v \
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gige_phy/transceiver/gige_sfp_mdio_gtwizard_gt.v \
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gige_phy/transceiver/gige_sfp_mdio_gtwizard_init.v \
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gige_phy/transceiver/gige_sfp_mdio_tx_startup_fsm.v \
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gige_phy/transceiver/gige_sfp_mdio_rx_startup_fsm.v \
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gige_phy/transceiver/gige_sfp_mdio_recclk_monitor.v \
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TEN_GIG_SRCS = $(COREGEN_TEN_GIG_SRCS) \
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ten_gige_phy/ten_gig_eth_pcs_pma_x300_top.v \
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ten_gige_phy/ten_gig_eth_pcs_pma_x300_top.ucf \
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ten_gige_phy/ten_gig_eth_pcs_pma_block.v \
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ten_gige_phy/ten_gig_eth_pcs_pma_mod.v \
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ten_gige_phy/gtx/ten_gig_eth_pcs_pma_gt_usrclk_source.v \
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ten_gige_phy/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser_gt.v \
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ten_gige_phy/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser.v \
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ifeq ($(FLOORPLAN), 1)
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ifeq ($(DEVICE), XC7K325T)
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TOP_SRCS+=floorplan_X300.ucf
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endif
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ifeq ($(DEVICE), XC7K410T)
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TOP_SRCS+=floorplan_X310.ucf
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endif
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endif
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ifdef BUILD_10G
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ETH_SRCS+=$(abspath $(TEN_GIG_SRCS)) $(XGE_SRCS) $(XGE_INTERFACE_SRCS) $(abspath x300_10ge.ucf)
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endif
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ifdef BUILD_1G
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ETH_SRCS+=$(abspath $(ONE_GIG_SRCS)) $(abspath x300_1ge.ucf)
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endif
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ifdef ETH10G_PORT0
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ETH_SRCS+=$(abspath x300_10ge_port0.ucf)
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endif
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ifdef ETH10G_PORT1
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ETH_SRCS+=$(abspath x300_10ge_port1.ucf)
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endif
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ifndef NO_DRAM_FIFOS
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DRAM_SRCS= \
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$(abspath ddr3.ucf) \
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$(COREGEN_DRAM_SRCS)
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else
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DRAM_SRCS=
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endif
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SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
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$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
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$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(COREGEN_DSP_SRCS) \
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$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
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$(ZPU_CORE_SRCS) $(WISHBONE_SRCS) \
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$(ETH_SRCS) $(IOPORT2_SRCS) $(COREGEN_CHIPSCOPE_SRCS) \
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$(PACKET_PROC_SRCS) $(VITA_SRCS) $(DSP_SRCS) $(DRAM_SRCS) $(AXI_SRCS)
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##################################################
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# Process Properties
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##################################################
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SYNTHESIZE_PROPERTIES = \
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"Number of Clock Buffers" 8 \
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"Pack I/O Registers into IOBs" Yes \
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"Optimization Effort" High \
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"Optimize Instantiated Primitives" TRUE \
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"Register Balancing" Yes \
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"Use Clock Enable" Auto \
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"Use Synchronous Reset" Auto \
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"Use Synchronous Set" Auto \
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"Verilog Macros" "$(EXTRA_DEFS) $(CUSTOM_DEFS)"
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TRANSLATE_PROPERTIES = \
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"Macro Search Path" "$(shell pwd)/coregen"
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MAP_PROPERTIES = \
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"Generate Detailed MAP Report" TRUE \
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"Allow Logic Optimization Across Hierarchy" TRUE \
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"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
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"Combinatorial Logic Optimization" TRUE \
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"Register Duplication" On \
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"Placer Effort Level" High \
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"Placer Extra Effort" Normal \
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"Enable Multi-Threading" 2 \
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"Starting Placer Cost Table (1-100)" $(shell awk 'BEGIN{srand();printf("%d", (100*rand()%100)+1)}')
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PLACE_ROUTE_PROPERTIES = \
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"Place & Route Effort Level (Overall)" High \
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"Extra Effort (Highest PAR level only)" Normal \
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"Enable Multi-Threading" 4
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STATIC_TIMING_PROPERTIES = \
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"Number of Paths in Error/Verbose Report" 10 \
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"Report Type" "Error Report"
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GEN_PROG_FILE_PROPERTIES = \
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"Configuration Rate" 6 \
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"Create Binary Configuration File" TRUE \
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"Done (Output Events)" 5 \
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"Enable Bitstream Compression" FALSE \
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"Enable Outputs (Output Events)" 6 \
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"Wait for DCI Match (Output Events)" NoWait
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SIM_MODEL_PROPERTIES = ""
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