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fpga: Multiple X300 FPGA bugfixes and enhancements

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- Fixed 10GigE firmware communication issues and sequence errors for TX
- Multiple changes to help ease timing closure
- Cleaned up build scripts
- Switched to Xilinx ISE 14.7 as the default build tool for X300


Original-commit: 64d71dcbc5fa6790385b288de25224d386b047b0
This commit is contained in:
Ashish Chaudhari
2014-09-24 18:45:31 -07:00
parent 6b7004c311
commit adf2da6ac7
275 changed files with 14057 additions and 293393 deletions
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top/x300/Makefile.x300.inc
+31 -14
View File
@@ -65,12 +65,32 @@ capture_ddrlvds.v \
gen_ddrlvds.v \
radio.v \
bus_int.v \
gige_phy.v \
gige_phy_mdio.v \
x300.ucf \
stc3.ucf \
timing.ucf
ONE_GIG_SRCS = $(COREGEN_ONE_GIG_SRCS) \
gige_phy/gige_phy_mdio.v \
gige_phy/gige_sfp_mdio_block.v \
gige_phy/gige_sfp_mdio_reset_sync.v \
gige_phy/gige_sfp_mdio_sync_block.v \
gige_phy/transceiver/gige_sfp_mdio_transceiver.v \
gige_phy/transceiver/gige_sfp_mdio_gtwizard.v \
gige_phy/transceiver/gige_sfp_mdio_gtwizard_gt.v \
gige_phy/transceiver/gige_sfp_mdio_gtwizard_init.v \
gige_phy/transceiver/gige_sfp_mdio_tx_startup_fsm.v \
gige_phy/transceiver/gige_sfp_mdio_rx_startup_fsm.v \
gige_phy/transceiver/gige_sfp_mdio_recclk_monitor.v \
TEN_GIG_SRCS = $(COREGEN_TEN_GIG_SRCS) \
ten_gige_phy/ten_gig_eth_pcs_pma_x300_top.v \
ten_gige_phy/ten_gig_eth_pcs_pma_x300_top.ucf \
ten_gige_phy/ten_gig_eth_pcs_pma_block.v \
ten_gige_phy/ten_gig_eth_pcs_pma_mod.v \
ten_gige_phy/gtx/ten_gig_eth_pcs_pma_gt_usrclk_source.v \
ten_gige_phy/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser_gt.v \
ten_gige_phy/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser.v \
ifeq ($(FLOORPLAN), 1)
ifeq ($(DEVICE), XC7K325T)
TOP_SRCS+=floorplan_X300.ucf
@@ -82,11 +102,11 @@ ifeq ($(FLOORPLAN), 1)
endif
ifdef BUILD_10G
ETH_SRCS+=$(TEN_GIG_SRCS) $(XGE_SRCS) $(XGE_INTERFACE_SRCS) $(abspath x300_10ge.ucf)
ETH_SRCS+=$(abspath $(TEN_GIG_SRCS)) $(XGE_SRCS) $(XGE_INTERFACE_SRCS) $(abspath x300_10ge.ucf)
endif
ifdef BUILD_1G
ETH_SRCS+=$(ONE_GIG_SRCS) $(abspath x300_1ge.ucf)
ETH_SRCS+=$(abspath $(ONE_GIG_SRCS)) $(abspath x300_1ge.ucf)
endif
ifdef ETH10G_PORT0
@@ -130,26 +150,23 @@ SYNTHESIZE_PROPERTIES = \
"Verilog Macros" "$(EXTRA_DEFS) $(CUSTOM_DEFS)"
TRANSLATE_PROPERTIES = \
"Macro Search Path" "$(shell pwd)/../../coregen/"
"Macro Search Path" "$(shell pwd)/coregen"
MAP_PROPERTIES = \
"Generate Detailed MAP Report" TRUE \
"Allow Logic Optimization Across Hierarchy" TRUE \
"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
"Combinatorial Logic Optimization" TRUE \
"Register Duplication" TRUE \
"Optimization Strategy (Cover Mode)" Speed \
"Map Effort Level" High \
"Extra Effort" Normal \
"Perform Timing-Driven Packing and Placement" TRUE \
"Enable Multi-Threading 2" \
"Starting Placer Cost Table (1-100)" $$(( $$RANDOM % 100 + 1 ))
#"Map to Input Functions" 4 \
"Register Duplication" On \
"Placer Effort Level" High \
"Placer Extra Effort" Normal \
"Enable Multi-Threading" 2 \
"Starting Placer Cost Table (1-100)" $(shell awk 'BEGIN{srand();printf("%d", (100*rand()%100)+1)}')
PLACE_ROUTE_PROPERTIES = \
"Place & Route Effort Level (Overall)" High \
"Extra Effort (Highest PAR level only)" Normal \
"Enable Multi-Threading 4"
"Enable Multi-Threading" 4
STATIC_TIMING_PROPERTIES = \
"Number of Paths in Error/Verbose Report" 10 \