fpga: Add BUILD_SEED variable

Adds a BUILD_SEED make variable that can be set to a 32-bit integer,
and adds an FPGA read-only register initialized by this variable.
Changing this variable will randomly affect the FPGA build results.
This can be useful when your build fails timing by a small amount,
allowing you to build again and get different results with the same
code.

For example, you could run the following to produce an FPGA build with
different timing results from the default build:

make X310_XG BUILD_SEED=123


Original-commit: 3a3a03486f9221c2e59fa6d0826c23d17730956d

top/x400/x4xx_global_regs.v

@@ -280,6 +280,13 @@ module x4xx_global_regs #(
             s_ctrlport_resp_data <= CHDR_CLK_RATE[CHDR_CLK_RATE_REG_SIZE-1:0];
           end
 
+          REG_BASE + BUILD_SEED_REG: begin
+            `ifndef BUILD_SEED
+              `define BUILD_SEED 32'b0
+            `endif
+            s_ctrlport_resp_data <= `BUILD_SEED;
+          end
+
           REG_BASE + CHDR_CLK_COUNT_REG: begin
             s_ctrlport_resp_data <= chdr_counter_reg;
           end
@@ -601,6 +608,13 @@ endmodule
 //        CHDR bus clock.
 //      </info>
 //    </register>
+//    <register name="BUILD_SEED_REG" offset="0x28" size="32" writable="false">
+//      <info>
+//        Build seed used for this compilation. Making this value readable
+//        ensures that compilation results are affected by the value in this
+//        register.
+//      </info>
+//    </register>
 //    <register name="QSFP_PORT_0_0_INFO_REG"   offset="0x60" size="32" writable="false">
 //      <info>
 //        Returns information from the QSFP0 Lane0.