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fpga: Add BUILD_SEED variable

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Adds a BUILD_SEED make variable that can be set to a 32-bit integer,
and adds an FPGA read-only register initialized by this variable.
Changing this variable will randomly affect the FPGA build results.
This can be useful when your build fails timing by a small amount,
allowing you to build again and get different results with the same
code.

For example, you could run the following to produce an FPGA build with
different timing results from the default build:

make X310_XG BUILD_SEED=123


Original-commit: 3a3a03486f9221c2e59fa6d0826c23d17730956d
This commit is contained in:
Wade Fife
2023-02-07 23:04:12 -06:00
parent 2c0fea5d1e
commit ab63d78a6c
15 changed files with 221 additions and 61 deletions
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top/x400/doc/X4XX_FPGA_left.htm
+1
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@@ -348,6 +348,7 @@
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|PPS_CTRL_REG" onclick="a('GLOBAL_REGS_REGMAP|PPS_CTRL_REG');">PPS_CTRL_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|CHDR_CLK_RATE_REG" onclick="a('GLOBAL_REGS_REGMAP|CHDR_CLK_RATE_REG');">CHDR_CLK_RATE_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|CHDR_CLK_COUNT_REG" onclick="a('GLOBAL_REGS_REGMAP|CHDR_CLK_COUNT_REG');">CHDR_CLK_COUNT_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|BUILD_SEED_REG" onclick="a('GLOBAL_REGS_REGMAP|BUILD_SEED_REG');">BUILD_SEED_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|GPS_CTRL_REG" onclick="a('GLOBAL_REGS_REGMAP|GPS_CTRL_REG');">GPS_CTRL_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|GPS_STATUS_REG" onclick="a('GLOBAL_REGS_REGMAP|GPS_STATUS_REG');">GPS_STATUS_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|DBOARD_CTRL_REG" onclick="a('GLOBAL_REGS_REGMAP|DBOARD_CTRL_REG');">DBOARD_CTRL_REG</span></p>
top/x400/doc/X4XX_FPGA_right.htm
+88 -5
View File
@@ -716,7 +716,7 @@ Prism.languages.vhdl={comment:/--.+/,"vhdl-vectors":{pattern:/\b[oxb]"[\da-f_]+"
<p>The top is defined in HDL source file common_regs.v, x4xx.v.</p>
<div class="group"><a name="P5 Content"></a><h2 class="group">P5 Content</h2>
<div class="register"><h3 class="register">Register map supplied for open-source projects</h3>
<i><BR/><BR/>"All content provided is Copyright 2022 National Instruments Corporation.
<i><BR/><BR/>"All content provided is Copyright 2023 National Instruments Corporation.
For information on NI trademark guidelines, please see <a href="http://www.ni.com/legal/trademarks/">http://www.ni.com/legal/trademarks/</a>. For the NI Patent Notice, please see <a href="http://www.ni.com/legal/patents/">http://www.ni.com/legal/patents/</a>."
</i></div><BR/>
</div>
@@ -6830,6 +6830,89 @@ Returns the count value of a free-running counter driven by the RFNoC
</div>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|BUILD_SEED_REG"></a>
<h3 class="register">Offset 0x0028: BUILD_SEED_REG Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|BUILD_SEED_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|BUILD_SEED_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|BUILD_SEED_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">BUILD_SEED_REG</td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0028</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x10000A0028
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Build seed used for this compilation. Making this value readable
ensures that compilation results are affected by the value in this
register.
</div>
</div>
<div class="register">
@@ -24241,9 +24324,9 @@ FPGA version.<BR/>
<tr valign="top">
<td class='value'>9</td>
<td class='value'>10</td>
<td class='l'>0x00000009</td>
<td class='l'>0x0000000A</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MINOR'></a>FPGA_CURRENT_VERSION_MINOR</p>
@@ -24254,9 +24337,9 @@ FPGA version.<BR/>
<tr valign="top">
<td class='value'>570827282</td>
<td class='value'>571610633</td>
<td class='l'>0x22062212</td>
<td class='l'>0x22121609</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_VERSION_LAST_MODIFIED_TIME'></a>FPGA_VERSION_LAST_MODIFIED_TIME</p>