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fpga: Add BUILD_SEED variable

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Adds a BUILD_SEED make variable that can be set to a 32-bit integer,
and adds an FPGA read-only register initialized by this variable.
Changing this variable will randomly affect the FPGA build results.
This can be useful when your build fails timing by a small amount,
allowing you to build again and get different results with the same
code.

For example, you could run the following to produce an FPGA build with
different timing results from the default build:

make X310_XG BUILD_SEED=123


Original-commit: 3a3a03486f9221c2e59fa6d0826c23d17730956d
This commit is contained in:
Wade Fife
2023-02-07 23:04:12 -06:00
parent 2c0fea5d1e
commit ab63d78a6c
15 changed files with 221 additions and 61 deletions
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top/x300/Makefile
+13 -9
View File
@@ -21,11 +21,14 @@
CREATE_LVBITX=python ../../lib/io_port2/create-lvbitx.py
GIGE_DEFS=BUILD_1G=1 SFP0_1GBE=1 SFP1_1GBE=1 $(OPTIONS)
HG_DEFS=BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 $(OPTIONS)
XG_DEFS=BUILD_10G=1 SFP0_10GBE=1 SFP1_10GBE=1 $(OPTIONS)
HA_DEFS=BUILD_1G=1 BUILD_AURORA=1 SFP0_1GBE=1 SFP1_AURORA=1 $(OPTIONS)
XA_DEFS=BUILD_10G=1 BUILD_AURORA=1 SFP0_10GBE=1 SFP1_AURORA=1 $(OPTIONS)
# Initialize a build seed. This can be changed to randomly affect build results.
BUILD_SEED ?= 0
GIGE_DEFS=BUILD_1G=1 SFP0_1GBE=1 SFP1_1GBE=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
HG_DEFS=BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
XG_DEFS=BUILD_10G=1 SFP0_10GBE=1 SFP1_10GBE=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
HA_DEFS=BUILD_1G=1 BUILD_AURORA=1 SFP0_1GBE=1 SFP1_AURORA=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
XA_DEFS=BUILD_10G=1 BUILD_AURORA=1 SFP0_10GBE=1 SFP1_AURORA=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
# Set build option (check RTL, run synthesis, or do a full build)
ifndef TARGET
@@ -146,9 +149,10 @@ help: ##Show this help message.
##
##Supported Options
##-----------------
##GUI=1 Launch the build in the Vivado GUI.
##CHECK=1 Launch the syntax checker instead of building a bitfile.
##SYNTH=1 Launch the build but stop after synthesis.
##TOP=<module> Specify a top module for syntax checking. (Optional. Default is the bitfile top)
##GUI=1 Launch the build in the Vivado GUI.
##CHECK=1 Launch the syntax checker instead of building a bitfile.
##SYNTH=1 Launch the build but stop after synthesis.
##BUILD_SEED=<N> Build seed to used to affect build results. (Default is 0)
##TOP=<module> Specify a top module for syntax checking. (Default is the bitfile top)
.PHONY: all clean cleanall help
top/x300/bus_int.v
+9 -1
View File
@@ -175,11 +175,12 @@ module bus_int #(
localparam RB_NUM_TIMEKEEPERS = 8'd12;
localparam RB_FP_GPIO_SRC = 8'd13;
localparam RB_DEVICE_ID = 8'd14;
localparam RB_BUILD_SEED = 8'd15;
localparam RB_TA_SFP0_BASE = SR_TA_SFP0_BASE;
localparam RB_TA_SFP1_BASE = SR_TA_SFP1_BASE;
localparam COMPAT_MAJOR = 16'h0027;
localparam COMPAT_MINOR = 16'h0001;
localparam COMPAT_MINOR = 16'h0002;
localparam NUM_TIMEKEEPERS = 1;
// Include the RFNoC image core header file
@@ -457,8 +458,15 @@ module bus_int #(
`else
RB_ETH_TYPE1: rb_data = {32'h0};
`endif
`endif
`ifndef GIT_HASH
`define GIT_HASH 32'h0BADC0DE
`endif
RB_GIT_HASH: rb_data = `GIT_HASH;
`ifndef BUILD_SEED
`define BUILD_SEED 32'b0
`endif
RB_BUILD_SEED: rb_data = `BUILD_SEED;
RB_XADC_VALS: rb_data = xadc_readback;
RB_FP_GPIO_SRC: rb_data = fp_gpio_src;
SR_BASE_TIME: begin