fpga: Add BUILD_SEED variable
Adds a BUILD_SEED make variable that can be set to a 32-bit integer, and adds an FPGA read-only register initialized by this variable. Changing this variable will randomly affect the FPGA build results. This can be useful when your build fails timing by a small amount, allowing you to build again and get different results with the same code. For example, you could run the following to produce an FPGA build with different timing results from the default build: make X310_XG BUILD_SEED=123 Original-commit: 3a3a03486f9221c2e59fa6d0826c23d17730956d
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+16
-12
@@ -23,15 +23,18 @@
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# Uncomment this line to add four example Aurora loopback lanes on the QSFP NPIO bus.
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# OPTIONS += QSFP_LANES=4
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# Initialize a build seed. This can be changed to randomly affect build results.
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BUILD_SEED ?= 0
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# Additional definitions specific to the various targets:
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WX_DEFS=SFP0_WR=1 SFP1_10GBE=1 BUILD_WR=1 BUILD_10G=1 $(OPTIONS)
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HG_DEFS=SFP0_1GBE=1 SFP1_10GBE=1 BUILD_1G=1 BUILD_10G=1 $(OPTIONS)
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XG_DEFS=SFP0_10GBE=1 SFP1_10GBE=1 BUILD_10G=1 $(OPTIONS)
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HA_DEFS=SFP0_1GBE=1 SFP1_AURORA=1 BUILD_1G=1 BUILD_AURORA=1 $(OPTIONS)
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XA_DEFS=SFP0_10GBE=1 SFP1_AURORA=1 BUILD_10G=1 BUILD_AURORA=1 $(OPTIONS)
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AA_DEFS=SFP0_AURORA=1 SFP1_AURORA=1 BUILD_AURORA=1 $(OPTIONS)
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XQ_DEFS=SFP0_WR=1 QSFP_10GBE=1 BUILD_WR=1 BUILD_10G=1 QSFP_LANES=2 $(OPTIONS)
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AQ_DEFS=SFP0_10GBE=1 SFP1_10GBE=1 QSFP_AURORA=1 BUILD_10G=1 BUILD_AURORA=1 QSFP_LANES=4 $(OPTIONS)
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WX_DEFS=SFP0_WR=1 SFP1_10GBE=1 BUILD_WR=1 BUILD_10G=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
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HG_DEFS=SFP0_1GBE=1 SFP1_10GBE=1 BUILD_1G=1 BUILD_10G=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
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XG_DEFS=SFP0_10GBE=1 SFP1_10GBE=1 BUILD_10G=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
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HA_DEFS=SFP0_1GBE=1 SFP1_AURORA=1 BUILD_1G=1 BUILD_AURORA=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
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XA_DEFS=SFP0_10GBE=1 SFP1_AURORA=1 BUILD_10G=1 BUILD_AURORA=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
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AA_DEFS=SFP0_AURORA=1 SFP1_AURORA=1 BUILD_AURORA=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
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XQ_DEFS=SFP0_WR=1 QSFP_10GBE=1 BUILD_WR=1 BUILD_10G=1 QSFP_LANES=2 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
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AQ_DEFS=SFP0_10GBE=1 SFP1_10GBE=1 QSFP_AURORA=1 BUILD_10G=1 BUILD_AURORA=1 QSFP_LANES=4 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
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# Defaults specific to the various targets:
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N300_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n300_rfnoc_image_core.v) DEFAULT_EDGE_FILE=$(abspath n300_static_router.hex)
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@@ -200,9 +203,10 @@ help: ##Show this help message.
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##
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##Supported Options
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##-----------------
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##GUI=1 Launch the build in the Vivado GUI.
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##CHECK=1 Launch the syntax checker instead of building a bitfile.
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##SYNTH=1 Launch the build but stop after synthesis.
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##TOP=<module> Specify a top module for syntax checking. (Optional. Default is the bitfile top)
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##GUI=1 Launch the build in the Vivado GUI.
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##CHECK=1 Launch the syntax checker instead of building a bitfile.
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##SYNTH=1 Launch the build but stop after synthesis.
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##BUILD_SEED=<N> Build seed to used to affect build results. (Default is 0)
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##TOP=<module> Specify a top module for syntax checking. (Default is the bitfile top)
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.PHONY: all clean cleanall help
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+12
-3
@@ -211,7 +211,7 @@ module n3xx_core #(
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/////////////////////////////////////////////////////////////////////////////////
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localparam [15:0] COMPAT_MAJOR = 16'd8;
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localparam [15:0] COMPAT_MINOR = 16'd1;
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localparam [15:0] COMPAT_MINOR = 16'd2;
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/////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////
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@@ -244,6 +244,7 @@ module n3xx_core #(
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localparam REG_FP_GPIO_MASTER = REG_BASE_MISC + 14'h30;
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localparam REG_FP_GPIO_RADIO_SRC = REG_BASE_MISC + 14'h34;
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localparam REG_NUM_TIMEKEEPERS = REG_BASE_MISC + 14'h48;
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localparam REG_BUILD_SEED = REG_BASE_MISC + 14'h4C;
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localparam NUM_TIMEKEEPERS = 1;
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@@ -543,11 +544,12 @@ module n3xx_core #(
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REG_DATESTAMP:
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cp_glob_resp_data <= build_datestamp;
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REG_GIT_HASH:
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REG_GIT_HASH: begin
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`ifndef GIT_HASH
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`define GIT_HASH 32'h0BADC0DE
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`define GIT_HASH 32'h0BADC0DE
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`endif
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cp_glob_resp_data <= `GIT_HASH;
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end
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REG_FP_GPIO_MASTER:
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cp_glob_resp_data <= fp_gpio_master_reg;
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@@ -588,6 +590,13 @@ module n3xx_core #(
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REG_NUM_TIMEKEEPERS:
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cp_glob_resp_data <= NUM_TIMEKEEPERS;
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REG_BUILD_SEED: begin
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`ifndef BUILD_SEED
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`define BUILD_SEED 32'b0
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`endif
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cp_glob_resp_data <= `BUILD_SEED;
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end
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default: begin
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// Don't acknowledge if the address doesn't match
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cp_glob_resp_ack <= 1'b0;
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