fpga: Add BUILD_SEED variable
Adds a BUILD_SEED make variable that can be set to a 32-bit integer, and adds an FPGA read-only register initialized by this variable. Changing this variable will randomly affect the FPGA build results. This can be useful when your build fails timing by a small amount, allowing you to build again and get different results with the same code. For example, you could run the following to produce an FPGA build with different timing results from the default build: make X310_XG BUILD_SEED=123 Original-commit: 3a3a03486f9221c2e59fa6d0826c23d17730956d
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+12
-3
@@ -193,7 +193,7 @@ module e320_core #(
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/////////////////////////////////////////////////////////////////////////////////
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localparam [15:0] COMPAT_MAJOR = 16'd6;
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localparam [15:0] COMPAT_MINOR = 16'd1;
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localparam [15:0] COMPAT_MINOR = 16'd2;
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/////////////////////////////////////////////////////////////////////////////////
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@@ -231,6 +231,7 @@ module e320_core #(
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localparam REG_DBOARD_CTRL = REG_BASE_MISC + 14'h40;
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localparam REG_DBOARD_STATUS = REG_BASE_MISC + 14'h44;
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localparam REG_NUM_TIMEKEEPERS = REG_BASE_MISC + 14'h48;
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localparam REG_BUILD_SEED = REG_BASE_MISC + 14'h4C;
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localparam NUM_TIMEKEEPERS = 1;
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@@ -486,11 +487,12 @@ module e320_core #(
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REG_DATESTAMP:
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cp_glob_resp_data <= build_datestamp;
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REG_GIT_HASH:
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REG_GIT_HASH: begin
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`ifndef GIT_HASH
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`define GIT_HASH 32'h0BADC0DE
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`define GIT_HASH 32'h0BADC0DE
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`endif
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cp_glob_resp_data <= `GIT_HASH;
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end
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REG_SCRATCH:
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cp_glob_resp_data <= scratch_reg;
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@@ -529,6 +531,13 @@ module e320_core #(
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REG_NUM_TIMEKEEPERS:
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cp_glob_resp_data <= NUM_TIMEKEEPERS;
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REG_BUILD_SEED: begin
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`ifndef BUILD_SEED
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`define BUILD_SEED 32'b0
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`endif
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cp_glob_resp_data <= `BUILD_SEED;
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end
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default: begin
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// Don't acknowledge if the address doesn't match
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cp_glob_resp_ack <= 1'b0;
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