fpga: Add BUILD_SEED variable
Adds a BUILD_SEED make variable that can be set to a 32-bit integer, and adds an FPGA read-only register initialized by this variable. Changing this variable will randomly affect the FPGA build results. This can be useful when your build fails timing by a small amount, allowing you to build again and get different results with the same code. For example, you could run the following to produce an FPGA build with different timing results from the default build: make X310_XG BUILD_SEED=123 Original-commit: 3a3a03486f9221c2e59fa6d0826c23d17730956d
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-7
@@ -14,9 +14,12 @@
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## build/usrp_<product>_fpga_<image_type>.dts: Device tree source file
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## build/usrp_<product>_fpga_<image_type>.rpt: Build report (includes utilization and timing summary)
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1G_DEFS=SFP_1GBE=1 BUILD_1G=1 $(OPTIONS)
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XG_DEFS=SFP_10GBE=1 BUILD_10G=1 $(OPTIONS)
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AA_DEFS=SFP_AURORA=1 BUILD_AURORA=1 $(OPTIONS)
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# Initialize a build seed. This can be changed to randomly affect build results.
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BUILD_SEED ?= 0
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1G_DEFS=SFP_1GBE=1 BUILD_1G=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
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XG_DEFS=SFP_10GBE=1 BUILD_10G=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
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AA_DEFS=SFP_AURORA=1 BUILD_AURORA=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
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# Set build option (check RTL, run synthesis, or do a full build)
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ifndef TARGET
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@@ -97,9 +100,10 @@ help: ##Show this help message.
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##
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##Supported Options
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##-----------------
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##GUI=1 Launch the build in the Vivado GUI.
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##CHECK=1 Launch the syntax checker instead of building a bitfile.
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##SYNTH=1 Launch the build but stop after synthesis.
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##TOP=<module> Specify a top module for syntax checking. (Optional. Default is the bitfile top)
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##GUI=1 Launch the build in the Vivado GUI.
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##CHECK=1 Launch the syntax checker instead of building a bitfile.
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##SYNTH=1 Launch the build but stop after synthesis.
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##BUILD_SEED=<N> Build seed to used to affect build results. (Default is 0)
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##TOP=<module> Specify a top module for syntax checking. (Default is the bitfile top)
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.PHONY: all clean cleanall help
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