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fpga: Add BUILD_SEED variable

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Adds a BUILD_SEED make variable that can be set to a 32-bit integer,
and adds an FPGA read-only register initialized by this variable.
Changing this variable will randomly affect the FPGA build results.
This can be useful when your build fails timing by a small amount,
allowing you to build again and get different results with the same
code.

For example, you could run the following to produce an FPGA build with
different timing results from the default build:

make X310_XG BUILD_SEED=123


Original-commit: 3a3a03486f9221c2e59fa6d0826c23d17730956d
This commit is contained in:
Wade Fife
2023-02-07 23:04:12 -06:00
parent 2c0fea5d1e
commit ab63d78a6c
15 changed files with 221 additions and 61 deletions
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top/e320/Makefile
+11 -7
View File
@@ -14,9 +14,12 @@
## build/usrp_<product>_fpga_<image_type>.dts: Device tree source file
## build/usrp_<product>_fpga_<image_type>.rpt: Build report (includes utilization and timing summary)
1G_DEFS=SFP_1GBE=1 BUILD_1G=1 $(OPTIONS)
XG_DEFS=SFP_10GBE=1 BUILD_10G=1 $(OPTIONS)
AA_DEFS=SFP_AURORA=1 BUILD_AURORA=1 $(OPTIONS)
# Initialize a build seed. This can be changed to randomly affect build results.
BUILD_SEED ?= 0
1G_DEFS=SFP_1GBE=1 BUILD_1G=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
XG_DEFS=SFP_10GBE=1 BUILD_10G=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
AA_DEFS=SFP_AURORA=1 BUILD_AURORA=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
# Set build option (check RTL, run synthesis, or do a full build)
ifndef TARGET
@@ -97,9 +100,10 @@ help: ##Show this help message.
##
##Supported Options
##-----------------
##GUI=1 Launch the build in the Vivado GUI.
##CHECK=1 Launch the syntax checker instead of building a bitfile.
##SYNTH=1 Launch the build but stop after synthesis.
##TOP=<module> Specify a top module for syntax checking. (Optional. Default is the bitfile top)
##GUI=1 Launch the build in the Vivado GUI.
##CHECK=1 Launch the syntax checker instead of building a bitfile.
##SYNTH=1 Launch the build but stop after synthesis.
##BUILD_SEED=<N> Build seed to used to affect build results. (Default is 0)
##TOP=<module> Specify a top module for syntax checking. (Default is the bitfile top)
.PHONY: all clean cleanall help
top/e320/e320_core.v
+12 -3
View File
@@ -193,7 +193,7 @@ module e320_core #(
/////////////////////////////////////////////////////////////////////////////////
localparam [15:0] COMPAT_MAJOR = 16'd6;
localparam [15:0] COMPAT_MINOR = 16'd1;
localparam [15:0] COMPAT_MINOR = 16'd2;
/////////////////////////////////////////////////////////////////////////////////
@@ -231,6 +231,7 @@ module e320_core #(
localparam REG_DBOARD_CTRL = REG_BASE_MISC + 14'h40;
localparam REG_DBOARD_STATUS = REG_BASE_MISC + 14'h44;
localparam REG_NUM_TIMEKEEPERS = REG_BASE_MISC + 14'h48;
localparam REG_BUILD_SEED = REG_BASE_MISC + 14'h4C;
localparam NUM_TIMEKEEPERS = 1;
@@ -486,11 +487,12 @@ module e320_core #(
REG_DATESTAMP:
cp_glob_resp_data <= build_datestamp;
REG_GIT_HASH:
REG_GIT_HASH: begin
`ifndef GIT_HASH
`define GIT_HASH 32'h0BADC0DE
`define GIT_HASH 32'h0BADC0DE
`endif
cp_glob_resp_data <= `GIT_HASH;
end
REG_SCRATCH:
cp_glob_resp_data <= scratch_reg;
@@ -529,6 +531,13 @@ module e320_core #(
REG_NUM_TIMEKEEPERS:
cp_glob_resp_data <= NUM_TIMEKEEPERS;
REG_BUILD_SEED: begin
`ifndef BUILD_SEED
`define BUILD_SEED 32'b0
`endif
cp_glob_resp_data <= `BUILD_SEED;
end
default: begin
// Don't acknowledge if the address doesn't match
cp_glob_resp_ack <= 1'b0;