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rtl: remove inferred CHDR conversion latches

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Give curr_word a complete combinational assignment and use blocking assignments in chdr_16sc_to_12sc.

This removes the two 64-bit latch banks and the resulting bogus inferred-clock timing endpoints while preserving all legal FSM-state behavior.
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miegl
2026-08-25 22:36:27 +02:00
parent 286cde0a8d
commit a95cce3d20
1 changed files with 13 additions and 8 deletions
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lib/vita_200/chdr_16sc_to_12sc.v
+13 -8
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@@ -224,16 +224,21 @@ module chdr_16sc_to_12sc
// //
// Mux for current word // Mux for current word
// //
always @(*) always @(*) begin
// Default assignment prevents latch inference for illegal/unhandled states.
curr_word = 64'd0;
case(state) case(state)
HEADER: curr_word <= {i_tdata[63:48], output_chdr_pkt_size, set_sid ? HEADER: curr_word = {i_tdata[63:48], output_chdr_pkt_size, set_sid ?
{i_tdata[15:0], new_sid_dst[15:0]}:i_tdata[31:0]}; {i_tdata[15:0], new_sid_dst[15:0]} : i_tdata[31:0]};
TIME: curr_word <= i_tdata; TIME: curr_word = i_tdata;
SAMPLE1: curr_word <= {q0,i0,q1, i1, 16'b0}; SAMPLE1: curr_word = {q0, i0, q1, i1, 16'b0};
SAMPLE2: curr_word <= {buff[63:16], q0, i0[11:8]}; SAMPLE2: curr_word = {buff[63:16], q0, i0[11:8]};
SAMPLE3: curr_word <= {buff[63:32], q0, i0,q1[11:4]}; SAMPLE3: curr_word = {buff[63:32], q0, i0, q1[11:4]};
SAMPLE4: curr_word <= {buff[63:48], q0, i0, q1, i1}; SAMPLE4: curr_word = {buff[63:48], q0, i0, q1, i1};
default: curr_word = 64'd0;
endcase endcase
end
assign o_tdata = buff_tvalid ? buff : curr_word; assign o_tdata = buff_tvalid ? buff : curr_word;
assign o_tvalid = (state == HEADER && buff_tvalid) || (i_tvalid && assign o_tvalid = (state == HEADER && buff_tvalid) || (i_tvalid &&