From a95cce3d2064a0ab05e3004c81516660c97b0f30 Mon Sep 17 00:00:00 2001 From: Josef Miegl Date: Tue, 25 Aug 2026 22:36:27 +0200 Subject: [PATCH] rtl: remove inferred CHDR conversion latches Give curr_word a complete combinational assignment and use blocking assignments in chdr_16sc_to_12sc. This removes the two 64-bit latch banks and the resulting bogus inferred-clock timing endpoints while preserving all legal FSM-state behavior. --- lib/vita_200/chdr_16sc_to_12sc.v | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/lib/vita_200/chdr_16sc_to_12sc.v b/lib/vita_200/chdr_16sc_to_12sc.v index 23c66ac..ec866d9 100644 --- a/lib/vita_200/chdr_16sc_to_12sc.v +++ b/lib/vita_200/chdr_16sc_to_12sc.v @@ -224,16 +224,21 @@ module chdr_16sc_to_12sc // // Mux for current word // - always @(*) + always @(*) begin + // Default assignment prevents latch inference for illegal/unhandled states. + curr_word = 64'd0; + case(state) - HEADER: curr_word <= {i_tdata[63:48], output_chdr_pkt_size, set_sid ? - {i_tdata[15:0], new_sid_dst[15:0]}:i_tdata[31:0]}; - TIME: curr_word <= i_tdata; - SAMPLE1: curr_word <= {q0,i0,q1, i1, 16'b0}; - SAMPLE2: curr_word <= {buff[63:16], q0, i0[11:8]}; - SAMPLE3: curr_word <= {buff[63:32], q0, i0,q1[11:4]}; - SAMPLE4: curr_word <= {buff[63:48], q0, i0, q1, i1}; + HEADER: curr_word = {i_tdata[63:48], output_chdr_pkt_size, set_sid ? + {i_tdata[15:0], new_sid_dst[15:0]} : i_tdata[31:0]}; + TIME: curr_word = i_tdata; + SAMPLE1: curr_word = {q0, i0, q1, i1, 16'b0}; + SAMPLE2: curr_word = {buff[63:16], q0, i0[11:8]}; + SAMPLE3: curr_word = {buff[63:32], q0, i0, q1[11:4]}; + SAMPLE4: curr_word = {buff[63:48], q0, i0, q1, i1}; + default: curr_word = 64'd0; endcase + end assign o_tdata = buff_tvalid ? buff : curr_word; assign o_tvalid = (state == HEADER && buff_tvalid) || (i_tvalid &&